FR2944645B1 - Procede d'amincissement d'un substrat silicium sur isolant - Google Patents

Procede d'amincissement d'un substrat silicium sur isolant

Info

Publication number
FR2944645B1
FR2944645B1 FR0952581A FR0952581A FR2944645B1 FR 2944645 B1 FR2944645 B1 FR 2944645B1 FR 0952581 A FR0952581 A FR 0952581A FR 0952581 A FR0952581 A FR 0952581A FR 2944645 B1 FR2944645 B1 FR 2944645B1
Authority
FR
France
Prior art keywords
slitting
insulation
silicon substrate
silicon
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0952581A
Other languages
English (en)
Other versions
FR2944645A1 (fr
Inventor
Patrick Reynaud
Ludovic Ecarnot
Khalid Radouane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0952581A priority Critical patent/FR2944645B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to PCT/EP2010/055198 priority patent/WO2010122023A2/fr
Priority to SG2011061926A priority patent/SG173873A1/en
Priority to KR1020117024745A priority patent/KR101667961B1/ko
Priority to CN201080016933.XA priority patent/CN102396051B/zh
Priority to EP10713998A priority patent/EP2422360A2/fr
Priority to JP2012506470A priority patent/JP5619872B2/ja
Priority to US13/257,901 priority patent/US8962492B2/en
Publication of FR2944645A1 publication Critical patent/FR2944645A1/fr
Application granted granted Critical
Publication of FR2944645B1 publication Critical patent/FR2944645B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Thin Film Transistor (AREA)
FR0952581A 2009-04-21 2009-04-21 Procede d'amincissement d'un substrat silicium sur isolant Active FR2944645B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR0952581A FR2944645B1 (fr) 2009-04-21 2009-04-21 Procede d'amincissement d'un substrat silicium sur isolant
SG2011061926A SG173873A1 (en) 2009-04-21 2010-04-20 Method to thin a silicon-on-insulator substrate
KR1020117024745A KR101667961B1 (ko) 2009-04-21 2010-04-20 실리콘-온-인슐레이터 기판의 씨닝 방법
CN201080016933.XA CN102396051B (zh) 2009-04-21 2010-04-20 使绝缘体上硅衬底减薄的方法
PCT/EP2010/055198 WO2010122023A2 (fr) 2009-04-21 2010-04-20 Procédé d'amincissement d'un substrat silicium sur isolant
EP10713998A EP2422360A2 (fr) 2009-04-21 2010-04-20 Procédé d'amincissement d'un substrat silicium sur isolant
JP2012506470A JP5619872B2 (ja) 2009-04-21 2010-04-20 シリコンオンインシュレータ基板を薄化する方法
US13/257,901 US8962492B2 (en) 2009-04-21 2010-04-20 Method to thin a silicon-on-insulator substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0952581A FR2944645B1 (fr) 2009-04-21 2009-04-21 Procede d'amincissement d'un substrat silicium sur isolant

Publications (2)

Publication Number Publication Date
FR2944645A1 FR2944645A1 (fr) 2010-10-22
FR2944645B1 true FR2944645B1 (fr) 2011-09-16

Family

ID=41319649

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0952581A Active FR2944645B1 (fr) 2009-04-21 2009-04-21 Procede d'amincissement d'un substrat silicium sur isolant

Country Status (8)

Country Link
US (1) US8962492B2 (fr)
EP (1) EP2422360A2 (fr)
JP (1) JP5619872B2 (fr)
KR (1) KR101667961B1 (fr)
CN (1) CN102396051B (fr)
FR (1) FR2944645B1 (fr)
SG (1) SG173873A1 (fr)
WO (1) WO2010122023A2 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2999801B1 (fr) 2012-12-14 2014-12-26 Soitec Silicon On Insulator Procede de fabrication d'une structure
CN104851792B (zh) * 2014-02-14 2017-09-22 北大方正集团有限公司 钝化的处理方法
JP6107709B2 (ja) * 2014-03-10 2017-04-05 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP6036732B2 (ja) * 2014-03-18 2016-11-30 信越半導体株式会社 貼り合わせウェーハの製造方法
CN104882362A (zh) * 2015-05-25 2015-09-02 上海华力微电子有限公司 氧化硅层清洗工艺及改善阱注入前光刻残留的方法
JP2018121070A (ja) * 2018-03-23 2018-08-02 富士通セミコンダクター株式会社 半導体装置の製造方法
CN108598083A (zh) * 2018-06-08 2018-09-28 上海华虹宏力半导体制造有限公司 浮栅的制备方法及半导体结构的制备方法
FR3103055A1 (fr) * 2019-11-08 2021-05-14 Soitec Procédé de finition d’une couche semi-conductrice monocristalline transférée sur un substrat receveur
CN114664657A (zh) * 2021-10-29 2022-06-24 中国科学院上海微系统与信息技术研究所 一种晶圆表面处理方法
CN114334792A (zh) * 2021-10-29 2022-04-12 上海新昇半导体科技有限公司 Soi结构的半导体硅晶圆及其制备方法
CN114121612B (zh) * 2022-01-27 2022-04-29 广东省大湾区集成电路与系统应用研究院 一种fdsoi硅外延生长工艺优化方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07183477A (ja) * 1993-12-22 1995-07-21 Nec Corp 半導体基板の製造方法
JPH09115869A (ja) * 1995-08-10 1997-05-02 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
JPH11307507A (ja) * 1998-04-21 1999-11-05 Super Silicon Kenkyusho:Kk ウエハ乾燥装置
US7749910B2 (en) * 2001-07-04 2010-07-06 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
US6916744B2 (en) * 2002-12-19 2005-07-12 Applied Materials, Inc. Method and apparatus for planarization of a material by growing a sacrificial film with customized thickness profile
JP2004259970A (ja) * 2003-02-26 2004-09-16 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
FR2852143B1 (fr) * 2003-03-04 2005-10-14 Soitec Silicon On Insulator Procede de traitement preventif de la couronne d'une tranche multicouche
US7256104B2 (en) * 2003-05-21 2007-08-14 Canon Kabushiki Kaisha Substrate manufacturing method and substrate processing apparatus
JP2005005674A (ja) * 2003-05-21 2005-01-06 Canon Inc 基板製造方法及び基板処理装置
JP4416108B2 (ja) 2003-11-17 2010-02-17 株式会社ディスコ 半導体ウェーハの製造方法
FR2880186B1 (fr) 2004-12-24 2007-07-20 Soitec Silicon On Insulator Procede de traitement d'une surface de plaquette
FR2884647B1 (fr) * 2005-04-15 2008-02-22 Soitec Silicon On Insulator Traitement de plaques de semi-conducteurs

Also Published As

Publication number Publication date
CN102396051A (zh) 2012-03-28
WO2010122023A2 (fr) 2010-10-28
KR101667961B1 (ko) 2016-10-20
SG173873A1 (en) 2011-10-28
US8962492B2 (en) 2015-02-24
CN102396051B (zh) 2015-05-06
JP5619872B2 (ja) 2014-11-05
FR2944645A1 (fr) 2010-10-22
EP2422360A2 (fr) 2012-02-29
US20120009797A1 (en) 2012-01-12
WO2010122023A3 (fr) 2010-12-16
KR20110137806A (ko) 2011-12-23
JP2012524420A (ja) 2012-10-11

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