FR2880186B1 - Procede de traitement d'une surface de plaquette - Google Patents
Procede de traitement d'une surface de plaquetteInfo
- Publication number
- FR2880186B1 FR2880186B1 FR0413930A FR0413930A FR2880186B1 FR 2880186 B1 FR2880186 B1 FR 2880186B1 FR 0413930 A FR0413930 A FR 0413930A FR 0413930 A FR0413930 A FR 0413930A FR 2880186 B1 FR2880186 B1 FR 2880186B1
- Authority
- FR
- France
- Prior art keywords
- processing
- wafer surface
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0413930A FR2880186B1 (fr) | 2004-12-24 | 2004-12-24 | Procede de traitement d'une surface de plaquette |
| US11/145,455 US7919391B2 (en) | 2004-12-24 | 2005-06-02 | Methods for preparing a bonding surface of a semiconductor wafer |
| PCT/EP2005/057003 WO2006069945A1 (fr) | 2004-12-24 | 2005-12-21 | Procédé de traitement d'une surface de plaquette |
| JP2007547504A JP2008526006A (ja) | 2004-12-24 | 2005-12-21 | ウェーハ表面の処理方法 |
| EP05823924A EP1829099A1 (fr) | 2004-12-24 | 2005-12-21 | Procede de traitement d'une surface de plaquette |
| KR1020077014457A KR100884672B1 (ko) | 2004-12-24 | 2005-12-21 | 웨이퍼 표면 처리 방법 |
| CNB2005800448464A CN100568484C (zh) | 2004-12-24 | 2005-12-21 | 晶片表面处理方法 |
| TW094145970A TWI333258B (en) | 2004-12-24 | 2005-12-23 | A method of treating a wafer surface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0413930A FR2880186B1 (fr) | 2004-12-24 | 2004-12-24 | Procede de traitement d'une surface de plaquette |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2880186A1 FR2880186A1 (fr) | 2006-06-30 |
| FR2880186B1 true FR2880186B1 (fr) | 2007-07-20 |
Family
ID=34953368
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR0413930A Expired - Fee Related FR2880186B1 (fr) | 2004-12-24 | 2004-12-24 | Procede de traitement d'une surface de plaquette |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN100568484C (fr) |
| FR (1) | FR2880186B1 (fr) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2944645B1 (fr) * | 2009-04-21 | 2011-09-16 | Soitec Silicon On Insulator | Procede d'amincissement d'un substrat silicium sur isolant |
| FR2992772B1 (fr) | 2012-06-28 | 2014-07-04 | Soitec Silicon On Insulator | Procede de realisation de structure composite avec collage de type metal/metal |
| CN105118804B (zh) * | 2015-09-29 | 2018-04-13 | 厦门大学 | 超薄硅薄膜钝化制备绝缘体上锗的方法 |
| CN110459555A (zh) * | 2019-08-29 | 2019-11-15 | 长春长光圆辰微电子技术有限公司 | 背照式图像传感器晶圆边缘无硅膜缺陷的工艺制程方法 |
| CN112670170B (zh) * | 2020-12-30 | 2024-02-02 | 长春长光圆辰微电子技术有限公司 | 一种提高硅片键合力的方法 |
| FR3136108B1 (fr) * | 2022-05-25 | 2024-04-19 | Commissariat Energie Atomique | Procédé de collage direct assisté par des élements cationiques |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3187109B2 (ja) * | 1992-01-31 | 2001-07-11 | キヤノン株式会社 | 半導体部材およびその製造方法 |
| JP3697106B2 (ja) * | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
| US7235461B2 (en) * | 2003-04-29 | 2007-06-26 | S.O.I.Tec Silicon On Insulator Technologies | Method for bonding semiconductor structures together |
-
2004
- 2004-12-24 FR FR0413930A patent/FR2880186B1/fr not_active Expired - Fee Related
-
2005
- 2005-12-21 CN CNB2005800448464A patent/CN100568484C/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN100568484C (zh) | 2009-12-09 |
| FR2880186A1 (fr) | 2006-06-30 |
| CN101088154A (zh) | 2007-12-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| CD | Change of name or company name |
Owner name: SOITEC, FR Effective date: 20120423 |
|
| ST | Notification of lapse |
Effective date: 20130830 |