FR2907966B1 - Procede de fabrication d'un substrat. - Google Patents

Procede de fabrication d'un substrat.

Info

Publication number
FR2907966B1
FR2907966B1 FR0609466A FR0609466A FR2907966B1 FR 2907966 B1 FR2907966 B1 FR 2907966B1 FR 0609466 A FR0609466 A FR 0609466A FR 0609466 A FR0609466 A FR 0609466A FR 2907966 B1 FR2907966 B1 FR 2907966B1
Authority
FR
France
Prior art keywords
producing
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0609466A
Other languages
English (en)
Other versions
FR2907966A1 (fr
Inventor
Konstantin Bourdelle
Carlos Mazure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0609466A priority Critical patent/FR2907966B1/fr
Priority to US11/877,456 priority patent/US7833877B2/en
Publication of FR2907966A1 publication Critical patent/FR2907966A1/fr
Application granted granted Critical
Publication of FR2907966B1 publication Critical patent/FR2907966B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
FR0609466A 2006-10-27 2006-10-27 Procede de fabrication d'un substrat. Active FR2907966B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0609466A FR2907966B1 (fr) 2006-10-27 2006-10-27 Procede de fabrication d'un substrat.
US11/877,456 US7833877B2 (en) 2006-10-27 2007-10-23 Method for producing a semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0609466A FR2907966B1 (fr) 2006-10-27 2006-10-27 Procede de fabrication d'un substrat.

Publications (2)

Publication Number Publication Date
FR2907966A1 FR2907966A1 (fr) 2008-05-02
FR2907966B1 true FR2907966B1 (fr) 2009-01-30

Family

ID=37964521

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0609466A Active FR2907966B1 (fr) 2006-10-27 2006-10-27 Procede de fabrication d'un substrat.

Country Status (2)

Country Link
US (1) US7833877B2 (fr)
FR (1) FR2907966B1 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7883956B2 (en) * 2008-02-15 2011-02-08 International Business Machines Corporation Method of forming coplanar active and isolation regions and structures thereof
FR2938120B1 (fr) * 2008-10-31 2011-04-08 Commissariat Energie Atomique Procede de formation d'une couche monocristalline dans le domaine micro-electronique
EP2246882B1 (fr) 2009-04-29 2015-03-04 Soitec Procédé de transfert d'une couche à partir d'un substrat donneur sur un substrat de manipulation
FR2968121B1 (fr) 2010-11-30 2012-12-21 Soitec Silicon On Insulator Procede de transfert d'une couche a haute temperature
EP2500933A1 (fr) * 2011-03-11 2012-09-19 S.O.I. TEC Silicon Structure multicouche et procédé de fabrication de dispositifs semi-conducteurs
US9136134B2 (en) 2012-02-22 2015-09-15 Soitec Methods of providing thin layers of crystalline semiconductor material, and related structures and devices
US9837334B2 (en) * 2015-03-30 2017-12-05 Globalfoundries Singapore Pte. Ltd. Programmable active cooling device
DE102015210384A1 (de) * 2015-06-05 2016-12-08 Soitec Verfahren zur mechanischen Trennung für eine Doppelschichtübertragung
FR3076069B1 (fr) * 2017-12-22 2021-11-26 Commissariat Energie Atomique Procede de transfert d'une couche utile
FR3076070B1 (fr) * 2017-12-22 2019-12-27 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de transfert d'une couche utile
FR3078822B1 (fr) * 2018-03-12 2020-02-28 Soitec Procede de preparation d’une couche mince de materiau ferroelectrique a base d’alcalin

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6251754B1 (en) * 1997-05-09 2001-06-26 Denso Corporation Semiconductor substrate manufacturing method
US6162705A (en) * 1997-05-12 2000-12-19 Silicon Genesis Corporation Controlled cleavage process and resulting device using beta annealing
US6103599A (en) * 1997-07-25 2000-08-15 Silicon Genesis Corporation Planarizing technique for multilayered substrates
FR2827423B1 (fr) * 2001-07-16 2005-05-20 Soitec Silicon On Insulator Procede d'amelioration d'etat de surface
US6703293B2 (en) * 2002-07-11 2004-03-09 Sharp Laboratories Of America, Inc. Implantation at elevated temperatures for amorphization re-crystallization of Si1-xGex films on silicon substrates
FR2844634B1 (fr) * 2002-09-18 2005-05-27 Soitec Silicon On Insulator Formation d'une couche utile relaxee a partir d'une plaquette sans couche tampon
FR2847076B1 (fr) * 2002-11-07 2005-02-18 Soitec Silicon On Insulator Procede de detachement d'une couche mince a temperature moderee apres co-implantation
WO2006037783A1 (fr) * 2004-10-04 2006-04-13 S.O.I.Tec Silicon On Insulator Technologies Procédé de transfert d'une couche mince comprenant une perturbation controlée d'une structure cristalline
US7285473B2 (en) * 2005-01-07 2007-10-23 International Business Machines Corporation Method for fabricating low-defect-density changed orientation Si
US7569857B2 (en) * 2006-09-29 2009-08-04 Intel Corporation Dual crystal orientation circuit devices on the same substrate

Also Published As

Publication number Publication date
US20080102601A1 (en) 2008-05-01
FR2907966A1 (fr) 2008-05-02
US7833877B2 (en) 2010-11-16

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