FR2999801B1 - Procede de fabrication d'une structure - Google Patents
Procede de fabrication d'une structureInfo
- Publication number
- FR2999801B1 FR2999801B1 FR1203428A FR1203428A FR2999801B1 FR 2999801 B1 FR2999801 B1 FR 2999801B1 FR 1203428 A FR1203428 A FR 1203428A FR 1203428 A FR1203428 A FR 1203428A FR 2999801 B1 FR2999801 B1 FR 2999801B1
- Authority
- FR
- France
- Prior art keywords
- support substrate
- interlayer
- forming
- substrate
- donor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 3
- 238000000034 method Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 abstract 8
- 239000011229 interlayer Substances 0.000 abstract 3
- 239000010410 layer Substances 0.000 abstract 3
- 238000000137 annealing Methods 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 2
- 230000002787 reinforcement Effects 0.000 abstract 2
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
Abstract
Ce procédé de fabrication d'une structure (3) comportant successivement un substrat support (2), une couche diélectrique (10), une couche active (11), une couche intercalaire (20) en silicium polycristallin, comporte les étapes : a) fournir un substrat donneur, b) former une zone de fragilisation dans le substrat donneur, c) fournir le substrat support (2), d) former la couche intercalaire (20) sur le substrat support (2), e) former la couche diélectrique (10), f) assembler le substrat donneur (1) et le substrat support (2), g) fracturer le substrat donneur (1) suivant la zone de fragilisation, h) soumettre la structure (3) à un recuit de renforcement d'au moins 10 minutes, le procédé de fabrication étant remarquable en ce que l'étape d) est exécutée de sorte que le silicium polycristallin de la couche intercalaire (20) présente une orientation de grains entièrement aléatoire, et en ce que le recuit de renforcement est exécuté à une température strictement supérieure à 950°C et inférieure à 1200°C.
Priority Applications (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1203428A FR2999801B1 (fr) | 2012-12-14 | 2012-12-14 | Procede de fabrication d'une structure |
JP2015547155A JP6354057B2 (ja) | 2012-12-14 | 2013-12-02 | 構造を作製するための方法 |
CN201380064142.8A CN104871306B (zh) | 2012-12-14 | 2013-12-02 | 用于制造结构的方法 |
PCT/IB2013/002692 WO2014091285A1 (fr) | 2012-12-14 | 2013-12-02 | Procédé de fabrication d'une structure |
RU2015118945A RU2607336C1 (ru) | 2012-12-14 | 2013-12-02 | Способ изготовления структуры |
US14/646,642 US9653536B2 (en) | 2012-12-14 | 2013-12-02 | Method for fabricating a structure |
KR1020157015337A KR102135644B1 (ko) | 2012-12-14 | 2013-12-02 | 구조를 제조하기 위한 방법 |
EP13805521.5A EP2932528B1 (fr) | 2012-12-14 | 2013-12-02 | Procédé de fabrication d'une structure |
TW102146277A TWI623037B (zh) | 2012-12-14 | 2013-12-13 | 製造結構的方法及用於高頻應用之結構 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1203428A FR2999801B1 (fr) | 2012-12-14 | 2012-12-14 | Procede de fabrication d'une structure |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2999801A1 FR2999801A1 (fr) | 2014-06-20 |
FR2999801B1 true FR2999801B1 (fr) | 2014-12-26 |
Family
ID=48050807
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1203428A Active FR2999801B1 (fr) | 2012-12-14 | 2012-12-14 | Procede de fabrication d'une structure |
Country Status (9)
Country | Link |
---|---|
US (1) | US9653536B2 (fr) |
EP (1) | EP2932528B1 (fr) |
JP (1) | JP6354057B2 (fr) |
KR (1) | KR102135644B1 (fr) |
CN (1) | CN104871306B (fr) |
FR (1) | FR2999801B1 (fr) |
RU (1) | RU2607336C1 (fr) |
TW (1) | TWI623037B (fr) |
WO (1) | WO2014091285A1 (fr) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016081313A1 (fr) * | 2014-11-18 | 2016-05-26 | Sunedison Semiconductor Limited | Procédé de fabrication de plaquettes de semi-conducteur sur isolant à haute résistivité comprenant couches de piégeage de charges |
EP4120320A1 (fr) * | 2015-03-03 | 2023-01-18 | GlobalWafers Co., Ltd. | Films de silicium polycristallin de piégeage de charge sur des substrats de silicium avec une contrainte de film commandable |
FR3048306B1 (fr) * | 2016-02-26 | 2018-03-16 | Soitec | Support pour une structure semi-conductrice |
FR3049763B1 (fr) * | 2016-03-31 | 2018-03-16 | Soitec | Substrat semi-conducteur sur isolant pour applications rf |
FR3074960B1 (fr) * | 2017-12-07 | 2019-12-06 | Soitec | Procede de transfert d'une couche utilisant une structure demontable |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5080933A (en) * | 1990-09-04 | 1992-01-14 | Motorola, Inc. | Selective deposition of polycrystalline silicon |
JP2691244B2 (ja) * | 1990-11-28 | 1997-12-17 | 株式会社日立製作所 | 誘電体分離基板 |
FR2773261B1 (fr) * | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
JP3484961B2 (ja) * | 1997-12-26 | 2004-01-06 | 三菱住友シリコン株式会社 | Soi基板の製造方法 |
US6368938B1 (en) * | 1999-10-05 | 2002-04-09 | Silicon Wafer Technologies, Inc. | Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate |
US20090325362A1 (en) | 2003-01-07 | 2009-12-31 | Nabil Chhaimi | Method of recycling an epitaxied donor wafer |
FR2892228B1 (fr) | 2005-10-18 | 2008-01-25 | Soitec Silicon On Insulator | Procede de recyclage d'une plaquette donneuse epitaxiee |
US7005160B2 (en) * | 2003-04-24 | 2006-02-28 | Asm America, Inc. | Methods for depositing polycrystalline films with engineered grain structures |
JP2007507093A (ja) * | 2003-09-26 | 2007-03-22 | ユニべルシテ・カトリック・ドゥ・ルベン | 抵抗損を低減させた積層型半導体構造の製造方法 |
WO2005120775A1 (fr) | 2004-06-08 | 2005-12-22 | S.O.I. Tec Silicon On Insulator Technologies | Planarisation d'une couche heteroepitaxiale |
US20080213981A1 (en) | 2005-01-31 | 2008-09-04 | Freescale Semiconductor, Inc. | Method of Fabricating a Silicon-On-Insulator Structure |
JP4934966B2 (ja) * | 2005-02-04 | 2012-05-23 | 株式会社Sumco | Soi基板の製造方法 |
BRPI0706659A2 (pt) * | 2006-01-20 | 2011-04-05 | Bp Corp North America Inc | métodos de fabricação de silìcio moldado e de célula solar, células solares, corpos e wafers de silìcio multicristalinos ordenados geometricamente continuos |
EP1835533B1 (fr) | 2006-03-14 | 2020-06-03 | Soitec | Méthode de fabrication de plaquettes composites et procédé de recyclage d'un substrat donneur usagé |
ATE383656T1 (de) | 2006-03-31 | 2008-01-15 | Soitec Silicon On Insulator | Verfahren zur herstellung eines verbundmaterials und verfahren zur auswahl eines wafers |
FR2899380B1 (fr) | 2006-03-31 | 2008-08-29 | Soitec Sa | Procede de revelation de defauts cristallins dans un substrat massif. |
EP2264755A3 (fr) | 2007-01-24 | 2011-11-23 | S.O.I.TEC Silicon on Insulator Technologies S.A. | Procédé de fabrication de plaquettes silicium sur isolant et plaquette correspondante |
EP2015354A1 (fr) * | 2007-07-11 | 2009-01-14 | S.O.I.Tec Silicon on Insulator Technologies | Procédé pour le recyclage d'un substrat, procédé de fabrication de tranches stratifiées et substrat donneur recyclé approprié |
US20090065816A1 (en) * | 2007-09-11 | 2009-03-12 | Applied Materials, Inc. | Modulating the stress of poly-crystaline silicon films and surrounding layers through the use of dopants and multi-layer silicon films with controlled crystal structure |
FR2943458B1 (fr) | 2009-03-18 | 2011-06-10 | Soitec Silicon On Insulator | Procede de finition d'un substrat de type "silicium sur isolant" soi |
FR2944645B1 (fr) | 2009-04-21 | 2011-09-16 | Soitec Silicon On Insulator | Procede d'amincissement d'un substrat silicium sur isolant |
FR2952224B1 (fr) | 2009-10-30 | 2012-04-20 | Soitec Silicon On Insulator | Procede de controle de la repartition des contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante. |
FR2953640B1 (fr) * | 2009-12-04 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante |
FR2953988B1 (fr) | 2009-12-11 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | Procede de detourage d'un substrat chanfreine. |
FR2957716B1 (fr) | 2010-03-18 | 2012-10-05 | Soitec Silicon On Insulator | Procede de finition d'un substrat de type semi-conducteur sur isolant |
US20120217622A1 (en) * | 2010-05-21 | 2012-08-30 | International Business Machines Corporation | Method for Imparting a Controlled Amount of Stress in Semiconductor Devices for Fabricating Thin Flexible Circuits |
FR2973158B1 (fr) * | 2011-03-22 | 2014-02-28 | Soitec Silicon On Insulator | Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences |
FR2977974B1 (fr) | 2011-07-13 | 2014-03-07 | Soitec Silicon On Insulator | Procede de mesure de defauts dans un substrat de silicium |
FR2987682B1 (fr) | 2012-03-05 | 2014-11-21 | Soitec Silicon On Insulator | Procede de test d'une structure semi-conducteur sur isolant et application dudit test pour la fabrication d'une telle structure |
-
2012
- 2012-12-14 FR FR1203428A patent/FR2999801B1/fr active Active
-
2013
- 2013-12-02 RU RU2015118945A patent/RU2607336C1/ru active
- 2013-12-02 JP JP2015547155A patent/JP6354057B2/ja active Active
- 2013-12-02 EP EP13805521.5A patent/EP2932528B1/fr active Active
- 2013-12-02 WO PCT/IB2013/002692 patent/WO2014091285A1/fr active Application Filing
- 2013-12-02 US US14/646,642 patent/US9653536B2/en active Active
- 2013-12-02 KR KR1020157015337A patent/KR102135644B1/ko active IP Right Grant
- 2013-12-02 CN CN201380064142.8A patent/CN104871306B/zh active Active
- 2013-12-13 TW TW102146277A patent/TWI623037B/zh active
Also Published As
Publication number | Publication date |
---|---|
EP2932528A1 (fr) | 2015-10-21 |
KR102135644B1 (ko) | 2020-07-20 |
EP2932528B1 (fr) | 2021-03-24 |
TWI623037B (zh) | 2018-05-01 |
JP6354057B2 (ja) | 2018-07-11 |
WO2014091285A1 (fr) | 2014-06-19 |
FR2999801A1 (fr) | 2014-06-20 |
CN104871306A (zh) | 2015-08-26 |
TW201436038A (zh) | 2014-09-16 |
CN104871306B (zh) | 2018-07-24 |
JP2016506619A (ja) | 2016-03-03 |
KR20150093696A (ko) | 2015-08-18 |
US20150303247A1 (en) | 2015-10-22 |
RU2607336C1 (ru) | 2017-01-10 |
US9653536B2 (en) | 2017-05-16 |
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