FR2952224B1 - Procede de controle de la repartition des contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante. - Google Patents

Procede de controle de la repartition des contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante.

Info

Publication number
FR2952224B1
FR2952224B1 FR0957662A FR0957662A FR2952224B1 FR 2952224 B1 FR2952224 B1 FR 2952224B1 FR 0957662 A FR0957662 A FR 0957662A FR 0957662 A FR0957662 A FR 0957662A FR 2952224 B1 FR2952224 B1 FR 2952224B1
Authority
FR
France
Prior art keywords
constraints
insulation
distribution
controlling
semiconductor type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0957662A
Other languages
English (en)
Other versions
FR2952224A1 (fr
Inventor
Sebastien Kerdiles
Patrick Reynaud
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0957662A priority Critical patent/FR2952224B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to PCT/EP2010/064604 priority patent/WO2011051078A1/fr
Priority to KR1020127011161A priority patent/KR101352483B1/ko
Priority to CN2010800484866A priority patent/CN102598243A/zh
Priority to JP2012535721A priority patent/JP2013509697A/ja
Priority to EP10762645.9A priority patent/EP2494593B1/fr
Priority to TW099133963A priority patent/TW201123282A/zh
Publication of FR2952224A1 publication Critical patent/FR2952224A1/fr
Application granted granted Critical
Publication of FR2952224B1 publication Critical patent/FR2952224B1/fr
Priority to US13/458,817 priority patent/US20120223419A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
FR0957662A 2009-10-30 2009-10-30 Procede de controle de la repartition des contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante. Active FR2952224B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR0957662A FR2952224B1 (fr) 2009-10-30 2009-10-30 Procede de controle de la repartition des contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante.
KR1020127011161A KR101352483B1 (ko) 2009-10-30 2010-09-30 절연체-상-반도체 유형의 구조 내 응력 분포의 조절을 위한 방법 및 상응하는 구조
CN2010800484866A CN102598243A (zh) 2009-10-30 2010-09-30 控制绝缘体上半导体型结构中应力分布的方法及对应结构
JP2012535721A JP2013509697A (ja) 2009-10-30 2010-09-30 半導体・オン・絶縁体型構造における応力の分布を制御するための方法およびこの方法に関連した構造
PCT/EP2010/064604 WO2011051078A1 (fr) 2009-10-30 2010-09-30 Procédé de maîtrise de la distribution de contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante
EP10762645.9A EP2494593B1 (fr) 2009-10-30 2010-09-30 Procédé de maîtrise de la distribution de contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante
TW099133963A TW201123282A (en) 2009-10-30 2010-10-06 Method for controlling the distribution of stresses in a semiconductor-on-insulator type structure and corresponding structure
US13/458,817 US20120223419A1 (en) 2009-10-30 2012-04-27 Method for controlling the distribution of stresses in a semiconductor-on-insulator type structure and corresponding structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0957662A FR2952224B1 (fr) 2009-10-30 2009-10-30 Procede de controle de la repartition des contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante.

Publications (2)

Publication Number Publication Date
FR2952224A1 FR2952224A1 (fr) 2011-05-06
FR2952224B1 true FR2952224B1 (fr) 2012-04-20

Family

ID=41571700

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0957662A Active FR2952224B1 (fr) 2009-10-30 2009-10-30 Procede de controle de la repartition des contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante.

Country Status (8)

Country Link
US (1) US20120223419A1 (fr)
EP (1) EP2494593B1 (fr)
JP (1) JP2013509697A (fr)
KR (1) KR101352483B1 (fr)
CN (1) CN102598243A (fr)
FR (1) FR2952224B1 (fr)
TW (1) TW201123282A (fr)
WO (1) WO2011051078A1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103523738B (zh) * 2012-07-06 2016-07-06 无锡华润上华半导体有限公司 微机电系统薄片及其制备方法
FR2999801B1 (fr) 2012-12-14 2014-12-26 Soitec Silicon On Insulator Procede de fabrication d'une structure
CN105712286B (zh) * 2014-12-02 2018-03-30 中芯国际集成电路制造(上海)有限公司 Mems器件的制作方法
FR3064398B1 (fr) * 2017-03-21 2019-06-07 Soitec Structure de type semi-conducteur sur isolant, notamment pour un capteur d'image de type face avant, et procede de fabrication d'une telle structure
CN110544668B (zh) * 2018-05-28 2022-03-25 沈阳硅基科技有限公司 一种通过贴膜改变soi边缘stir的方法
FR3091620B1 (fr) * 2019-01-07 2021-01-29 Commissariat Energie Atomique Procédé de transfert de couche avec réduction localisée d’une capacité à initier une fracture
KR102055543B1 (ko) 2019-04-30 2019-12-13 동빈 박 개폐 시스템을 포함하는 공기터널이 형성된 라이더 슈트
KR20220111965A (ko) 2021-02-03 2022-08-10 최동민 오토바이 레이싱 에어백 전신 슈트
FR3132383A1 (fr) * 2022-01-31 2023-08-04 Soitec Procédé de fabrication d’une structure de type double semi-conducteur sur isolant

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US3516803A (en) * 1966-10-06 1970-06-23 Texas Instruments Inc Method for the purification of trichlorosilane
US6057212A (en) * 1998-05-04 2000-05-02 International Business Machines Corporation Method for making bonded metal back-plane substrates
JPH11345954A (ja) * 1998-05-29 1999-12-14 Shin Etsu Handotai Co Ltd 半導体基板及びその製造方法
US6331473B1 (en) * 1998-12-29 2001-12-18 Seiko Epson Corporation SOI substrate, method for making the same, semiconductive device and liquid crystal panel using the same
US6365465B1 (en) * 1999-03-19 2002-04-02 International Business Machines Corporation Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques
JP2000349266A (ja) * 1999-03-26 2000-12-15 Canon Inc 半導体部材の製造方法、半導体基体の利用方法、半導体部材の製造システム、半導体部材の生産管理方法及び堆積膜形成装置の利用方法
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
JP2004071939A (ja) * 2002-08-08 2004-03-04 Toshiba Corp 半導体装置及びその製造方法
JP2004193515A (ja) * 2002-12-13 2004-07-08 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法
KR100779341B1 (ko) * 2003-10-21 2007-11-23 가부시키가이샤 섬코 고저항 실리콘 웨이퍼의 제조 방법, 에피택셜 웨이퍼 및ｓｏｉ 웨이퍼의 제조 방법
DE102004048626B3 (de) * 2004-10-06 2006-04-13 X-Fab Semiconductor Foundries Ag Oxidationsverfahren von Siliziumscheiben zur Reduzierung von mechanischen Spannungen
US7402520B2 (en) * 2004-11-26 2008-07-22 Applied Materials, Inc. Edge removal of silicon-on-insulator transfer wafer
CN101124657B (zh) * 2005-02-28 2010-04-14 信越半导体股份有限公司 贴合晶圆的制造方法及贴合晶圆
JP4398934B2 (ja) * 2005-02-28 2010-01-13 信越半導体株式会社 Ｓｏｉウエーハの製造方法
KR20100065145A (ko) 2007-09-14 2010-06-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 전자 기기
FR2928775B1 (fr) * 2008-03-11 2011-12-09 Soitec Silicon On Insulator Procede de fabrication d'un substrat de type semiconducteur sur isolant

Also Published As

Publication number Publication date
KR20120069753A (ko) 2012-06-28
WO2011051078A1 (fr) 2011-05-05
CN102598243A (zh) 2012-07-18
US20120223419A1 (en) 2012-09-06
EP2494593A1 (fr) 2012-09-05
KR101352483B1 (ko) 2014-01-17
EP2494593B1 (fr) 2013-11-06
TW201123282A (en) 2011-07-01
JP2013509697A (ja) 2013-03-14
FR2952224A1 (fr) 2011-05-06

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