IT1391239B1 - Metodo per la formazione di bump in substrati con through via - Google Patents

Metodo per la formazione di bump in substrati con through via

Info

Publication number
IT1391239B1
IT1391239B1 ITMI2008A001505A ITMI20081505A IT1391239B1 IT 1391239 B1 IT1391239 B1 IT 1391239B1 IT MI2008A001505 A ITMI2008A001505 A IT MI2008A001505A IT MI20081505 A ITMI20081505 A IT MI20081505A IT 1391239 B1 IT1391239 B1 IT 1391239B1
Authority
IT
Italy
Prior art keywords
substrates
bump formation
bump
formation
Prior art date
Application number
ITMI2008A001505A
Other languages
English (en)
Inventor
Pier Paolo Stoppino
Gian Pietro Vanalli
Giovanni Campardo
Aldo Losavio
Paolo Pulici
Original Assignee
Milano Politecnico
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Milano Politecnico, St Microelectronics Srl filed Critical Milano Politecnico
Priority to ITMI2008A001505A priority Critical patent/IT1391239B1/it
Priority to US12/537,075 priority patent/US8759215B2/en
Publication of ITMI20081505A1 publication Critical patent/ITMI20081505A1/it
Application granted granted Critical
Publication of IT1391239B1 publication Critical patent/IT1391239B1/it
Priority to US14/291,749 priority patent/US8928123B2/en

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    • H—ELECTRICITY
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
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    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
ITMI2008A001505A 2008-08-08 2008-08-08 Metodo per la formazione di bump in substrati con through via IT1391239B1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
ITMI2008A001505A IT1391239B1 (it) 2008-08-08 2008-08-08 Metodo per la formazione di bump in substrati con through via
US12/537,075 US8759215B2 (en) 2008-08-08 2009-08-06 Method for forming bumps in substrates with through vias
US14/291,749 US8928123B2 (en) 2008-08-08 2014-05-30 Through via structure including a conductive portion and aligned solder portion

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Application Number Priority Date Filing Date Title
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DE102011005978A1 (de) * 2011-03-23 2012-09-27 Siemens Aktiengesellschaft Integrierte Schaltung mit einer elektrischen Durchkontaktierung sowie Verfahren zur Herstellung einer elektrischen Durchkontaktierung
US9312175B2 (en) * 2012-12-20 2016-04-12 Invensas Corporation Surface modified TSV structure and methods thereof
US9589946B2 (en) * 2015-04-28 2017-03-07 Kabushiki Kaisha Toshiba Chip with a bump connected to a plurality of wirings
JP6810346B2 (ja) * 2016-12-07 2021-01-06 富士通株式会社 発光素子接合基板
US11908784B2 (en) * 2020-09-23 2024-02-20 Nxp Usa, Inc. Packaged semiconductor device assembly

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US5618752A (en) * 1995-06-05 1997-04-08 Harris Corporation Method of fabrication of surface mountable integrated circuits
US6882030B2 (en) * 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
JP3027951B2 (ja) * 1997-03-12 2000-04-04 日本電気株式会社 半導体装置の製造方法
US6498381B2 (en) * 2001-02-22 2002-12-24 Tru-Si Technologies, Inc. Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
TW594972B (en) * 2002-03-19 2004-06-21 Seiko Epson Corp Semiconductor device and its manufacturing method, circuit board and electronic machine
JP2004095849A (ja) * 2002-08-30 2004-03-25 Fujikura Ltd 貫通電極付き半導体基板の製造方法、貫通電極付き半導体デバイスの製造方法
JP4072677B2 (ja) * 2003-01-15 2008-04-09 セイコーエプソン株式会社 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器
JP3990347B2 (ja) * 2003-12-04 2007-10-10 ローム株式会社 半導体チップおよびその製造方法、ならびに半導体装置
US7767493B2 (en) * 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US7425507B2 (en) * 2005-06-28 2008-09-16 Micron Technology, Inc. Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures
US7517798B2 (en) * 2005-09-01 2009-04-14 Micron Technology, Inc. Methods for forming through-wafer interconnects and structures resulting therefrom
KR100809696B1 (ko) * 2006-08-08 2008-03-06 삼성전자주식회사 사이즈가 상이한 복수의 반도체 칩이 적층된 멀티 칩패키지 및 그 제조방법
JP2008071831A (ja) * 2006-09-12 2008-03-27 Teoss Corp 貫通電極を備えるｉｃチップ、および該ｉｃチップの製造方法
US8049310B2 (en) * 2008-04-01 2011-11-01 Qimonda Ag Semiconductor device with an interconnect element and method for manufacture

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US8928123B2 (en) 2015-01-06
US20140264852A1 (en) 2014-09-18
US8759215B2 (en) 2014-06-24
ITMI20081505A1 (it) 2010-02-09
US20100032834A1 (en) 2010-02-11

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