FR2953640B1 - Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante - Google Patents

Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante

Info

Publication number
FR2953640B1
FR2953640B1 FR0958658A FR0958658A FR2953640B1 FR 2953640 B1 FR2953640 B1 FR 2953640B1 FR 0958658 A FR0958658 A FR 0958658A FR 0958658 A FR0958658 A FR 0958658A FR 2953640 B1 FR2953640 B1 FR 2953640B1
Authority
FR
France
Prior art keywords
support substrate
layer
substrate
donor substrate
semiconductor material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0958658A
Other languages
English (en)
Other versions
FR2953640A1 (fr
Inventor
Patrick Reynaud
Sebastien Kerdiles
Daniel Delprat
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0958658A priority Critical patent/FR2953640B1/fr
Priority to TW099141842A priority patent/TWI544550B/zh
Priority to JP2012541525A priority patent/JP2013513234A/ja
Priority to CN201080054092.1A priority patent/CN102640278B/zh
Priority to SG2012039137A priority patent/SG181093A1/en
Priority to KR1020127017419A priority patent/KR101379409B1/ko
Priority to PCT/EP2010/068883 priority patent/WO2011067394A1/fr
Priority to EP10785433A priority patent/EP2507827A1/fr
Publication of FR2953640A1 publication Critical patent/FR2953640A1/fr
Application granted granted Critical
Publication of FR2953640B1 publication Critical patent/FR2953640B1/fr
Priority to US13/487,066 priority patent/US8658514B2/en
Priority to US14/049,263 priority patent/US8962450B2/en
Priority to US14/612,772 priority patent/US9293473B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

La présente invention est relative à un procédé de fabrication d'une structure de type SOI, à pertes électriques diminuées, qui comprend successivement un substrat support en silicium (2), une couche d'oxyde (10) et une couche mince d'un matériau semi-conducteur (11), une couche de silicium polycristallin étant intercalée entre le substrat support et la couche d'oxyde, qui comprend les étapes suivantes : a) oxydation d'un substrat donneur (1) en matériau semi-conducteur pour y former en surface une couche d'oxyde (10) ; b) implantation d'ions dans le substrat donneur pour y former une zone de fragilisation ; c) collage du substrat donneur (1) sur le substrat support (2), le dit substrat support (2) ayant subi un traitement thermique apte à lui conférer une haute résistivité, sa face supérieure qui reçoit le substrat donneur (1) étant revêtue de ladite couche de silicium polycristallin (20) ; d) fracture du substrat donneur (1) selon la zone de fragilisation pour transférer sur le substrat support (2) une couche mince (11 ) de matériau semi conducteur ; e) mise en œuvre d'au moins une stabilisation thermique de ladite structure (3) ainsi réalisée, caractérisé par le fait que ledit traitement apte à conférer une haute résistivité audit substrat support (2) est mis en œuvre avant la formation de la couche de silicium polycristallin (20), et que l'étape e) comporte au moins une étape thermique longue, mise en œuvre à une température qui n'excède pas 950°C, pendant au moins 10 minutes.
FR0958658A 2009-12-04 2009-12-04 Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante Active FR2953640B1 (fr)

Priority Applications (11)

Application Number Priority Date Filing Date Title
FR0958658A FR2953640B1 (fr) 2009-12-04 2009-12-04 Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
TW099141842A TWI544550B (zh) 2009-12-04 2010-12-02 具有減少的電損失的絕緣體上半導體型結構的製造方法及相應的結構
EP10785433A EP2507827A1 (fr) 2009-12-04 2010-12-03 Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
SG2012039137A SG181093A1 (en) 2009-12-04 2010-12-03 Method for manufacturing a semiconductor-on-insulator structure having low electrical losses, and corresponding structure
KR1020127017419A KR101379409B1 (ko) 2009-12-04 2010-12-03 전기 손실들이 감소된 반도체 온 절연체 타입 구조의 제조 공정 및 대응 구조
PCT/EP2010/068883 WO2011067394A1 (fr) 2009-12-04 2010-12-03 Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
JP2012541525A JP2013513234A (ja) 2009-12-04 2010-12-03 電気的損失が低減した半導体オンインシュレータタイプの構造の製造プロセス及び対応する構造
CN201080054092.1A CN102640278B (zh) 2009-12-04 2010-12-03 使电损耗减小的绝缘体上半导体型结构的制造方法及相应的结构
US13/487,066 US8658514B2 (en) 2009-12-04 2012-06-01 Method for manufacturing a semiconductor-on-insulator structure having low electrical losses, and corresponding structure
US14/049,263 US8962450B2 (en) 2009-12-04 2013-10-09 Method for manufacturing a semiconductor-on-insulator structure having low electrical losses
US14/612,772 US9293473B2 (en) 2009-12-04 2015-02-03 Method for manufacturing a semiconductor on insulator structure having low electrical losses

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0958658A FR2953640B1 (fr) 2009-12-04 2009-12-04 Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante

Publications (2)

Publication Number Publication Date
FR2953640A1 FR2953640A1 (fr) 2011-06-10
FR2953640B1 true FR2953640B1 (fr) 2012-02-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
FR0958658A Active FR2953640B1 (fr) 2009-12-04 2009-12-04 Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante

Country Status (9)

Country Link
US (3) US8658514B2 (fr)
EP (1) EP2507827A1 (fr)
JP (1) JP2013513234A (fr)
KR (1) KR101379409B1 (fr)
CN (1) CN102640278B (fr)
FR (1) FR2953640B1 (fr)
SG (1) SG181093A1 (fr)
TW (1) TWI544550B (fr)
WO (1) WO2011067394A1 (fr)

Cited By (2)

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US11373856B2 (en) 2017-01-26 2022-06-28 Soitec Support for a semiconductor structure
US11462676B2 (en) 2017-03-31 2022-10-04 Soitec Method for adjusting the stress state of a piezoelectric film and acoustic wave device employing such a film

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FR2953640B1 (fr) 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
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US8853054B2 (en) * 2012-03-06 2014-10-07 Sunedison Semiconductor Limited Method of manufacturing silicon-on-insulator wafers
FR2999801B1 (fr) * 2012-12-14 2014-12-26 Soitec Silicon On Insulator Procede de fabrication d'une structure
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JP6070487B2 (ja) * 2013-09-04 2017-02-01 信越半導体株式会社 Ｓｏｉウェーハの製造方法、ｓｏｉウェーハ、及び半導体デバイス
JP5942948B2 (ja) * 2013-09-17 2016-06-29 信越半導体株式会社 Ｓｏｉウェーハの製造方法及び貼り合わせｓｏｉウェーハ
FI130149B (en) * 2013-11-26 2023-03-15 Okmetic Oyj High Resistive Silicon Substrate with Reduced RF Loss for RF Integrated Passive Device
KR102189611B1 (ko) 2014-01-23 2020-12-14 글로벌웨이퍼스 씨오., 엘티디. 고 비저항 soi 웨이퍼 및 그 제조 방법
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JP6118757B2 (ja) 2014-04-24 2017-04-19 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
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FR3098642B1 (fr) 2019-07-12 2021-06-11 Soitec Silicon On Insulator procédé de fabrication d'une structure comprenant une couche mince reportée sur un support muni d’une couche de piégeage de charges
FR3121548B1 (fr) 2021-03-30 2024-02-16 Soitec Silicon On Insulator Procede de preparation d’un substrat avance, notamment pour des applications photoniques
FR3113184B1 (fr) 2020-07-28 2022-09-16 Soitec Silicon On Insulator Procede de preparation d’un substrat support, et procede de report d’une couche mince sur ce substrat support
JP2023535319A (ja) 2020-07-28 2023-08-17 ソイテック 電荷トラップ層が設けられたキャリア基板に薄層を転写するプロセス
FR3114910A1 (fr) * 2020-10-06 2022-04-08 Soitec Procédé de fabrication d’un substrat pour la croissance épitaxiale d’une couche d’un alliage III-N à base de gallium
CN112420915B (zh) * 2020-11-23 2022-12-23 济南晶正电子科技有限公司 复合衬底的制备方法、复合薄膜及电子元器件
FR3129029B1 (fr) 2021-11-09 2023-09-29 Soitec Silicon On Insulator Procede de preparation d’un substrat support muni d’une couche de piegeage de charges
FR3129028B1 (fr) 2021-11-09 2023-11-10 Soitec Silicon On Insulator Procede de preparation d’un substrat support muni d’une couche de piegeage de charges
FR3137493A1 (fr) 2022-06-29 2024-01-05 Soitec Procede de fabrication d’une structure comportant une couche barriere a la diffusion d’especes atomiques
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US11462676B2 (en) 2017-03-31 2022-10-04 Soitec Method for adjusting the stress state of a piezoelectric film and acoustic wave device employing such a film

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US8658514B2 (en) 2014-02-25
KR20120087188A (ko) 2012-08-06
KR101379409B1 (ko) 2014-04-04
SG181093A1 (en) 2012-07-30
WO2011067394A1 (fr) 2011-06-09
US20140038388A1 (en) 2014-02-06
TW201140697A (en) 2011-11-16
JP2013513234A (ja) 2013-04-18
CN102640278B (zh) 2014-07-30
FR2953640A1 (fr) 2011-06-10
US8962450B2 (en) 2015-02-24
US20150171110A1 (en) 2015-06-18
US20120319121A1 (en) 2012-12-20
TWI544550B (zh) 2016-08-01
EP2507827A1 (fr) 2012-10-10
US9293473B2 (en) 2016-03-22
CN102640278A (zh) 2012-08-15

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