FR2938118B1 - Procede de fabrication d'un empilement de couches minces semi-conductrices - Google Patents

Procede de fabrication d'un empilement de couches minces semi-conductrices

Info

Publication number
FR2938118B1
FR2938118B1 FR0857409A FR0857409A FR2938118B1 FR 2938118 B1 FR2938118 B1 FR 2938118B1 FR 0857409 A FR0857409 A FR 0857409A FR 0857409 A FR0857409 A FR 0857409A FR 2938118 B1 FR2938118 B1 FR 2938118B1
Authority
FR
France
Prior art keywords
stack
manufacturing
semiconductor layers
thin semiconductor
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0857409A
Other languages
English (en)
Other versions
FR2938118A1 (fr
Inventor
Didier Landru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0857409A priority Critical patent/FR2938118B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to US13/121,671 priority patent/US8513092B2/en
Priority to CN2009801414425A priority patent/CN102187451A/zh
Priority to TW098136763A priority patent/TWI463564B/zh
Priority to JP2011533726A priority patent/JP5681975B2/ja
Priority to PCT/EP2009/064307 priority patent/WO2010049496A1/fr
Priority to EP09740907.2A priority patent/EP2345067B1/fr
Publication of FR2938118A1 publication Critical patent/FR2938118A1/fr
Application granted granted Critical
Publication of FR2938118B1 publication Critical patent/FR2938118B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)
FR0857409A 2008-10-30 2008-10-30 Procede de fabrication d'un empilement de couches minces semi-conductrices Active FR2938118B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0857409A FR2938118B1 (fr) 2008-10-30 2008-10-30 Procede de fabrication d'un empilement de couches minces semi-conductrices
CN2009801414425A CN102187451A (zh) 2008-10-30 2009-10-29 制造半导体薄膜的堆叠的方法
TW098136763A TWI463564B (zh) 2008-10-30 2009-10-29 製造半導體薄膜之堆疊的方法
JP2011533726A JP5681975B2 (ja) 2008-10-30 2009-10-29 半導体薄膜のスタックを製造する方法
US13/121,671 US8513092B2 (en) 2008-10-30 2009-10-29 Method for producing a stack of semi-conductor thin films
PCT/EP2009/064307 WO2010049496A1 (fr) 2008-10-30 2009-10-29 Procédé de production d'une pile de films minces à semi-conducteurs
EP09740907.2A EP2345067B1 (fr) 2008-10-30 2009-10-29 Procédé de production d'une pile de films minces à semi-conducteurs

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0857409A FR2938118B1 (fr) 2008-10-30 2008-10-30 Procede de fabrication d'un empilement de couches minces semi-conductrices

Publications (2)

Publication Number Publication Date
FR2938118A1 FR2938118A1 (fr) 2010-05-07
FR2938118B1 true FR2938118B1 (fr) 2011-04-22

Family

ID=40671234

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0857409A Active FR2938118B1 (fr) 2008-10-30 2008-10-30 Procede de fabrication d'un empilement de couches minces semi-conductrices

Country Status (7)

Country Link
US (1) US8513092B2 (fr)
EP (1) EP2345067B1 (fr)
JP (1) JP5681975B2 (fr)
CN (1) CN102187451A (fr)
FR (1) FR2938118B1 (fr)
TW (1) TWI463564B (fr)
WO (1) WO2010049496A1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2953640B1 (fr) 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
FR2980916B1 (fr) 2011-10-03 2014-03-28 Soitec Silicon On Insulator Procede de fabrication d'une structure de type silicium sur isolant
FR2989516B1 (fr) 2012-04-11 2014-04-18 Soitec Silicon On Insulator Procede de fabrication d'une structure soi mettant en oeuvre deux rta
FR2995447B1 (fr) 2012-09-07 2014-09-05 Soitec Silicon On Insulator Procede de separation d'au moins deux substrats selon une interface choisie
FR2995445B1 (fr) 2012-09-07 2016-01-08 Soitec Silicon On Insulator Procede de fabrication d'une structure en vue d'une separation ulterieure
WO2015119742A1 (fr) * 2014-02-07 2015-08-13 Sunedison Semiconductor Limited Procédés de préparation de structures à semi-conducteur en couches
FR3057705B1 (fr) * 2016-10-13 2019-04-12 Soitec Procede de dissolution d'un oxyde enterre dans une plaquette de silicium sur isolant
CN117835790B (zh) * 2024-03-06 2024-06-04 四川科尔威光电科技有限公司 半导体致冷器基板金属化方法及半导体致冷器金属化基板

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003046993A1 (fr) * 2001-11-29 2003-06-05 Shin-Etsu Handotai Co.,Ltd. Procede de production de plaquettes soi
JP4407127B2 (ja) 2003-01-10 2010-02-03 信越半導体株式会社 Ｓｏｉウエーハの製造方法
TW200428637A (en) * 2003-01-23 2004-12-16 Shinetsu Handotai Kk SOI wafer and production method thereof
JP2004259970A (ja) * 2003-02-26 2004-09-16 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
JP4854917B2 (ja) * 2003-03-18 2012-01-18 信越半導体株式会社 Ｓｏｉウェーハ及びその製造方法
JP4407384B2 (ja) * 2004-05-28 2010-02-03 株式会社Ｓｕｍｃｏ Ｓｏｉ基板の製造方法
US7560361B2 (en) * 2004-08-12 2009-07-14 International Business Machines Corporation Method of forming gate stack for semiconductor electronic device
JP2007173694A (ja) * 2005-12-26 2007-07-05 Canon Inc 半導体基板の作製方法
FR2896618B1 (fr) 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite
GB0612093D0 (en) * 2006-06-19 2006-07-26 Univ Belfast IC Substrate and Method of Manufacture of IC Substrate
FR2903809B1 (fr) * 2006-07-13 2008-10-17 Soitec Silicon On Insulator Traitement thermique de stabilisation d'interface e collage.
FR2905801B1 (fr) * 2006-09-12 2008-12-05 Soitec Silicon On Insulator Procede de transfert d'une couche a haute temperature
FR2911431B1 (fr) * 2007-01-16 2009-05-15 Soitec Silicon On Insulator Procede de fabrication de structures soi a couche isolante d'epaisseur controlee
FR2912259B1 (fr) * 2007-02-01 2009-06-05 Soitec Silicon On Insulator Procede de fabrication d'un substrat du type "silicium sur isolant".
KR101431780B1 (ko) 2007-03-19 2014-09-19 소이텍 패턴화된 얇은 ｓｏｉ

Also Published As

Publication number Publication date
WO2010049496A1 (fr) 2010-05-06
EP2345067A1 (fr) 2011-07-20
TW201030841A (en) 2010-08-16
US8513092B2 (en) 2013-08-20
JP2012507167A (ja) 2012-03-22
CN102187451A (zh) 2011-09-14
JP5681975B2 (ja) 2015-03-11
FR2938118A1 (fr) 2010-05-07
TWI463564B (zh) 2014-12-01
EP2345067B1 (fr) 2014-09-17
US20110177673A1 (en) 2011-07-21

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