FR2938119B1 - Procede de detachement de couches semi-conductrices a basse temperature - Google Patents

Procede de detachement de couches semi-conductrices a basse temperature

Info

Publication number
FR2938119B1
FR2938119B1 FR0857411A FR0857411A FR2938119B1 FR 2938119 B1 FR2938119 B1 FR 2938119B1 FR 0857411 A FR0857411 A FR 0857411A FR 0857411 A FR0857411 A FR 0857411A FR 2938119 B1 FR2938119 B1 FR 2938119B1
Authority
FR
France
Prior art keywords
low temperature
semiconductor layers
temperature semiconductor
detaching
detaching low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0857411A
Other languages
English (en)
Other versions
FR2938119A1 (fr
Inventor
Didier Landru
Ionut Radu
Sebastien Vincent
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0857411A priority Critical patent/FR2938119B1/fr
Priority to TW098136362A priority patent/TWI545614B/zh
Priority to JP2011533727A priority patent/JP2012507168A/ja
Priority to PCT/EP2009/064308 priority patent/WO2010049497A1/fr
Priority to KR1020117012006A priority patent/KR101304245B1/ko
Priority to SG10201404793VA priority patent/SG10201404793VA/en
Priority to US13/126,655 priority patent/US8623740B2/en
Priority to EP09744143.0A priority patent/EP2345068B1/fr
Priority to KR1020137012834A priority patent/KR20130061194A/ko
Priority to KR1020117031016A priority patent/KR101446977B1/ko
Priority to CN2009801431524A priority patent/CN102197473A/zh
Publication of FR2938119A1 publication Critical patent/FR2938119A1/fr
Application granted granted Critical
Publication of FR2938119B1 publication Critical patent/FR2938119B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
FR0857411A 2008-10-30 2008-10-30 Procede de detachement de couches semi-conductrices a basse temperature Active FR2938119B1 (fr)

Priority Applications (11)

Application Number Priority Date Filing Date Title
FR0857411A FR2938119B1 (fr) 2008-10-30 2008-10-30 Procede de detachement de couches semi-conductrices a basse temperature
TW098136362A TWI545614B (zh) 2008-10-30 2009-10-27 低溫下分離半導體層之方法
KR1020117031016A KR101446977B1 (ko) 2008-10-30 2009-10-29 저온에서 반도체층들을 분리하는 방법
KR1020117012006A KR101304245B1 (ko) 2008-10-30 2009-10-29 저온에서 반도체층들을 분리하는 방법
SG10201404793VA SG10201404793VA (en) 2008-10-30 2009-10-29 Method of detaching semi-conductor layers at low temperature
US13/126,655 US8623740B2 (en) 2008-10-30 2009-10-29 Method of detaching semi-conductor layers at low temperature
JP2011533727A JP2012507168A (ja) 2008-10-30 2009-10-29 半導体層を低温で取り外す方法
KR1020137012834A KR20130061194A (ko) 2008-10-30 2009-10-29 저온에서 반도체층들을 분리하는 방법
PCT/EP2009/064308 WO2010049497A1 (fr) 2008-10-30 2009-10-29 Procédé de détachement de couches semi-conductrices à basse température
CN2009801431524A CN102197473A (zh) 2008-10-30 2009-10-29 低温下剥离半导体层的方法
EP09744143.0A EP2345068B1 (fr) 2008-10-30 2009-10-29 Procédé de détachement de couches semi-conductrices à basse température

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0857411A FR2938119B1 (fr) 2008-10-30 2008-10-30 Procede de detachement de couches semi-conductrices a basse temperature

Publications (2)

Publication Number Publication Date
FR2938119A1 FR2938119A1 (fr) 2010-05-07
FR2938119B1 true FR2938119B1 (fr) 2011-04-22

Family

ID=40673943

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0857411A Active FR2938119B1 (fr) 2008-10-30 2008-10-30 Procede de detachement de couches semi-conductrices a basse temperature

Country Status (9)

Country Link
US (1) US8623740B2 (fr)
EP (1) EP2345068B1 (fr)
JP (1) JP2012507168A (fr)
KR (3) KR20130061194A (fr)
CN (1) CN102197473A (fr)
FR (1) FR2938119B1 (fr)
SG (1) SG10201404793VA (fr)
TW (1) TWI545614B (fr)
WO (1) WO2010049497A1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012182201A (ja) * 2011-02-28 2012-09-20 Shin Etsu Chem Co Ltd 半導体ウェーハの製造方法
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
FR2980916B1 (fr) * 2011-10-03 2014-03-28 Soitec Silicon On Insulator Procede de fabrication d'une structure de type silicium sur isolant
US8637381B2 (en) * 2011-10-17 2014-01-28 International Business Machines Corporation High-k dielectric and silicon nitride box region
FR2987166B1 (fr) 2012-02-16 2017-05-12 Soitec Silicon On Insulator Procede de transfert d'une couche
FR2995447B1 (fr) 2012-09-07 2014-09-05 Soitec Silicon On Insulator Procede de separation d'au moins deux substrats selon une interface choisie
FR2995445B1 (fr) 2012-09-07 2016-01-08 Soitec Silicon On Insulator Procede de fabrication d'une structure en vue d'une separation ulterieure
FR2995444B1 (fr) * 2012-09-10 2016-11-25 Soitec Silicon On Insulator Procede de detachement d'une couche
US10068795B2 (en) * 2014-02-07 2018-09-04 Globalwafers Co., Ltd. Methods for preparing layered semiconductor structures
FR3091620B1 (fr) * 2019-01-07 2021-01-29 Commissariat Energie Atomique Procédé de transfert de couche avec réduction localisée d’une capacité à initier une fracture
CN110491827B (zh) * 2019-08-13 2021-02-12 北京工业大学 一种半导体薄膜层的转移方法及复合晶圆的制备方法
JP2023137581A (ja) * 2022-03-18 2023-09-29 キオクシア株式会社 半導体装置、半導体装置の製造方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4771016A (en) * 1987-04-24 1988-09-13 Harris Corporation Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor
US6287941B1 (en) * 1999-04-21 2001-09-11 Silicon Genesis Corporation Surface finishing of SOI substrates using an EPI process
FR2797713B1 (fr) * 1999-08-20 2002-08-02 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
FR2845202B1 (fr) * 2002-10-01 2004-11-05 Soitec Silicon On Insulator Procede de recuit rapide de tranches de materiau semiconducteur.
JP4407127B2 (ja) * 2003-01-10 2010-02-03 信越半導体株式会社 Ｓｏｉウエーハの製造方法
JP2004259970A (ja) * 2003-02-26 2004-09-16 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
FR2855908B1 (fr) * 2003-06-06 2005-08-26 Soitec Silicon On Insulator Procede d'obtention d'une structure comprenant au moins un substrat et une couche ultramince
US7084460B2 (en) * 2003-11-03 2006-08-01 International Business Machines Corporation Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates
US7772087B2 (en) * 2003-12-19 2010-08-10 Commissariat A L'energie Atomique Method of catastrophic transfer of a thin film after co-implantation
US6992025B2 (en) * 2004-01-12 2006-01-31 Sharp Laboratories Of America, Inc. Strained silicon on insulator from film transfer and relaxation by hydrogen implantation
JP2007173354A (ja) * 2005-12-20 2007-07-05 Shin Etsu Chem Co Ltd Ｓｏｉ基板およびｓｏｉ基板の製造方法
WO2007071787A1 (fr) * 2005-12-22 2007-06-28 S.O.I.Tec Silicon On Insulator Technologies Procede de simplification d'une sequence de finition et structure obtenue par le procede
FR2896618B1 (fr) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite
FR2899594A1 (fr) * 2006-04-10 2007-10-12 Commissariat Energie Atomique Procede d'assemblage de substrats avec traitements thermiques a basses temperatures
JP5109287B2 (ja) * 2006-05-09 2012-12-26 株式会社Ｓｕｍｃｏ 半導体基板の製造方法
FR2903808B1 (fr) 2006-07-11 2008-11-28 Soitec Silicon On Insulator Procede de collage direct de deux substrats utilises en electronique, optique ou opto-electronique
FR2903809B1 (fr) * 2006-07-13 2008-10-17 Soitec Silicon On Insulator Traitement thermique de stabilisation d'interface e collage.
JP4820801B2 (ja) * 2006-12-26 2011-11-24 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの製造方法
JP5231460B2 (ja) * 2007-03-19 2013-07-10 ソワテク パターニングされた薄いｓｏｉ
US20100176495A1 (en) * 2009-01-12 2010-07-15 International Business Machines Corporation Low cost fabrication of double box back gate silicon-on-insulator wafers
US7767546B1 (en) * 2009-01-12 2010-08-03 International Business Machines Corporation Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer
US8673703B2 (en) * 2009-11-17 2014-03-18 International Business Machines Corporation Fabrication of graphene nanoelectronic devices on SOI structures

Also Published As

Publication number Publication date
CN102197473A (zh) 2011-09-21
EP2345068B1 (fr) 2015-09-02
FR2938119A1 (fr) 2010-05-07
TW201027591A (en) 2010-07-16
SG10201404793VA (en) 2014-10-30
KR101446977B1 (ko) 2014-10-07
TWI545614B (zh) 2016-08-11
EP2345068A1 (fr) 2011-07-20
KR20110075039A (ko) 2011-07-05
KR101304245B1 (ko) 2013-09-05
US20110207295A1 (en) 2011-08-25
JP2012507168A (ja) 2012-03-22
KR20130061194A (ko) 2013-06-10
WO2010049497A1 (fr) 2010-05-06
KR20120013454A (ko) 2012-02-14
US8623740B2 (en) 2014-01-07

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