FR3057705B1 - Procede de dissolution d'un oxyde enterre dans une plaquette de silicium sur isolant - Google Patents
Procede de dissolution d'un oxyde enterre dans une plaquette de silicium sur isolant Download PDFInfo
- Publication number
- FR3057705B1 FR3057705B1 FR1659917A FR1659917A FR3057705B1 FR 3057705 B1 FR3057705 B1 FR 3057705B1 FR 1659917 A FR1659917 A FR 1659917A FR 1659917 A FR1659917 A FR 1659917A FR 3057705 B1 FR3057705 B1 FR 3057705B1
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- FR
- France
- Prior art keywords
- silicon
- dissolving
- oxide
- bleed
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title abstract 4
- 229910052710 silicon Inorganic materials 0.000 title abstract 4
- 239000010703 silicon Substances 0.000 title abstract 4
- 238000000034 method Methods 0.000 title abstract 3
- 239000012212 insulator Substances 0.000 abstract 3
- 238000000137 annealing Methods 0.000 abstract 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract 1
- 229910052760 oxygen Inorganic materials 0.000 abstract 1
- 239000001301 oxygen Substances 0.000 abstract 1
- 230000002000 scavenging effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Formation Of Insulating Films (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
La présente invention porte sur un procédé de dissolution d'un oxyde enterré dans une plaquette de silicium sur isolant, comprenant la fourniture d'une plaquette de silicium sur isolant (100, 300, 400, 500) ayant une couche de silicium (101, 301, 401, 501) fixée à un substrat de support (103, 303, 403, 503) par l'intermédiaire d'une couche d'oxyde enterrée (102, 302, 402, 502), et le recuit de ladite plaquette de silicium sur isolant (100, 300, 400, 500) pour dissoudre au moins partiellement la couche d'oxyde enterrée (102, 302, 402, 502). Le procédé inventif comprend en outre une étape de prévoir une couche de piégeage d'oxygène (104, 304, 404, 504) sur ou au-dessus de la couche de silicium (101, 301, 401, 501) avant l'étape de recuit.
Priority Applications (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1659917A FR3057705B1 (fr) | 2016-10-13 | 2016-10-13 | Procede de dissolution d'un oxyde enterre dans une plaquette de silicium sur isolant |
TW106133228A TWI641040B (zh) | 2016-10-13 | 2017-09-27 | 用於溶解絕緣體上矽晶圓中埋置氧化物之方法 |
CN201780063006.5A CN109844911B (zh) | 2016-10-13 | 2017-09-29 | 用于在绝缘体上硅晶圆中溶解埋置氧化物的方法 |
KR1020197011145A KR102217707B1 (ko) | 2016-10-13 | 2017-09-29 | 실리콘-온-절연체 웨이퍼 내의 매립 산화물을 용해시키기 위한 방법 |
PCT/EP2017/074823 WO2018069067A1 (fr) | 2016-10-13 | 2017-09-29 | Procédé de dissolution d'un oxyde enfoui dans une tranche de silicium sur isolant |
JP2019518498A JP6801154B2 (ja) | 2016-10-13 | 2017-09-29 | シリコンオンインシュレータウェハの埋め込み酸化膜を溶解するための方法 |
US16/342,133 US10847370B2 (en) | 2016-10-13 | 2017-09-29 | Method for dissolving a buried oxide in a silicon-on-insulator wafer |
DE112017005180.0T DE112017005180T5 (de) | 2016-10-13 | 2017-09-29 | Verfahren zum Auflösen eines vergrabenen Oxids in einem Silicon-On-Insulator-Wafer |
SG11201903019XA SG11201903019XA (en) | 2016-10-13 | 2017-09-29 | Method for dissolving a buried oxide in a silicon-on-insulator wafer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1659917A FR3057705B1 (fr) | 2016-10-13 | 2016-10-13 | Procede de dissolution d'un oxyde enterre dans une plaquette de silicium sur isolant |
FR1659917 | 2016-10-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3057705A1 FR3057705A1 (fr) | 2018-04-20 |
FR3057705B1 true FR3057705B1 (fr) | 2019-04-12 |
Family
ID=57583305
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1659917A Active FR3057705B1 (fr) | 2016-10-13 | 2016-10-13 | Procede de dissolution d'un oxyde enterre dans une plaquette de silicium sur isolant |
Country Status (9)
Country | Link |
---|---|
US (1) | US10847370B2 (fr) |
JP (1) | JP6801154B2 (fr) |
KR (1) | KR102217707B1 (fr) |
CN (1) | CN109844911B (fr) |
DE (1) | DE112017005180T5 (fr) |
FR (1) | FR3057705B1 (fr) |
SG (1) | SG11201903019XA (fr) |
TW (1) | TWI641040B (fr) |
WO (1) | WO2018069067A1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11069560B2 (en) * | 2016-11-01 | 2021-07-20 | Shin-Etsu Chemical Co., Ltd. | Method of transferring device layer to transfer substrate and highly thermal conductive substrate |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003078116A (ja) * | 2001-08-31 | 2003-03-14 | Canon Inc | 半導体部材の製造方法及び半導体装置の製造方法 |
US6784072B2 (en) * | 2002-07-22 | 2004-08-31 | International Business Machines Corporation | Control of buried oxide in SIMOX |
US6664598B1 (en) * | 2002-09-05 | 2003-12-16 | International Business Machines Corporation | Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control |
US20050170570A1 (en) * | 2004-01-30 | 2005-08-04 | International Business Machines Corporation | High electrical quality buried oxide in simox |
US8138061B2 (en) * | 2005-01-07 | 2012-03-20 | International Business Machines Corporation | Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide |
US7867906B2 (en) * | 2005-06-22 | 2011-01-11 | Nec Corporation | Semiconductor device and method for manufacturing same |
JP2007180416A (ja) * | 2005-12-28 | 2007-07-12 | Siltronic Ag | Soiウェーハの製造方法 |
FR2936356B1 (fr) * | 2008-09-23 | 2010-10-22 | Soitec Silicon On Insulator | Procede de dissolution locale de la couche d'oxyde dans une structure de type semi-conducteur sur isolant |
FR2937794A1 (fr) * | 2008-10-28 | 2010-04-30 | Soitec Silicon On Insulator | Procede de traitement d'une structure de type semi-conducteur sur isolant par dissolution selective de sa couche d'oxyde |
FR2938118B1 (fr) * | 2008-10-30 | 2011-04-22 | Soitec Silicon On Insulator | Procede de fabrication d'un empilement de couches minces semi-conductrices |
FR2941324B1 (fr) * | 2009-01-22 | 2011-04-29 | Soitec Silicon On Insulator | Procede de dissolution de la couche d'oxyde dans la couronne d'une structure de type semi-conducteur sur isolant. |
US20100244206A1 (en) | 2009-03-31 | 2010-09-30 | International Business Machines Corporation | Method and structure for threshold voltage control and drive current improvement for high-k metal gate transistors |
EP2381470B1 (fr) * | 2010-04-22 | 2012-08-22 | Soitec | Dispositif semi-conducteur comprenant un transistor à effet de champ dans une structure silicium sur isolant |
US8796116B2 (en) * | 2011-01-31 | 2014-08-05 | Sunedison Semiconductor Limited | Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods |
JP2012204501A (ja) * | 2011-03-24 | 2012-10-22 | Sony Corp | 半導体装置、電子デバイス、及び、半導体装置の製造方法 |
FR2980916B1 (fr) * | 2011-10-03 | 2014-03-28 | Soitec Silicon On Insulator | Procede de fabrication d'une structure de type silicium sur isolant |
US8637381B2 (en) * | 2011-10-17 | 2014-01-28 | International Business Machines Corporation | High-k dielectric and silicon nitride box region |
JP2013157586A (ja) * | 2012-01-27 | 2013-08-15 | Mtec:Kk | 化合物半導体 |
US8633118B2 (en) * | 2012-02-01 | 2014-01-21 | Tokyo Electron Limited | Method of forming thin metal and semi-metal layers by thermal remote oxygen scavenging |
FR3003684B1 (fr) | 2013-03-25 | 2015-03-27 | Soitec Silicon On Insulator | Procede de dissolution d'une couche de dioxyde de silicium. |
KR102336517B1 (ko) | 2015-09-24 | 2021-12-07 | 에스케이텔레콤 주식회사 | 심볼 입력 방법 및 그 장치 |
-
2016
- 2016-10-13 FR FR1659917A patent/FR3057705B1/fr active Active
-
2017
- 2017-09-27 TW TW106133228A patent/TWI641040B/zh active
- 2017-09-29 JP JP2019518498A patent/JP6801154B2/ja active Active
- 2017-09-29 SG SG11201903019XA patent/SG11201903019XA/en unknown
- 2017-09-29 WO PCT/EP2017/074823 patent/WO2018069067A1/fr active Application Filing
- 2017-09-29 CN CN201780063006.5A patent/CN109844911B/zh active Active
- 2017-09-29 KR KR1020197011145A patent/KR102217707B1/ko active IP Right Grant
- 2017-09-29 US US16/342,133 patent/US10847370B2/en active Active
- 2017-09-29 DE DE112017005180.0T patent/DE112017005180T5/de active Pending
Also Published As
Publication number | Publication date |
---|---|
JP2019535144A (ja) | 2019-12-05 |
DE112017005180T5 (de) | 2019-07-04 |
CN109844911A (zh) | 2019-06-04 |
TW201814785A (zh) | 2018-04-16 |
CN109844911B (zh) | 2023-03-24 |
FR3057705A1 (fr) | 2018-04-20 |
TWI641040B (zh) | 2018-11-11 |
JP6801154B2 (ja) | 2020-12-16 |
KR20190047083A (ko) | 2019-05-07 |
KR102217707B1 (ko) | 2021-02-19 |
US20190259617A1 (en) | 2019-08-22 |
WO2018069067A1 (fr) | 2018-04-19 |
SG11201903019XA (en) | 2019-05-30 |
US10847370B2 (en) | 2020-11-24 |
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