FR2936356B1 - Procede de dissolution locale de la couche d'oxyde dans une structure de type semi-conducteur sur isolant - Google Patents

Procede de dissolution locale de la couche d'oxyde dans une structure de type semi-conducteur sur isolant

Info

Publication number
FR2936356B1
FR2936356B1 FR0856383A FR0856383A FR2936356B1 FR 2936356 B1 FR2936356 B1 FR 2936356B1 FR 0856383 A FR0856383 A FR 0856383A FR 0856383 A FR0856383 A FR 0856383A FR 2936356 B1 FR2936356 B1 FR 2936356B1
Authority
FR
France
Prior art keywords
insulation
oxide layer
type structure
semiconductor type
locally dissolving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0856383A
Other languages
English (en)
Other versions
FR2936356A1 (fr
Inventor
Christelle Veytizou
Fabrice Gritti
Eric Guiot
Oleg Kononchuk
Didier Landru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0856383A priority Critical patent/FR2936356B1/fr
Priority to TW098131203A priority patent/TWI514474B/zh
Priority to JP2011527350A priority patent/JP5351271B2/ja
Priority to CN2009801313388A priority patent/CN102119440B/zh
Priority to EP09815672.2A priority patent/EP2329523B1/fr
Priority to KR1020117006368A priority patent/KR101572070B1/ko
Priority to PCT/EP2009/062219 priority patent/WO2010034696A1/fr
Priority to US13/062,996 priority patent/US8324072B2/en
Publication of FR2936356A1 publication Critical patent/FR2936356A1/fr
Application granted granted Critical
Publication of FR2936356B1 publication Critical patent/FR2936356B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
FR0856383A 2008-09-23 2008-09-23 Procede de dissolution locale de la couche d'oxyde dans une structure de type semi-conducteur sur isolant Active FR2936356B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR0856383A FR2936356B1 (fr) 2008-09-23 2008-09-23 Procede de dissolution locale de la couche d'oxyde dans une structure de type semi-conducteur sur isolant
TW098131203A TWI514474B (zh) 2008-09-23 2009-09-16 用於局部溶解位在絕緣底半導體型結構中的氧化物層之方法
CN2009801313388A CN102119440B (zh) 2008-09-23 2009-09-21 在绝缘体上半导体型结构中局部溶解氧化物层的方法
EP09815672.2A EP2329523B1 (fr) 2008-09-23 2009-09-21 Procédé de dissolution locale de la couche d'oxyde dans une structure de type semi-conducteur sur isolant
JP2011527350A JP5351271B2 (ja) 2008-09-23 2009-09-21 セミコンダクタ−オン−インシュレータ型構造中の酸化物層を局所的に溶解する方法
KR1020117006368A KR101572070B1 (ko) 2008-09-23 2009-09-21 반도체-온-절연체 유형 구조에서 산화물 층을 국지적으로 해체하기 위한 프로세스
PCT/EP2009/062219 WO2010034696A1 (fr) 2008-09-23 2009-09-21 Processus de dissolution locale de la couche d’oxyde dans une structure de type semi-conducteur-sur-isolant
US13/062,996 US8324072B2 (en) 2008-09-23 2009-09-21 Process for locally dissolving the oxide layer in a semiconductor-on-insulator type structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0856383A FR2936356B1 (fr) 2008-09-23 2008-09-23 Procede de dissolution locale de la couche d'oxyde dans une structure de type semi-conducteur sur isolant

Publications (2)

Publication Number Publication Date
FR2936356A1 FR2936356A1 (fr) 2010-03-26
FR2936356B1 true FR2936356B1 (fr) 2010-10-22

Family

ID=40585519

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0856383A Active FR2936356B1 (fr) 2008-09-23 2008-09-23 Procede de dissolution locale de la couche d'oxyde dans une structure de type semi-conducteur sur isolant

Country Status (8)

Country Link
US (1) US8324072B2 (fr)
EP (1) EP2329523B1 (fr)
JP (1) JP5351271B2 (fr)
KR (1) KR101572070B1 (fr)
CN (1) CN102119440B (fr)
FR (1) FR2936356B1 (fr)
TW (1) TWI514474B (fr)
WO (1) WO2010034696A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2972564B1 (fr) 2011-03-08 2016-11-04 S O I Tec Silicon On Insulator Tech Procédé de traitement d'une structure de type semi-conducteur sur isolant
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
FR2987166B1 (fr) 2012-02-16 2017-05-12 Soitec Silicon On Insulator Procede de transfert d'une couche
FR2995444B1 (fr) * 2012-09-10 2016-11-25 Soitec Silicon On Insulator Procede de detachement d'une couche
FR3003684B1 (fr) * 2013-03-25 2015-03-27 Soitec Silicon On Insulator Procede de dissolution d'une couche de dioxyde de silicium.
US10026642B2 (en) 2016-03-07 2018-07-17 Sunedison Semiconductor Limited (Uen201334164H) Semiconductor on insulator structure comprising a sacrificial layer and method of manufacture thereof
FR3057705B1 (fr) * 2016-10-13 2019-04-12 Soitec Procede de dissolution d'un oxyde enterre dans une plaquette de silicium sur isolant
US10896824B2 (en) * 2018-12-14 2021-01-19 Tokyo Electron Limited Roughness reduction methods for materials using illuminated etch solutions

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5985735A (en) * 1995-09-29 1999-11-16 Intel Corporation Trench isolation process using nitrogen preconditioning to reduce crystal defects
US6350659B1 (en) * 1999-09-01 2002-02-26 Agere Systems Guardian Corp. Process of making semiconductor device having regions of insulating material formed in a semiconductor substrate
US6300218B1 (en) * 2000-05-08 2001-10-09 International Business Machines Corporation Method for patterning a buried oxide thickness for a separation by implanted oxygen (simox) process
JP4631347B2 (ja) * 2004-08-06 2011-02-16 株式会社Ｓｕｍｃｏ 部分ｓｏｉ基板およびその製造方法
US8138061B2 (en) * 2005-01-07 2012-03-20 International Business Machines Corporation Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide
US20070020877A1 (en) * 2005-07-21 2007-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Shallow trench isolation structure and method of fabricating the same
US8754446B2 (en) * 2006-08-30 2014-06-17 International Business Machines Corporation Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material
JP2008159811A (ja) * 2006-12-22 2008-07-10 Siltronic Ag Ｓｏｉウェーハの製造方法ならびにｓｏｉウェーハ
FR2910702B1 (fr) 2006-12-26 2009-04-03 Soitec Silicon On Insulator Procede de fabrication d'un substrat mixte
KR101358361B1 (ko) 2006-12-26 2014-02-06 소이텍 절연체 상 반도체 구조물을 제조하는 방법
WO2008114099A1 (fr) * 2007-03-19 2008-09-25 S.O.I.Tec Silicon On Insulator Technologies Silicium sur isolant mince à motifs
JP2011504655A (ja) * 2007-11-23 2011-02-10 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ 精密な酸化物の溶解
FR2941324B1 (fr) * 2009-01-22 2011-04-29 Soitec Silicon On Insulator Procede de dissolution de la couche d'oxyde dans la couronne d'une structure de type semi-conducteur sur isolant.

Also Published As

Publication number Publication date
TWI514474B (zh) 2015-12-21
EP2329523A1 (fr) 2011-06-08
WO2010034696A1 (fr) 2010-04-01
KR101572070B1 (ko) 2015-11-26
KR20110055676A (ko) 2011-05-25
CN102119440A (zh) 2011-07-06
US8324072B2 (en) 2012-12-04
CN102119440B (zh) 2013-12-25
US20120094496A1 (en) 2012-04-19
FR2936356A1 (fr) 2010-03-26
TW201019396A (en) 2010-05-16
EP2329523B1 (fr) 2013-09-11
JP2012503322A (ja) 2012-02-02
JP5351271B2 (ja) 2013-11-27

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