FR2978605B1 - Procede de fabrication d'une structure semi-conductrice comprenant une couche fonctionnalisee sur un substrat support - Google Patents
Procede de fabrication d'une structure semi-conductrice comprenant une couche fonctionnalisee sur un substrat supportInfo
- Publication number
- FR2978605B1 FR2978605B1 FR1156910A FR1156910A FR2978605B1 FR 2978605 B1 FR2978605 B1 FR 2978605B1 FR 1156910 A FR1156910 A FR 1156910A FR 1156910 A FR1156910 A FR 1156910A FR 2978605 B1 FR2978605 B1 FR 2978605B1
- Authority
- FR
- France
- Prior art keywords
- manufacturing
- support substrate
- semiconductor structure
- functionalized layer
- functionalized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1156910A FR2978605B1 (fr) | 2011-07-28 | 2011-07-28 | Procede de fabrication d'une structure semi-conductrice comprenant une couche fonctionnalisee sur un substrat support |
KR20120081307A KR101369007B1 (ko) | 2011-07-28 | 2012-07-25 | 지지기판에 기능화 층을 구비하는 반도체 구조물을 제조하기 위한 프로세스 |
US13/557,959 US9087767B2 (en) | 2011-07-28 | 2012-07-25 | Process for manufacturing a semiconductor structure comprising a functionalized layer on a support substrate |
CN201210262813.9A CN102903610B (zh) | 2011-07-28 | 2012-07-26 | 制造包括位于支撑衬底上的功能化层的半导体结构的工艺 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1156910A FR2978605B1 (fr) | 2011-07-28 | 2011-07-28 | Procede de fabrication d'une structure semi-conductrice comprenant une couche fonctionnalisee sur un substrat support |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2978605A1 FR2978605A1 (fr) | 2013-02-01 |
FR2978605B1 true FR2978605B1 (fr) | 2015-10-16 |
Family
ID=45001913
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1156910A Active FR2978605B1 (fr) | 2011-07-28 | 2011-07-28 | Procede de fabrication d'une structure semi-conductrice comprenant une couche fonctionnalisee sur un substrat support |
Country Status (4)
Country | Link |
---|---|
US (1) | US9087767B2 (fr) |
KR (1) | KR101369007B1 (fr) |
CN (1) | CN102903610B (fr) |
FR (1) | FR2978605B1 (fr) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9098666B2 (en) | 2012-11-28 | 2015-08-04 | Qualcomm Incorporated | Clock distribution network for 3D integrated circuit |
US9064077B2 (en) | 2012-11-28 | 2015-06-23 | Qualcomm Incorporated | 3D floorplanning using 2D and 3D blocks |
US9536840B2 (en) | 2013-02-12 | 2017-01-03 | Qualcomm Incorporated | Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods |
US20140225218A1 (en) * | 2013-02-12 | 2014-08-14 | Qualcomm Incorporated | Ion reduced, ion cut-formed three-dimensional (3d) integrated circuits (ic) (3dics), and related methods and systems |
US9041448B2 (en) | 2013-03-05 | 2015-05-26 | Qualcomm Incorporated | Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods |
US9177890B2 (en) | 2013-03-07 | 2015-11-03 | Qualcomm Incorporated | Monolithic three dimensional integration of semiconductor integrated circuits |
US9171608B2 (en) | 2013-03-15 | 2015-10-27 | Qualcomm Incorporated | Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods |
FR3063834B1 (fr) * | 2017-03-10 | 2021-04-30 | Soitec Silicon On Insulator | Procede de fabrication d'un dispositif semi-conducteur tridimensionnel |
FR3116940B1 (fr) * | 2020-11-27 | 2023-06-09 | Commissariat Energie Atomique | Procédé basse température de fabrication d’un substrat semiconducteur sur isolant |
CN116216630B (zh) * | 2023-04-28 | 2023-07-21 | 润芯感知科技(南昌)有限公司 | 一种半导体器件及其制造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6103599A (en) * | 1997-07-25 | 2000-08-15 | Silicon Genesis Corporation | Planarizing technique for multilayered substrates |
FR2773261B1 (fr) * | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
FR2842349B1 (fr) | 2002-07-09 | 2005-02-18 | Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon | |
JP4794810B2 (ja) * | 2003-03-20 | 2011-10-19 | シャープ株式会社 | 半導体装置の製造方法 |
WO2005069356A1 (fr) | 2004-01-15 | 2005-07-28 | Japan Science And Technology Agency | Procede de production d'un film mince monocristallin et dispositif a film mince monocristallin |
TWI283442B (en) * | 2004-09-09 | 2007-07-01 | Sez Ag | Method for selective etching |
EP1894234B1 (fr) * | 2005-02-28 | 2021-11-03 | Silicon Genesis Corporation | Procédé de rigidification du substrat et système pour un transfert de couche. |
JP2006297502A (ja) | 2005-04-15 | 2006-11-02 | Toshiba Corp | 半導体装置及びその製造方法 |
US8241995B2 (en) * | 2006-09-18 | 2012-08-14 | International Business Machines Corporation | Bonding of substrates including metal-dielectric patterns with metal raised above dielectric |
JP5415676B2 (ja) * | 2007-05-30 | 2014-02-12 | 信越化学工業株式会社 | Soiウェーハの製造方法 |
SG171714A1 (en) * | 2008-12-19 | 2011-07-28 | Soitec Silicon On Insulator | Strain engineered composite semiconductor substrates and methods of forming same |
US8058137B1 (en) * | 2009-04-14 | 2011-11-15 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8557679B2 (en) * | 2010-06-30 | 2013-10-15 | Corning Incorporated | Oxygen plasma conversion process for preparing a surface for bonding |
US8461017B2 (en) | 2010-07-19 | 2013-06-11 | Soitec | Methods of forming bonded semiconductor structures using a temporary carrier having a weakened ion implant region for subsequent separation along the weakened region |
SG177817A1 (en) | 2010-07-19 | 2012-02-28 | Soitec Silicon On Insulator | Temporary semiconductor structure bonding methods and related bonded semiconductor structures |
US9000557B2 (en) * | 2012-03-17 | 2015-04-07 | Zvi Or-Bach | Semiconductor device and structure |
-
2011
- 2011-07-28 FR FR1156910A patent/FR2978605B1/fr active Active
-
2012
- 2012-07-25 US US13/557,959 patent/US9087767B2/en active Active
- 2012-07-25 KR KR20120081307A patent/KR101369007B1/ko active IP Right Grant
- 2012-07-26 CN CN201210262813.9A patent/CN102903610B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US9087767B2 (en) | 2015-07-21 |
KR20130014380A (ko) | 2013-02-07 |
FR2978605A1 (fr) | 2013-02-01 |
CN102903610A (zh) | 2013-01-30 |
KR101369007B1 (ko) | 2014-02-27 |
CN102903610B (zh) | 2015-12-02 |
US20130026608A1 (en) | 2013-01-31 |
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Legal Events
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Owner name: SOITEC, FR Effective date: 20130208 |
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