FR2842349B1 - Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon - Google Patents

Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon

Info

Publication number
FR2842349B1
FR2842349B1 FR0208600A FR0208600A FR2842349B1 FR 2842349 B1 FR2842349 B1 FR 2842349B1 FR 0208600 A FR0208600 A FR 0208600A FR 0208600 A FR0208600 A FR 0208600A FR 2842349 B1 FR2842349 B1 FR 2842349B1
Authority
FR
France
Prior art keywords
layer
lattice parameter
buffer layer
semiconductor material
relaxed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0208600A
Other languages
English (en)
Other versions
FR2842349A1 (fr
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to FR0208600A priority Critical patent/FR2842349B1/fr
Priority to US10/614,327 priority patent/US7018910B2/en
Priority to CNB038162032A priority patent/CN100477150C/zh
Priority to JP2004519128A priority patent/JP2005532688A/ja
Priority to AU2003249475A priority patent/AU2003249475A1/en
Priority to EP03762850A priority patent/EP1522097B9/fr
Priority to KR1020057000477A priority patent/KR100796832B1/ko
Priority to DE60329192T priority patent/DE60329192D1/de
Priority to PCT/IB2003/003466 priority patent/WO2004006327A2/fr
Priority to TW092118765A priority patent/TWI289900B/zh
Priority to EP03762848A priority patent/EP1535326B1/fr
Priority to DE60329293T priority patent/DE60329293D1/de
Priority to JP2004519126A priority patent/JP4904478B2/ja
Priority to AU2003250462A priority patent/AU2003250462A1/en
Priority to PCT/IB2003/003497 priority patent/WO2004006311A2/fr
Priority to AT03762848T priority patent/ATE442667T1/de
Priority to AT03762850T priority patent/ATE443344T1/de
Publication of FR2842349A1 publication Critical patent/FR2842349A1/fr
Priority to US11/032,844 priority patent/US6991956B2/en
Application granted granted Critical
Publication of FR2842349B1 publication Critical patent/FR2842349B1/fr
Priority to US11/106,135 priority patent/US7510949B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
FR0208600A 2002-07-09 2002-07-09 Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon Expired - Fee Related FR2842349B1 (fr)

Priority Applications (19)

Application Number Priority Date Filing Date Title
FR0208600A FR2842349B1 (fr) 2002-07-09 2002-07-09 Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon
US10/614,327 US7018910B2 (en) 2002-07-09 2003-07-08 Transfer of a thin layer from a wafer comprising a buffer layer
AU2003250462A AU2003250462A1 (en) 2002-07-09 2003-07-09 Transfer of a thin layer from a wafer comprising a buffer layer
AU2003249475A AU2003249475A1 (en) 2002-07-09 2003-07-09 Transfer of a thin layer from a wafer comprising a buffer layer
EP03762850A EP1522097B9 (fr) 2002-07-09 2003-07-09 Transfert d'une couche mince depuis une tranche comprenant une couche tampon
KR1020057000477A KR100796832B1 (ko) 2002-07-09 2003-07-09 완충층을 포함하는 웨이퍼로부터 박층의 이송
DE60329192T DE60329192D1 (de) 2002-07-09 2003-07-09 Transfer einer dünnschicht von einem wafer mit einer pufferschicht
PCT/IB2003/003466 WO2004006327A2 (fr) 2002-07-09 2003-07-09 Transfert d'une couche mince d'une tranche semi-conductrice comportant une couche tampon
TW092118765A TWI289900B (en) 2002-07-09 2003-07-09 Transfer of a thin layer from a wafer comprising a buffer layer
EP03762848A EP1535326B1 (fr) 2002-07-09 2003-07-09 Transfert d'une couche mince d'une tranche semi-conductrice comportant une couche tampon
CNB038162032A CN100477150C (zh) 2002-07-09 2003-07-09 制造包含薄半导体层的结构的方法、所获得的中间结构以及该方法的应用
JP2004519126A JP4904478B2 (ja) 2002-07-09 2003-07-09 バッファ層を備えるウエハからの薄層の転移
JP2004519128A JP2005532688A (ja) 2002-07-09 2003-07-09 バッファ層を備えるウエハからの薄層の転移
PCT/IB2003/003497 WO2004006311A2 (fr) 2002-07-09 2003-07-09 Transfert d'une couche mince depuis une tranche comprenant une couche tampon
AT03762848T ATE442667T1 (de) 2002-07-09 2003-07-09 Transfer einer dünnschicht von einem wafer mit einer pufferschicht
AT03762850T ATE443344T1 (de) 2002-07-09 2003-07-09 Übertragung einer dünnen schicht von einer scheibe mit einer pufferschicht
DE60329293T DE60329293D1 (de) 2002-07-09 2003-07-09 Übertragung einer dünnen schicht von einer scheibe mit einer pufferschicht
US11/032,844 US6991956B2 (en) 2002-07-09 2005-01-10 Methods for transferring a thin layer from a wafer having a buffer layer
US11/106,135 US7510949B2 (en) 2002-07-09 2005-04-13 Methods for producing a multilayer semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0208600A FR2842349B1 (fr) 2002-07-09 2002-07-09 Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon

Publications (2)

Publication Number Publication Date
FR2842349A1 FR2842349A1 (fr) 2004-01-16
FR2842349B1 true FR2842349B1 (fr) 2005-02-18

Family

ID=29763664

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0208600A Expired - Fee Related FR2842349B1 (fr) 2002-07-09 2002-07-09 Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon

Country Status (11)

Country Link
US (1) US6991956B2 (fr)
EP (2) EP1535326B1 (fr)
JP (2) JP2005532688A (fr)
KR (1) KR100796832B1 (fr)
CN (1) CN100477150C (fr)
AT (2) ATE442667T1 (fr)
AU (2) AU2003249475A1 (fr)
DE (2) DE60329192D1 (fr)
FR (1) FR2842349B1 (fr)
TW (1) TWI289900B (fr)
WO (2) WO2004006327A2 (fr)

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US7018910B2 (en) * 2002-07-09 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Transfer of a thin layer from a wafer comprising a buffer layer
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FR2867307B1 (fr) 2004-03-05 2006-05-26 Soitec Silicon On Insulator Traitement thermique apres detachement smart-cut
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US7495266B2 (en) * 2004-06-16 2009-02-24 Massachusetts Institute Of Technology Strained silicon-on-silicon by wafer bonding and layer transfer
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FR2886053B1 (fr) 2005-05-19 2007-08-10 Soitec Silicon On Insulator Procede de gravure chimique uniforme
FR2886052B1 (fr) 2005-05-19 2007-11-23 Soitec Silicon On Insulator Traitement de surface apres gravure selective
FR2888400B1 (fr) 2005-07-08 2007-10-19 Soitec Silicon On Insulator Procede de prelevement de couche
KR100707654B1 (ko) 2005-07-26 2007-04-13 동부일렉트로닉스 주식회사 반도체 장치의 소자 분리 구조 및 그 형성방법
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
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Also Published As

Publication number Publication date
US6991956B2 (en) 2006-01-31
AU2003249475A1 (en) 2004-01-23
ATE442667T1 (de) 2009-09-15
JP4904478B2 (ja) 2012-03-28
TW200411820A (en) 2004-07-01
FR2842349A1 (fr) 2004-01-16
KR20050018984A (ko) 2005-02-28
DE60329192D1 (de) 2009-10-22
WO2004006311A3 (fr) 2004-03-04
CN1666330A (zh) 2005-09-07
EP1522097B9 (fr) 2010-03-03
EP1522097A2 (fr) 2005-04-13
AU2003250462A1 (en) 2004-01-23
WO2004006311A2 (fr) 2004-01-15
JP2005532688A (ja) 2005-10-27
EP1535326A2 (fr) 2005-06-01
ATE443344T1 (de) 2009-10-15
DE60329293D1 (de) 2009-10-29
KR100796832B1 (ko) 2008-01-22
AU2003250462A8 (en) 2004-01-23
WO2004006327A3 (fr) 2004-03-04
US20050191825A1 (en) 2005-09-01
EP1522097B1 (fr) 2009-09-16
TWI289900B (en) 2007-11-11
JP2005532687A (ja) 2005-10-27
WO2004006327A2 (fr) 2004-01-15
EP1535326B1 (fr) 2009-09-09
CN100477150C (zh) 2009-04-08

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