ATE465514T1 - Herstellungsverfahren für eine bruchzone in einem substrat durch koimplantation - Google Patents

Herstellungsverfahren für eine bruchzone in einem substrat durch koimplantation

Info

Publication number
ATE465514T1
ATE465514T1 AT03767871T AT03767871T ATE465514T1 AT E465514 T1 ATE465514 T1 AT E465514T1 AT 03767871 T AT03767871 T AT 03767871T AT 03767871 T AT03767871 T AT 03767871T AT E465514 T1 ATE465514 T1 AT E465514T1
Authority
AT
Austria
Prior art keywords
principal
implantation
depth
species
substrate
Prior art date
Application number
AT03767871T
Other languages
English (en)
Inventor
Bernard Aspar
Christelle Lagahe
Nicolas Sousbie
Jean-Francois Michaud
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE465514T1 publication Critical patent/ATE465514T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Vapour Deposition (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Laminated Bodies (AREA)
  • Moulding By Coating Moulds (AREA)
  • Semiconductor Memories (AREA)
  • Silicon Compounds (AREA)
AT03767871T 2002-11-07 2003-10-31 Herstellungsverfahren für eine bruchzone in einem substrat durch koimplantation ATE465514T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0213934A FR2847075B1 (fr) 2002-11-07 2002-11-07 Procede de formation d'une zone fragile dans un substrat par co-implantation
PCT/FR2003/003256 WO2004044976A1 (fr) 2002-11-07 2003-10-31 Procede de formation d'une zone fragile dans un substrat par co-implantation

Publications (1)

Publication Number Publication Date
ATE465514T1 true ATE465514T1 (de) 2010-05-15

Family

ID=32116441

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03767871T ATE465514T1 (de) 2002-11-07 2003-10-31 Herstellungsverfahren für eine bruchzone in einem substrat durch koimplantation

Country Status (11)

Country Link
US (1) US20070037363A1 (de)
EP (1) EP1559138B1 (de)
JP (2) JP5258146B2 (de)
KR (2) KR101174594B1 (de)
CN (1) CN100587940C (de)
AT (1) ATE465514T1 (de)
AU (1) AU2003292305A1 (de)
DE (1) DE60332261D1 (de)
FR (1) FR2847075B1 (de)
TW (1) TWI323912B (de)
WO (1) WO2004044976A1 (de)

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US7176108B2 (en) 2002-11-07 2007-02-13 Soitec Silicon On Insulator Method of detaching a thin film at moderate temperature after co-implantation
FR2848336B1 (fr) 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
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US7772087B2 (en) 2003-12-19 2010-08-10 Commissariat A L'energie Atomique Method of catastrophic transfer of a thin film after co-implantation
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FR2886051B1 (fr) 2005-05-20 2007-08-10 Commissariat Energie Atomique Procede de detachement d'un film mince
FR2889887B1 (fr) 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
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FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
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FR2899378B1 (fr) 2006-03-29 2008-06-27 Commissariat Energie Atomique Procede de detachement d'un film mince par fusion de precipites
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KR101484296B1 (ko) 2007-06-26 2015-01-19 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 기판의 제작방법
FR2922359B1 (fr) * 2007-10-12 2009-12-18 Commissariat Energie Atomique Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire
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US20110207306A1 (en) * 2010-02-22 2011-08-25 Sarko Cherekdjian Semiconductor structure made using improved ion implantation process
FR2981501B1 (fr) * 2011-10-17 2016-05-13 Soitec Silicon On Insulator Procédé de transfert de couches matériau dans des processus d’intégration 3d et structures et dispositifs associes
TWI573198B (zh) * 2011-09-27 2017-03-01 索泰克公司 在三度空間集積製程中轉移材料層之方法及其相關結構與元件
US8673733B2 (en) 2011-09-27 2014-03-18 Soitec Methods of transferring layers of material in 3D integration processes and related structures and devices
US8841742B2 (en) 2011-09-27 2014-09-23 Soitec Low temperature layer transfer process using donor structure with material in recesses in transfer layer, semiconductor structures fabricated using such methods
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CN104979425B (zh) * 2014-04-09 2017-03-15 中国科学院上海高等研究院 一种应用于层转移薄膜生长的籽晶阵列的制备方法
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JP7160943B2 (ja) 2018-04-27 2022-10-25 グローバルウェーハズ カンパニー リミテッド 半導体ドナー基板からの層移転を容易にする光アシスト板状体形成
CN112262467B (zh) * 2018-06-08 2024-08-09 环球晶圆股份有限公司 将硅薄层移转的方法
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EP4414483A1 (de) 2021-10-06 2024-08-14 Shin-Etsu Handotai Co., Ltd. Verfahren zur herstellung einer heteroepitaktischen schicht

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Also Published As

Publication number Publication date
AU2003292305A1 (en) 2004-06-03
WO2004044976A1 (fr) 2004-05-27
KR20110048584A (ko) 2011-05-11
CN1708844A (zh) 2005-12-14
JP2011223011A (ja) 2011-11-04
TW200414320A (en) 2004-08-01
JP5258146B2 (ja) 2013-08-07
CN100587940C (zh) 2010-02-03
US20070037363A1 (en) 2007-02-15
JP2006505941A (ja) 2006-02-16
KR20050072793A (ko) 2005-07-12
FR2847075B1 (fr) 2005-02-18
DE60332261D1 (de) 2010-06-02
KR101116540B1 (ko) 2012-02-28
KR101174594B1 (ko) 2012-08-16
EP1559138B1 (de) 2010-04-21
FR2847075A1 (fr) 2004-05-14
EP1559138A1 (de) 2005-08-03
TWI323912B (en) 2010-04-21

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