KR101116540B1 - 공-이온주입에 의한 기판의 취약한 영역의 형성 방법 - Google Patents
공-이온주입에 의한 기판의 취약한 영역의 형성 방법 Download PDFInfo
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- KR101116540B1 KR101116540B1 KR1020057008062A KR20057008062A KR101116540B1 KR 101116540 B1 KR101116540 B1 KR 101116540B1 KR 1020057008062 A KR1020057008062 A KR 1020057008062A KR 20057008062 A KR20057008062 A KR 20057008062A KR 101116540 B1 KR101116540 B1 KR 101116540B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Abstract
Description
Claims (18)
- (a) 기판(1)에 "주요한" 화학종(4)을 "주요한" 깊이(5)로 "주요한" 이온주입을 수행하는 단계; 및(b) 상기 기판(1)에, 기판(1)을 취약화시키는데 있어서 상기 주요한 화학종(4)보다 덜 효과적인 1가지 이상의 "제2의" 화학종(2)을 상기 주요한 화학종(4)의 농도보다 더 높은 농도로 상기 주요한 깊이(5)와는 다른 "제2의" 깊이(3)로 1회 이상 "제2의" 이온주입을 수행하는 단계; 및 추가로,(c) 상기 제2의 화학종(2)의 일부분 이상을 상기 주요한 깊이(5)의 수준까지 이동시키는 단계; 및(d) 상기 주요한 깊이(5)를 따라 균열을 개시하는 단계를 포함하고, 이때 상기 단계들은 (b), (a), (c) 및 (d)의 순으로 수행되는 것을 특징으로 하는, 기판(1)에 화학종을 이온주입하여 취약한 매립 영역을 형성하고 이후에 상기 취약한 매립 영역을 따라 기판(1)의 균열을 개시하여 그로부터 얇은 층(6)을 분리시킬 수 있는, 얇은 층의 제작 방법.
- 제1항에 있어서, 제2의 깊이(3)가 주요한 깊이(5)보다 더 깊음을 특징으로 하는 제작 방법.
- 제1항에 있어서, 제2의 깊이(3)가 주요한 깊이(5)보다 더 얕음을 특징으로 하는 제작 방법.
- 제2항 또는 제3항에 있어서, 주요한 이온주입 이전에 1회 이상 제2의 이온주입을 수행함을 특징으로 하는 제작 방법.
- 제1항에 있어서, 단계 (c)를 열 처리에 의해 촉진시킴을 특징으로 하는 제작 방법.
- 제1항에 있어서, 단계 (d)를 열 처리의 보조하에 수행함을 특징으로 하는 제작 방법.
- 제5항 또는 제6항에 있어서, 단계 (c) 및 (d)를 동일한 열 처리 공정 동안 수행함을 특징으로 하는 제작 방법.
- 제5항 또는 제6항에 있어서, 단계 (b) 및 (c)의 부재하에 균열을 개시하는데 필요할 열 부하(thermal budget)보다 더 낮은 열 부하내에서 열 처리를 수행함을 특징으로 하는 제작 방법.
- 제5항 또는 제6항에 있어서, 예정된 열 부하보다 더 높은 열 부하로 균열을 개시할 수 있기 위해 필요할 양보다 더 많은 양의 제2의 화학종(2)을 이온주입함으로써 예정된 열 부하를 충족시킴을 특징으로 하는 제작 방법.
- 제5항 또는 제6항에 있어서, 열 처리가 용광로내 가열, 국소 가열 또는 레이저 가열, 또는 이들의 조합을 포함함을 특징으로 하는 제작 방법.
- 제1항 내지 제3항, 제5항 및 제6항 중 어느 한 항에 있어서, 단계 (d)가 기계적 응력의 적용을 포함함을 특징으로 하는 제작 방법.
- 제11항에 있어서, 기계적 응력이 유체의 분사물의 사용, 이온주입된 영역으로의 블레이드(blade)의 삽입, 기판(1)으로의 견인력, 전단력 또는 절곡 응력의 적용 또는 음파의 적용, 또는 이들의 조합을 포함함을 특징으로 하는 제작 방법.
- 제1항 내지 제3항, 제5항 및 제6항 중 어느 한 항에 있어서, 단계 (d)의 이전에 또는 도중에, 기판(1)으로부터 얇은 층(6)을 분리시킨 후에 상기 얇은 층(6)의 지지체로서 기능하는 증점제를 기판(1)에 적용함을 특징으로 하는 제작 방법.
- 제1항 내지 제3항, 제5항 및 제6항 중 어느 한 항에 있어서, 단계 (d)의 이전에 또는 도중에, "핸들(handle)" 지지체를 기판(1)에 적용한 후, 얇은 층(6)을 최종 지지체 상으로 전달함을 특징으로 하는 제작 방법.
- 제1항 내지 제3항, 제5항 및 제6항 중 어느 한 항에 있어서, 주요한 화학종(4)이 수소 이온 또는 원자로 구성됨을 특징으로 하는 제작 방법.
- 제1항 내지 제3항, 제5항 및 제6항 중 어느 한 항에 있어서, 제2의 화학종(2)이 1종 이상의 희유 기체의 이온들 또는 원자들을 포함함을 특징으로 하는 제작 방법.
- 제1항 내지 제3항, 제5항 및 제6항 중 어느 한 항에 따른 방법에 의해 제작됨을 특징으로 하는 얇은 층(6).
- 제17항에 있어서, 연성 또는 강성 지지체 상으로 전달됨을 특징으로 하는 얇은 층(6).
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0213934A FR2847075B1 (fr) | 2002-11-07 | 2002-11-07 | Procede de formation d'une zone fragile dans un substrat par co-implantation |
FR02/13934 | 2002-11-07 | ||
PCT/FR2003/003256 WO2004044976A1 (fr) | 2002-11-07 | 2003-10-31 | Procede de formation d'une zone fragile dans un substrat par co-implantation |
Related Child Applications (1)
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KR1020117007374A Division KR101174594B1 (ko) | 2002-11-07 | 2003-10-31 | 공-이온주입에 의한 기판의 취약한 영역의 형성 방법 |
Publications (2)
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KR20050072793A KR20050072793A (ko) | 2005-07-12 |
KR101116540B1 true KR101116540B1 (ko) | 2012-02-28 |
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KR1020057008062A KR101116540B1 (ko) | 2002-11-07 | 2003-10-31 | 공-이온주입에 의한 기판의 취약한 영역의 형성 방법 |
KR1020117007374A KR101174594B1 (ko) | 2002-11-07 | 2003-10-31 | 공-이온주입에 의한 기판의 취약한 영역의 형성 방법 |
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KR1020117007374A KR101174594B1 (ko) | 2002-11-07 | 2003-10-31 | 공-이온주입에 의한 기판의 취약한 영역의 형성 방법 |
Country Status (11)
Country | Link |
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US (1) | US20070037363A1 (ko) |
EP (1) | EP1559138B1 (ko) |
JP (2) | JP5258146B2 (ko) |
KR (2) | KR101116540B1 (ko) |
CN (1) | CN100587940C (ko) |
AT (1) | ATE465514T1 (ko) |
AU (1) | AU2003292305A1 (ko) |
DE (1) | DE60332261D1 (ko) |
FR (1) | FR2847075B1 (ko) |
TW (1) | TWI323912B (ko) |
WO (1) | WO2004044976A1 (ko) |
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2002
- 2002-11-07 FR FR0213934A patent/FR2847075B1/fr not_active Expired - Fee Related
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2003
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- 2003-10-31 KR KR1020057008062A patent/KR101116540B1/ko active IP Right Grant
- 2003-10-31 CN CN200380102438A patent/CN100587940C/zh not_active Expired - Lifetime
- 2003-10-31 KR KR1020117007374A patent/KR101174594B1/ko active IP Right Grant
- 2003-10-31 DE DE60332261T patent/DE60332261D1/de not_active Expired - Lifetime
- 2003-10-31 AU AU2003292305A patent/AU2003292305A1/en not_active Abandoned
- 2003-10-31 EP EP03767871A patent/EP1559138B1/fr not_active Expired - Lifetime
- 2003-10-31 AT AT03767871T patent/ATE465514T1/de not_active IP Right Cessation
- 2003-10-31 WO PCT/FR2003/003256 patent/WO2004044976A1/fr active Application Filing
- 2003-11-03 TW TW092130631A patent/TWI323912B/zh not_active IP Right Cessation
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2004
- 2004-05-27 US US10/534,199 patent/US20070037363A1/en not_active Abandoned
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JPH1187668A (ja) * | 1997-09-04 | 1999-03-30 | Mitsubishi Materials Shilicon Corp | Soi基板の製造方法 |
Also Published As
Publication number | Publication date |
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KR101174594B1 (ko) | 2012-08-16 |
ATE465514T1 (de) | 2010-05-15 |
TW200414320A (en) | 2004-08-01 |
JP2006505941A (ja) | 2006-02-16 |
JP5258146B2 (ja) | 2013-08-07 |
EP1559138A1 (fr) | 2005-08-03 |
KR20050072793A (ko) | 2005-07-12 |
JP2011223011A (ja) | 2011-11-04 |
US20070037363A1 (en) | 2007-02-15 |
WO2004044976A1 (fr) | 2004-05-27 |
TWI323912B (en) | 2010-04-21 |
KR20110048584A (ko) | 2011-05-11 |
DE60332261D1 (de) | 2010-06-02 |
CN1708844A (zh) | 2005-12-14 |
EP1559138B1 (fr) | 2010-04-21 |
FR2847075A1 (fr) | 2004-05-14 |
AU2003292305A1 (en) | 2004-06-03 |
CN100587940C (zh) | 2010-02-03 |
FR2847075B1 (fr) | 2005-02-18 |
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