FR2988516B1 - Procede d'implantation de fragilisation de substrats ameliore - Google Patents

Procede d'implantation de fragilisation de substrats ameliore

Info

Publication number
FR2988516B1
FR2988516B1 FR1252613A FR1252613A FR2988516B1 FR 2988516 B1 FR2988516 B1 FR 2988516B1 FR 1252613 A FR1252613 A FR 1252613A FR 1252613 A FR1252613 A FR 1252613A FR 2988516 B1 FR2988516 B1 FR 2988516B1
Authority
FR
France
Prior art keywords
improving
enhanced substrates
substrates
enhanced
improving method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1252613A
Other languages
English (en)
Other versions
FR2988516A1 (fr
Inventor
Mohamed Nadia Ben
Carole David
Camille Rigal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR1252613A priority Critical patent/FR2988516B1/fr
Priority to DE112013001656.7T priority patent/DE112013001656T5/de
Priority to CN201380015733.6A priority patent/CN104205300B/zh
Priority to US14/386,937 priority patent/US9425081B2/en
Priority to PCT/IB2013/000412 priority patent/WO2013140223A1/fr
Publication of FR2988516A1 publication Critical patent/FR2988516A1/fr
Application granted granted Critical
Publication of FR2988516B1 publication Critical patent/FR2988516B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
FR1252613A 2012-03-23 2012-03-23 Procede d'implantation de fragilisation de substrats ameliore Active FR2988516B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR1252613A FR2988516B1 (fr) 2012-03-23 2012-03-23 Procede d'implantation de fragilisation de substrats ameliore
DE112013001656.7T DE112013001656T5 (de) 2012-03-23 2013-03-14 Verbessertes Implantationsverfahren zur Bildung von Zerbrechlichkeit von Substraten
CN201380015733.6A CN104205300B (zh) 2012-03-23 2013-03-14 改进的用于衬底的脆化的注入的方法
US14/386,937 US9425081B2 (en) 2012-03-23 2013-03-14 Method of implantation for fragilization of substrates
PCT/IB2013/000412 WO2013140223A1 (fr) 2012-03-23 2013-03-14 Procédé amélioré d'implantation pour fragilisation de substrats

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1252613A FR2988516B1 (fr) 2012-03-23 2012-03-23 Procede d'implantation de fragilisation de substrats ameliore

Publications (2)

Publication Number Publication Date
FR2988516A1 FR2988516A1 (fr) 2013-09-27
FR2988516B1 true FR2988516B1 (fr) 2014-03-07

Family

ID=48095931

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1252613A Active FR2988516B1 (fr) 2012-03-23 2012-03-23 Procede d'implantation de fragilisation de substrats ameliore

Country Status (5)

Country Link
US (1) US9425081B2 (fr)
CN (1) CN104205300B (fr)
DE (1) DE112013001656T5 (fr)
FR (1) FR2988516B1 (fr)
WO (1) WO2013140223A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016081367A1 (fr) 2014-11-18 2016-05-26 Sunedison Semiconductor Limited Substrat de silicium sur isolant de grande résistivité comprenant une couche de piégeage de charge formée par co-implantation he-n2
EP3378094B1 (fr) 2015-11-20 2021-09-15 Globalwafers Co., Ltd. Procédé de fabrication consistant à lisser une surface de semi-conducteur
FR3063176A1 (fr) * 2017-02-17 2018-08-24 Soitec Masquage d'une zone au bord d'un substrat donneur lors d'une etape d'implantation ionique
JP6686962B2 (ja) * 2017-04-25 2020-04-22 信越半導体株式会社 貼り合わせウェーハの製造方法
CN112262467B (zh) 2018-06-08 2024-08-09 环球晶圆股份有限公司 将硅薄层移转的方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1302985A1 (fr) * 2000-05-30 2003-04-16 Shin-Etsu Handotai Co., Ltd Procede de fabrication d'une plaquette collee et cette derniere
FR2847075B1 (fr) * 2002-11-07 2005-02-18 Commissariat Energie Atomique Procede de formation d'une zone fragile dans un substrat par co-implantation
US6806479B1 (en) * 2003-08-13 2004-10-19 Advanced Ion Beam Technology, Inc. Apparatus and method for reducing implant angle variations across a large wafer for a batch disk
US7772087B2 (en) * 2003-12-19 2010-08-10 Commissariat A L'energie Atomique Method of catastrophic transfer of a thin film after co-implantation
JP2008244435A (ja) * 2007-01-29 2008-10-09 Silicon Genesis Corp 選択された注入角度を用いて線形加速器工程を使用した材料の自立膜の製造方法および構造
EP2320454A1 (fr) 2009-11-05 2011-05-11 S.O.I.Tec Silicon on Insulator Technologies Porte substrat et dispositif de serrage par clip
US8445358B2 (en) * 2010-03-31 2013-05-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device
US8357974B2 (en) 2010-06-30 2013-01-22 Corning Incorporated Semiconductor on glass substrate with stiffening layer and process of making the same
US20120043712A1 (en) * 2010-08-17 2012-02-23 Varian Semiconductor Equipment Associates, Inc. Mechanism and method for aligning a workpiece to a shadow mask

Also Published As

Publication number Publication date
US20150050797A1 (en) 2015-02-19
FR2988516A1 (fr) 2013-09-27
CN104205300B (zh) 2017-11-14
WO2013140223A1 (fr) 2013-09-26
CN104205300A (zh) 2014-12-10
US9425081B2 (en) 2016-08-23
DE112013001656T5 (de) 2014-12-18

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