JP2010514185A - 注入によってGaN薄層を調製および出発基板を再利用するための方法 - Google Patents
注入によってGaN薄層を調製および出発基板を再利用するための方法 Download PDFInfo
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- 229910052734 helium Inorganic materials 0.000 claims abstract description 42
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 42
- 239000001307 helium Substances 0.000 claims abstract description 41
- 239000001257 hydrogen Substances 0.000 claims abstract description 41
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims abstract description 40
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 19
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
Abstract
Description
1.微小空孔層を生じさせるために十分な濃度でイオン(または原子)を注入するための、気体種またはイオン(Hまたは希ガス)を用いた初期基板の一方の面に衝撃を与えるステップと、
2.基板のこの面の、支持体または補強材と呼ばれる第2の基板と(典型的には分子結合により)密着するステップと、
3.熱処理および/または切り離し応力の適用(例えば、2枚の基板間へのブレードの挿入および/または引張力を加えることおよび/または曲げおよび/またはせん断力を加えることおよび/または慎重に選択した出力および周波数の超音波またはマイクロ波の適用)による微小空孔層を破断するステップと、
4.基板を再利用するステップと、
を行うことによって薄膜を切り離し、時に補強材と呼ばれる支持体上にその薄膜を転写するために使用される。
ヘリウムおよび水素イオンを用いて出発基板の上記自由面に衝撃を与えるステップであって、第一にヘリウムが上記厚い領域の厚さに注入され、第二に水素が注入され、ヘリウムのドーズ量および水素のドーズ量がそれぞれ1017原子/cm2〜4.1017原子/cm2であるステップと、
出発基板の残余部からの、自由面とヘリウムおよび水素の注入深さとの間に位置しているGaNの厚い領域のすべての部分の切り離しを生じさせるようになされた破断処理を出発基板に適用するステップと、を含む。
ヘリウムイオンと、その後任意選択で水素イオンを用いて出発基板の上記自由面に衝撃を与えるステップであって、第一にヘリウムが上記厚い領域の厚さに注入され、少なくとも大部分がヘリウムからなる累積注入ドーズ量が3.1017原子/cm2〜4.5 1017原子/cm2であるステップと、
出発基板の残余部からの、自由面とヘリウムの注入深さとの間に位置しているGaNの厚い領域のすべての部分の切り離しを生じさせるようになされた破断処理を出発基板に適用するステップと、を含む。
1)注入層13を形成するための、矢印12で表されるヘリウムの衝撃によるGaN出発基板の第1の注入ステップ。この注入ステップは、1017/cm2程度〜4.1017/cm2程度のドーズ量で行われる。
2)矢印12’で表される水素の衝撃によるこの出発基板11の第2の注入ステップ。この注入ステップは、1017/cm2程度〜4.1017/cm2程度のドーズ量で行われる。
3)好ましくは低温における所与の時間の熱処理を実際には含む脆化処理ステップ。この処理ステップは、この熱処理のみによって分離するまたは破断させるために必要となるであろう熱(または熱機械)バジェットの少なくとも85%を有利に表す熱(または機械的応力を加えられている場合には熱機械)バジェットの適用に対応する。
4)この注入済み基板を、ホスト基板とも呼ばれる第2の基板17と密着させるステップ。
5)出発構造を分離して薄層15(場合によっては残余部15Aを含む)残留破断処理を適用するステップ。基板残余部16は再利用する準備が整っており、再び上記注入ステップを受ける。
GaN(70Ga14N)結晶性基板に、以下の条件下:エネルギー=90keV、ドーズ量=2.1017cm−2でHeイオンを注入し、その後以下の条件下:エネルギー=60keV、ドーズ量=2.1017cm−2でHイオンを注入する。その後、注入後の基板上に、500nm〜1μmから選択することができる厚さのSiO2保護層を、PECVD(プラズマ支援化学気相成長)プロセスによって蒸着させる。その後、280℃−1時間の超脆化アニーリングを適用する(すなわち、追加の機械的応力なしに280℃で1時間)。
GaNおよびサファイア基板の化学洗浄ステップと、
化学的機械研磨ステップと、
基板同士の密着ステップと、
によって、GaN基板を分子付着によりバルクのサファイア補強材に結合させる。
GaN(70Ga14N)結晶性基板を、LPCVD(低圧化学気相成長)プロセスによって900℃で蒸着させた、厚さ500nmのSiO2結合層で覆う。この基板に、以下の条件下:エネルギー=210keV、ドーズ量=2.1017cm−2でHeイオンを注入し、その後以下の条件下:エネルギー=120keV、ドーズ量=2.1017cm−2でHイオンを注入する。その後、300℃−44分の超脆化アニーリングを適用する。
GaN(70Ga14N)結晶性基板を、PECVD(プラズマ支援化学気相成長)プロセスによって300℃で蒸着させた、厚さ250nmのSiO2結合層で覆う。この基板に、以下の条件下:エネルギー=90keV、ドーズ量=3.1017cm−2でHeイオンを注入し、その後以下の条件下:エネルギー=60keV、ドーズ量=1017cm−2でHイオンを注入する。その後、495℃−4時間10分の超脆化アニーリングを適用する。495℃−4時間10分のアニーリングは495℃における破断熱バジェットの〜98%を表すことに留意されたい。これは、これらの条件下では、495℃−4時間15分の後破断が得られるためである。
He=2、H=1、すなわち、総量3、
He=2、H=1.5、すなわち、総量3.5、
He=1.75、H=2、すなわち、総量3.75、
He=2、H=2、すなわち、総量4、および
He=3、H=1、すなわち、総量4。
Claims (26)
- 出発基板自由面に沿った少なくとも厚い表面領域がGaNである出発基板からのGaN薄層の作製方法であって、以下のステップ:
ヘリウムおよび水素イオンを用いて出発基板の前記自由面に衝撃を与えるステップであって、第一にヘリウムが前記厚い領域の厚さに注入され、第二に水素が注入され、ヘリウムのドーズ量および水素のドーズ量がそれぞれ1.1017原子/cm2〜4.1017原子/cm2であるステップと、
出発基板の残余部からの、自由面とヘリウムおよび水素の注入深さとの間に位置しているGaNの厚い領域のすべての部分の切り離しを生じさせるようになされた破断処理を出発基板に適用するステップと、を含む方法。 - ヘリウムの注入ドーズ量が、少なくとも水素の注入ドーズ量に等しいことを特徴とする、請求項1に記載の方法。
- 破断後の出発基板の残余部が再利用されることを特徴とする、請求項1または2に記載の方法。
- 最大でも厚さ1ミクロンの最大でも1回の研磨を伴う、出発基板の残余部のその再利用前の準備処理をさらに含むことを特徴とする、請求項3に記載の方法。
- 出発基板を、切り離し前に、前記自由面を介してホスト基板と密着させることを特徴とする、請求項1から4のいずれか一項に記載の方法。
- 密着が分子結合であることを特徴とする、請求項5に記載の方法。
- ホスト基板と密着させる前に、出発基板の自由面上に少なくとも1つの層が蒸着されることを特徴とする、請求項5または6に記載の方法。
- 破断処理が、密着の前に、熱処理を含み、また水素の注入深さで出発基板の破断を得るために必要な熱機械バジェットの少なくとも85%に対応する脆化処理を、出発基板へ適用することを、その後密着の後に、残留破断処理を適用することを含むことを特徴とする、請求項5から7のいずれか一項に記載の方法。
- 熱脆化処理が、蒸気の状態の層を蒸着させるステップを含むことを特徴とする、請求項8に記載の方法。
- 脆化処理が、機械的応力を加えることを含むことを特徴とする、請求項8または9に記載の方法。
- 熱脆化処理が、高くても400℃の温度で行われることを特徴とする、請求項8から10のいずれか一項に記載の方法。
- 脆化処理が、切り離しを得るのに必要なバジェットの少なくとも95%の熱機械バジェットを備えることを特徴とする、請求項8から11のいずれか一項に記載の方法。
- 残留破断処理が熱処理を含むことを特徴とする、請求項8から12のいずれか一項に記載の方法。
- 残留破断処理が、高くても250℃に等しい温度で行われることを特徴とする、請求項13に記載の方法。
- 残留破断処理が、機械的応力を加えることを含むことを特徴とする、請求項8から14のいずれか一項に記載の方法。
- 残留破断処理が、室温で行われることを特徴とする、請求項15に記載の方法。
- 残留破断処理が、超音波の適用を含むことを特徴とする、請求項15または16に記載の方法。
- 残留破断処理が、マイクロ波の適用を含むことを特徴とする、請求項15または16に記載の方法。
- ヘリウムの注入ドーズ量が1.1017〜2.1017He+/cm2であることを特徴とする、請求項1から18のいずれか一項に記載の方法。
- 水素注入ドーズ量が1.1017〜2.1017H+/cm2の範囲内であることを特徴とする、請求項1から19のいずれか一項に記載の方法。
- 累積注入ドーズ量が近似的に3.1017原子/cm2〜4.5 1017原子/cm2であることを特徴とする、請求項1から20のいずれか一項に記載の方法。
- ヘリウム注入ステップでの注入エネルギーが、水素注入エネルギーよりも大きいことを特徴とする、請求項1から21のいずれか一項に記載の方法。
- ヘリウム注入エネルギーが90keV〜210keVで、水素注入エネルギーが60keV〜120keVであることを特徴とする、請求項1から22のいずれか一項に記載の方法。
- 任意の非結合領域を含む薄層全体の切り離しを完全にするための仕上げ熱処理を含むことを特徴とする、請求項1から23のいずれか一項に記載の方法。
- 出発基板の自由面に沿った少なくとも厚い表面領域がGaNである出発基板からのGaN薄層の作製方法であって、以下のステップ:
ヘリウムイオンと、その後任意選択で水素イオンを用いて出発基板の前記自由面に衝撃を与えるステップであって、第一にヘリウムが前記厚い領域の厚さに注入され、少なくとも大部分がヘリウムからなる累積注入ドーズ量が3.1017原子/cm2〜4.5 1017原子/cm2であるステップと、
出発基板の残余部からの、自由面とヘリウムの注入深さとの間に位置しているGaNの厚い領域のすべての部分の切り離しを生じさせるようになされた破断処理を出発基板に適用するステップと、を含む方法。 - 注入ドーズ量全体が、約4.1017/cm2程度のヘリウムからなることを特徴とする、請求項25に記載の方法。
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FR0655664 | 2006-12-19 | ||
FR0655664A FR2910179B1 (fr) | 2006-12-19 | 2006-12-19 | PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART |
PCT/FR2007/002100 WO2008093008A2 (fr) | 2006-12-19 | 2007-12-18 | Procédé de fabrication de couches minces de gan par implantation et recyclage d'un substrat de départ |
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JP2011071518A (ja) * | 2009-09-25 | 2011-04-07 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | 埋め込み型脆化層が分割によって暴露された表面から基板を超音波平坦化する方法 |
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FR2748851B1 (fr) | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
FR2848336B1 (fr) * | 2002-12-09 | 2005-10-28 | Commissariat Energie Atomique | Procede de realisation d'une structure contrainte destinee a etre dissociee |
FR2856844B1 (fr) * | 2003-06-24 | 2006-02-17 | Commissariat Energie Atomique | Circuit integre sur puce de hautes performances |
FR2861497B1 (fr) * | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
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JP2011071518A (ja) * | 2009-09-25 | 2011-04-07 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | 埋め込み型脆化層が分割によって暴露された表面から基板を超音波平坦化する方法 |
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EP2102904A2 (fr) | 2009-09-23 |
FR2910179A1 (fr) | 2008-06-20 |
WO2008093008A3 (fr) | 2009-03-19 |
JP5412289B2 (ja) | 2014-02-12 |
EP2102904B1 (fr) | 2017-12-06 |
WO2008093008A2 (fr) | 2008-08-07 |
US8778775B2 (en) | 2014-07-15 |
FR2910179B1 (fr) | 2009-03-13 |
US20100025228A1 (en) | 2010-02-04 |
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