SG11201804271QA - Manufacturing method of smoothing a semiconductor surface - Google Patents

Manufacturing method of smoothing a semiconductor surface

Info

Publication number
SG11201804271QA
SG11201804271QA SG11201804271QA SG11201804271QA SG11201804271QA SG 11201804271Q A SG11201804271Q A SG 11201804271QA SG 11201804271Q A SG11201804271Q A SG 11201804271QA SG 11201804271Q A SG11201804271Q A SG 11201804271QA SG 11201804271Q A SG11201804271Q A SG 11201804271QA
Authority
SG
Singapore
Prior art keywords
international
semiconductor
peters
pct
smoothing
Prior art date
Application number
SG11201804271QA
Inventor
Gang Wang
Charles Lottes
Sasha Kweskin
Original Assignee
Sunedison Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sunedison Semiconductor Ltd filed Critical Sunedison Semiconductor Ltd
Publication of SG11201804271QA publication Critical patent/SG11201804271QA/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02581—Transition metal or rare earth elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
  • Drying Of Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property - Organization International Bureau ..... ......,„01 (43) International Publication Date r 26 May 2017(26.05.2017) WIPO I PCT ID Hit (10) WO International 2017/087393 111111111111111111111111111111111111111111111111111111111111t111111111111111 Publication Al Number (51) International Patent Classification: (81) Designated States (unless otherwise indicated, for every HO1L 21/762 (2006.01) H01L 21/02 (2006.01) kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, (21) International Application Number: BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, PCT/US2016/062050 DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, (22) International Filing Date: HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, 15 November 2016 (15.11.2016) KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, (25) Filing Language: English OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, (26) Publication Language: English SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, (30) Priority Data: ZW. 62/257,764 20 November 2015 (20.11.2015) US (84) Designated States (unless otherwise indicated, for every (71) Applicant: SUNEDISON SEMICONDUCTOR LIM- kind of regional protection available): ARIPO (BW, GH, ITED [SG/SG]; 9 Battery Road, #15-01, Straits Trading GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, Building, Singapore 049910 (SG). TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, (72) Inventor; and TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, (71) Applicant o r US only): LOTTES, Charles, R. [US/US]; LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, 501 Pearl Drive, St. Peters, MO 63376 (US). SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, (72) Inventors: WANG, Gang; 501 Pearl Drive, St. Peters, GW, KM, ML, MR, NE, SN, TD, TG). MO 63376 (US). KVVESKIN, Sasha; 501 Pearl Drive, St. Published: Peters, MO 63376 (US). 21(3)) with international search report (Art (74) Agents: SCHUTH, Richard, A. et al.; Armstrong Teas- dale LLP, 7700 Forsyth Blvd., Suite 1800, St. Louis, MO 63105 (US). (54) Title: MANUFACTURING METHOD OF SMOOTHING A SEMICONDUCTOR SURFACE 2.4 H I ,-;Te 2.2 --; ct 21 2 ; Lk ct 1.81 E ' , = 1.6 c (t) , 1 1 X 1A-1 § 1 , 12 CD - .4t M CT\ M it-- cc O it-- 1-1 (57) : A method is provided device layer having a smooth surface. 71 High SL The for preparing ! 1 , - 1 - Medium SL STRESS semiconductor method provided involves FIG. Low SL structure, LAYER smoothing a semiconductor T 2 e.g., a semiconductor i No SL Control on substrate -1 insulator structure, comprising surface by making use N a of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smooth - 0 ness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30um X 30um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.
SG11201804271QA 2015-11-20 2016-11-15 Manufacturing method of smoothing a semiconductor surface SG11201804271QA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562257764P 2015-11-20 2015-11-20
PCT/US2016/062050 WO2017087393A1 (en) 2015-11-20 2016-11-15 Manufacturing method of smoothing a semiconductor surface

Publications (1)

Publication Number Publication Date
SG11201804271QA true SG11201804271QA (en) 2018-06-28

Family

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Family Applications (2)

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SG10201913407TA SG10201913407TA (en) 2015-11-20 2016-11-15 Manufacturing method of smoothing a semiconductor surface
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Family Applications Before (1)

Application Number Title Priority Date Filing Date
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Country Status (7)

Country Link
US (4) US10529616B2 (en)
EP (1) EP3378094B1 (en)
JP (1) JP6749394B2 (en)
CN (2) CN117198983A (en)
SG (2) SG10201913407TA (en)
TW (2) TWI626690B (en)
WO (1) WO2017087393A1 (en)

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