JP2005524241A - 仮支持部材除去を伴う基板の製造方法並びにそのための基板 - Google Patents
仮支持部材除去を伴う基板の製造方法並びにそのための基板 Download PDFInfo
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Abstract
Description
仮支持部材上に、前記第一の層と前記仮支持部材との間の界面近傍で脆弱な結合状態を生じさせて、前記第一の層の少なくとも一部を形成し、
実質的に少なくとも前記脆弱な結合のレベルで前記第一の層を選択的にそして部分的にエッチングし、
前記エッチングされた領域が前記基板上全面に一つ又はそれ以上の実質的に閉ざされた空洞を形成するように、前記エッチングされた領域を覆う第二の層を前記仮支持部材上に形成された前記第一の層上に結合させ、
前記脆弱な結合において前記仮支持部材から前記第一の層を分離するための強制力に前記結果の構造全体を晒すことを特徴とする。
第一の層と、
前記第一の層が上部に固定され、前記第一の層との間の界面に脆弱な結合状態が生じている仮支持部材と、
前記第一の層の材料内に部分的に、実質的に前記脆弱な結合のレベルに形成され、そして、前記第一の層の未処理面側の外側に開放されている一つ又はそれ以上の空洞とを備え、
前記エッチングされた領域を覆う第二の層を前記仮支持部材上に形成された前記第一の層上に接着し、前記脆弱な結合のレベルで前記仮支持部材から前記第一の層を分離させようとする圧力が前記形成された密封空洞内に生じる。
Claims (33)
- マイクロエレクトロニクス、光電子工学又は光工学における素子を作るための基板の製造方法であって、前記基板は第一の層を備え、
仮支持部材上に、前記第一の層と前記仮支持部材との間の界面近傍で脆弱な結合状態を生じさせて、前記第一の層の少なくとも一部を形成し、
実質的に少なくとも前記脆弱な結合のレベルで前記第一の層を選択的にそして部分的にエッチングし、
前記エッチングされた領域が前記基板上全面に一つ又はそれ以上の実質的に閉ざされた空洞を形成するように、前記エッチングされた領域を覆う第二の層を前記仮支持部材上に形成された前記第一の層上に結合させ、
前記脆弱な結合において前記仮支持部材から前記第一の層を分離するための強制力に前記結果の構造全体を晒す工程を備えたことを特徴とする方法。 - 前記強制力は、少なくとも部分的には、前記空洞又は前記複数の空洞に含まれる流体の圧力を上昇させることから生じることを特徴とする請求項1に記載の方法。
- 前記流体の圧力上昇は前記基板上全面でほぼ均一であることを特徴とする請求項2に記載の方法。
- 前記流体の圧力上昇は前記基板上全面で不均一であることを特徴とする請求項2に記載の方法。
- 前記流体の圧力上昇は前記基板の一端部近傍で大きいことを特徴とする請求項4に記載の方法。
- 前記流体はガスであることを特徴とする請求項2乃至6いずれかに記載の方法。
- 前記圧力上昇は前記ガスの温度を上げることにより行われることを特徴とする請求項6に記載の方法。
- 細長い複数の空洞の集合体が形成されることを特徴とする請求項1乃至7いずれかに記載の方法。
- 前記複数の空洞は均等に分布されることを特徴とする請求項8に記載の方法。
- 前記複数の空洞は前記基板上全面で均等に分布されることを特徴とする請求項9に記載の方法。
- 素子が形成される基板の有効領域を分離する中間領域内に前記複数の空洞が形成されることを特徴とする請求項10に記載の方法。
- 前記複数の空洞は互いに分離されることを特徴とする請求項1乃至11いずれかに記載の方法。
- 少なくともある複数の空洞は互いに繋がり合うチャネルを形成することを特徴とする請求項11に記載の方法。
- 少なくとも部分的に堆積により仮支持部材上に前記第一の層が形成されることを特徴とする請求項1乃至13いずれかに記載の方法。
- 前記脆弱な結合状態を前記仮支持部材と、該仮支持部材に固定され、前記堆積による薄く成長した層との間に生じさせ、前記第一の層が前記薄く成長した層と前記堆積による層とにより成ることを特徴とする請求項14に記載の方法。
- ドナー基板からの層転送により前記薄く成長した層が前記仮支持部材に固定されることを特徴とする請求項15に記載の方法。
- 前記転送された薄い層と前記仮支持部材との間の接着エネルギを抑制することにより前記脆弱な結合状態を生じさせることを特徴とする請求項16に記載の方法。
- 前記第二の層は前記第一の層のための機械的な支持部材を成し、そして前記基板の一部であることを特徴とする請求項1乃至17いずれかに記載の方法。
- 前記第一の層の材料とその近傍の前記仮支持部材の材料とは温度上昇のために互いに充分に異なる熱膨張係数を有し、前記仮支持部材と前記第二の層とに固定された前記第一の層を備える集合体が前記温度上昇に晒され、前記第一の層と前記仮支持部材との間の界面レベルで剪断強制力を生じさせることを特徴とする請求項1乃至18いずれかに記載の方法。
- 前記第二の層近傍の前記第一の層の材料と前記第二の層の材料とは、これら材料間の接着にいかなる欠陥をも生じさせないように、前記温度上昇のために充分に近い熱膨張係数を有することを特徴とする請求項19に記載の方法。
- シーリングにより前記第二の層が前記第一の層上に結合されることを特徴とする請求項1乃至20いずれかに記載の方法。
- 前記第二の層は石英で形成されることを特徴とする記載の方法。
- 前記第二の層近傍の前記第一の層の材料はモノ又はポリ金属窒化物で形成されることを特徴とする請求項22に記載の方法。
- マイクロエレクトロニクス、光電子工学又は光工学における素子を作るための基板であって、
第一の層と、
前記第一の層が上部に固定され、前記第一の層との間の界面に脆弱な結合状態が生じている仮支持部材と、
前記第一の層の材料内に部分的に、実質的に前記脆弱な結合のレベルに形成され、そして、前記第一の層の未処理面側の外側に開放されている一つ又はそれ以上の空洞とを備え、
前記エッチングされた領域を覆う第二の層を前記仮支持部材上に形成された前記第一の層上に接着し、前記脆弱な結合のレベルで前記仮支持部材から前記第一の層を分離させようとする圧力が前記形成された密封空洞内に生じることを特徴とする基板。 - 前記複数の空洞は細長い形状であることを特徴とする請求項24に記載の基板。
- 前記複数の空洞は均等に分布されていることを特徴とする請求項25に記載の基板。
- 前記複数の空洞は前記基板上全面で均等に分布されていることを特徴とする請求項26に記載の基板。
- 素子が形成される基板の有効領域を分離する中間領域内に前記複数の空洞が形成されていることを特徴とする請求項27に記載の基板。
- 前記複数の空洞は互いに分離されていることを特徴とする請求項24乃至28いずれかに記載の基板。
- 少なくともある複数の空洞は互いに繋がり合うチャネルを形成していることを特徴とする請求項24乃至29いずれかに記載の基板。
- 前記脆弱な結合状態が前記仮支持部材と堆積による薄く成長した層との間に生じており、前記基板が前記薄く成長した層と前記堆積による層とを備えていることを特徴とする請求項24乃至30いずれかに記載の基板。
- 前記第一の層の材料とその近傍の前記仮支持部材の材料とは温度上昇のために互いに充分に異なる熱膨張係数を有し、前記仮支持部材と前記第二の層とに固定された前記第一の層を備える集合体が前記温度上昇に晒され、前記第一の層と前記仮支持部材との間の界面レベルで剪断強制力が生じることを特徴とする請求項24乃至31いずれかに記載の基板。
- 前記未処理面近傍の前記第一の層の材料はモノ又はポリ金属窒化物で成ることを特徴とする請求項24乃至32いずれかに記載の基板。
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FR02/05423 | 2002-04-30 | ||
FR0205423A FR2839199B1 (fr) | 2002-04-30 | 2002-04-30 | Procede de fabrication de substrats avec detachement d'un support temporaire, et substrat associe |
PCT/IB2003/002431 WO2003094224A1 (en) | 2002-04-30 | 2003-04-30 | Process for manufacturing substrates with detachment of a temporary support, and associated substrate |
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EP (1) | EP1502298A1 (ja) |
JP (1) | JP4854958B2 (ja) |
KR (1) | KR100917941B1 (ja) |
AU (1) | AU2003232414A1 (ja) |
FR (1) | FR2839199B1 (ja) |
WO (1) | WO2003094224A1 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2866982B1 (fr) * | 2004-02-27 | 2008-05-09 | Soitec Silicon On Insulator | Procede de fabrication de composants electroniques |
EP1569263B1 (de) * | 2004-02-27 | 2011-11-23 | OSRAM Opto Semiconductors GmbH | Verfahren zum Verbinden zweier Wafer |
US7329588B2 (en) * | 2004-11-16 | 2008-02-12 | Intel Corporation | Forming a reticle for extreme ultraviolet radiation and structures formed thereby |
FR2873235A1 (fr) * | 2004-12-31 | 2006-01-20 | Soitec Silicon On Insulator | Procede d'obtention d'un substrat demontable a energie de collage controlee |
KR101047762B1 (ko) * | 2005-02-21 | 2011-07-07 | 엘지이노텍 주식회사 | 질화갈륨 박막으로부터 기판을 분리하는 방법 |
TWI256082B (en) * | 2005-06-01 | 2006-06-01 | Touch Micro System Tech | Method of segmenting a wafer |
JP2007134388A (ja) * | 2005-11-08 | 2007-05-31 | Sharp Corp | 窒化物系半導体素子とその製造方法 |
US8133803B2 (en) * | 2009-06-23 | 2012-03-13 | Academia Sinica | Method for fabricating semiconductor substrates and semiconductor devices |
KR101162084B1 (ko) * | 2010-05-06 | 2012-07-03 | 광주과학기술원 | 수직형 발광 다이오드의 제조방법 및 막질들의 분리방법 |
FR2977069B1 (fr) | 2011-06-23 | 2014-02-07 | Soitec Silicon On Insulator | Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire |
DE102011113642B4 (de) * | 2011-09-16 | 2013-06-06 | Austriamicrosystems Ag | Verfahren zur Herstellung eines Halbleiterbauelementes unter Verwendung eines Hilfsträgers |
FR2980917B1 (fr) * | 2011-09-30 | 2013-09-27 | St Microelectronics Crolles 2 | Procede de realisation d'une liaison traversante electriquement conductrice |
EP2747130B1 (en) | 2012-12-21 | 2017-10-11 | ams AG | Method of producing a removable wafer connection and a wafer-carrier assembly |
CN103474529B (zh) * | 2013-10-11 | 2016-05-11 | 聚灿光电科技股份有限公司 | 一种垂直led芯片的制作方法以及垂直led芯片 |
FR3019374A1 (fr) * | 2014-03-28 | 2015-10-02 | Soitec Silicon On Insulator | Procede de separation et de transfert de couches |
FR3041364B1 (fr) * | 2015-09-18 | 2017-10-06 | Soitec Silicon On Insulator | Procede de transfert de paves monocristallins |
FR3079659B1 (fr) * | 2018-03-29 | 2020-03-13 | Soitec | Procede de fabrication d'un substrat donneur pour la realisation d'une structure integree en trois dimensions et procede de fabrication d'une telle structure integree |
US10832933B1 (en) * | 2018-04-02 | 2020-11-10 | Facebook Technologies, Llc | Dry-etching of carrier substrate for microLED microassembly |
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JPH1145862A (ja) * | 1997-07-24 | 1999-02-16 | Denso Corp | 半導体基板の製造方法 |
WO2001093325A1 (fr) * | 2000-05-30 | 2001-12-06 | Commissariat A L'energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
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FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
US6027958A (en) | 1996-07-11 | 2000-02-22 | Kopin Corporation | Transferred flexible integrated circuit |
DE69728022T2 (de) * | 1996-12-18 | 2004-08-12 | Canon K.K. | Vefahren zum Herstellen eines Halbleiterartikels unter Verwendung eines Substrates mit einer porösen Halbleiterschicht |
JP2001523046A (ja) | 1997-11-11 | 2001-11-20 | アービン・センサーズ・コーポレイション | 回路を備える半導体ウェハをシンニングするための方法および同方法によって作られるウェハ |
US6071795A (en) * | 1998-01-23 | 2000-06-06 | The Regents Of The University Of California | Separation of thin films from transparent substrates by selective optical processing |
JP3525061B2 (ja) * | 1998-09-25 | 2004-05-10 | 株式会社東芝 | 半導体発光素子の製造方法 |
US6177359B1 (en) * | 1999-06-07 | 2001-01-23 | Agilent Technologies, Inc. | Method for detaching an epitaxial layer from one substrate and transferring it to another substrate |
FR2796491B1 (fr) * | 1999-07-12 | 2001-08-31 | Commissariat Energie Atomique | Procede de decollement de deux elements et dispositif pour sa mise en oeuvre |
US6806171B1 (en) * | 2001-08-24 | 2004-10-19 | Silicon Wafer Technologies, Inc. | Method of producing a thin layer of crystalline material |
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2002
- 2002-04-30 FR FR0205423A patent/FR2839199B1/fr not_active Expired - Lifetime
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- 2003-04-30 EP EP03747530A patent/EP1502298A1/en not_active Withdrawn
- 2003-04-30 WO PCT/IB2003/002431 patent/WO2003094224A1/en active Application Filing
- 2003-04-30 AU AU2003232414A patent/AU2003232414A1/en not_active Abandoned
- 2003-04-30 KR KR1020047017490A patent/KR100917941B1/ko active IP Right Grant
- 2003-04-30 JP JP2004502345A patent/JP4854958B2/ja not_active Expired - Lifetime
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH1145862A (ja) * | 1997-07-24 | 1999-02-16 | Denso Corp | 半導体基板の製造方法 |
WO2001093325A1 (fr) * | 2000-05-30 | 2001-12-06 | Commissariat A L'energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
Also Published As
Publication number | Publication date |
---|---|
FR2839199B1 (fr) | 2005-06-24 |
AU2003232414A1 (en) | 2003-11-17 |
US20050112885A1 (en) | 2005-05-26 |
KR100917941B1 (ko) | 2009-09-21 |
WO2003094224A8 (en) | 2004-01-15 |
WO2003094224B1 (en) | 2004-02-26 |
US7041577B2 (en) | 2006-05-09 |
EP1502298A1 (en) | 2005-02-02 |
FR2839199A1 (fr) | 2003-10-31 |
WO2003094224A1 (en) | 2003-11-13 |
KR20040102197A (ko) | 2004-12-03 |
JP4854958B2 (ja) | 2012-01-18 |
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