WO2001099169A2 - Systeme de couche d'arret de gravure - Google Patents

Systeme de couche d'arret de gravure Download PDF

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WO2001099169A2
WO2001099169A2 PCT/US2001/019613 US0119613W WO0199169A2 WO 2001099169 A2 WO2001099169 A2 WO 2001099169A2 US 0119613 W US0119613 W US 0119613W WO 0199169 A2 WO0199169 A2 WO 0199169A2
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layer
substrate
etch
siι
graded
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PCT/US2001/019613
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WO2001099169A3 (fr
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Kenneth C. Wu
Eugene A. Fitzgerald
Jeffrey T. Borenstein
Gianna Taraschi
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Massachusetts Institute Of Technology
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Priority claimed from US09/599,260 external-priority patent/US6689211B1/en
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Priority to EP01946546A priority Critical patent/EP1295319A2/fr
Priority to AU2001268577A priority patent/AU2001268577A1/en
Priority to JP2002503924A priority patent/JP2003536273A/ja
Publication of WO2001099169A2 publication Critical patent/WO2001099169A2/fr
Publication of WO2001099169A3 publication Critical patent/WO2001099169A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

Definitions

  • MEMS Microelectromechanical systems
  • MEMS form the bridge between conventional microelectronics and the physical world. They serve the entire spectrum of possible applications. MEMS include such varied devices as sensors, actuators, chemical reactors, drug delivery systems, turbines, and display technologies.
  • At the heart of any MEMS is a physical structure (a membrane, cantilever beam, bridge, arm, channel, or grating) that is "micromachined" from silicon or some other electronic material. Since MEMS are of about the same size scale and, ideally, fully integrated with associated microelectronics, naturally they should capitalize on the same materials, processes, equipment, and technologies as those of the microelectronics industry. Because the process technology for silicon is already extensively developed for VLSI electronics, silicon is the dominant material for micromachining. Silicon is also mechanically superior to compound semiconductor materials and, by far, no other electronic material has been as thoroughly studied.
  • a wide array of micromachined silicon devices are fabricated using a high boron concentration "etch-stop" layer in combination with anisotropic wet etchants such as ethylenediamine and pyrocatechol aqueous solution (EDP), potassium hydroxide aqueous solution (KOH), or hydrazine (N2H2).
  • Etch selectivity is defined as the preferential etching of one material faster than another and quantified as the ratio of the faster rate to the slower rate. Selectivity is realized for boron levels above 10 9 cm"3, and improves as boron content increases. It should be noted that etch stops are also used in bond and etch-back silicon on insulator (BESOI) processing for SOI microelectronics.
  • BESOI bond and etch-back silicon on insulator
  • etch-stop requirements differ somewhat from those of micromachining, e.g., physical dimensions and defects, but the fundamentals are the same. Hence, learning and development in one area of application can and should be leveraged in the other. In particular, advances in relaxed SiGe alloys as substrates for high speed electronics suggests that a bond-and-etch scheme for creating SiGe-on-insulator would be a desirable process for creating high speed and wireless communications systems.
  • the invention provides a SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate.
  • the etch-stop material system can vary in exact composition, but is a doped or undoped Si ⁇ - x Ge x alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition.
  • the etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/ pyrocatechol/ pyrazine (EDP), TMAH, and hydrazine.
  • EDP ethylenediamine/ pyrocatechol/ pyrazine
  • TMAH ethylenediamine/ pyrocatechol/ pyrazine
  • a cantilever can be made of this etch-stop material system, then released from its substrate and surrounding material, i.e., "micromachined", by exposure to one of these etchants.
  • Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e., differences in etch rate versus pure undoped silicon. This is attributed to the change in energy band structure by the addition of germanium. Furthermore, the nondegenerate doping in the Si ⁇ - x Ge x alloy should not affect the etch- stop behavior.
  • the etch-stop of the invention includes the use of a graded-composition buffer between the silicon substrate and the SiGe etch-stop material.
  • the buffer has a linearly-changing composition with respect to thickness, from pure silicon at the substrate/ buffer interface to a composition of germanium, and dopant if also present, at the buffer/ etch-stop interface which can still be etched at an appreciable rate.
  • germanium and concentration there is a strategic jump in germanium and concentration from the buffer side of the interface to the etch-stop material, such that the etch-stop layer is considerably more resistant to the etchant.
  • a monocrystalline etch-stop layer system for use on a monocrystalline Si substrate.
  • the system includes a substantially relaxed graded and a uniform etch-stop layer of substantially relaxed Si t -yGey.
  • the system includes a substantially relaxed graded layer of Si ⁇ - x Ge x , a uniform etch-stop layer of substantially relaxed S ⁇ - y Ge y , and a strained Si ⁇ - z Ge z layer.
  • the system includes a substantially relaxed graded layer of Si ⁇ - x Ge x , a uniform etch-stop layer of substantially relaxed S ⁇ -yGey, a second etch-stop layer of strained Si ⁇ - z Ge z , and a substantially relaxed Sii- w Ge-y layer.
  • a method of integrating device or layer includes depositing a substantially relaxed graded layer of Sii- x G ⁇ x on a Si substrate; depositing a uniform etch-stop layer of substantially relaxed Si ⁇ -yGe y on the graded buffer; and etching portions of the substrate and the graded buffer in order to release the etch-stop layer.
  • a method of integrating a device or layer includes depositing a substantially relaxed graded layer of Si ⁇ - x Ge x on a Si substrate; depositing a uniform first etch-stop layer of substantially relaxed Si ⁇ - y Ge y on the graded buffer; depositing a second etch-stop layer of strained Si ⁇ - z Ge z ; depositing a substantially relaxed Si ⁇ - w Ge w layer; etching portions of the substrate and the graded buffer in order to release the first etch-stop layer; and etching portions of the residual graded buffer in order to release the second etch-stop Si ⁇ - z Ge z layer.
  • FIGs. 1A-1D are functional block diagrams of exemplary epitaxial SiGe etch stop structures configured on a silicon substrate in accordance with the invention
  • FIG. 2 is a cross-sectional TEM micrograph of the structure of FIG. IB;
  • FIG. 3 is a cross-sectional TEM micrograph of the structure of FIG. 1C;
  • FIG. 4 is graph of dopant concentrations of the structure of FIG. 1A;
  • FIG. 5 is a graph of dopant concentrations of the structure of FIG. ID;
  • FIG. 6 A is a graph showing the cylindrical etch results of the structure of FIG. 1 A;
  • FIG. 6B is graph showing a magnification of the left side of FIG. 6A;
  • FIG. 7 is a graph showing the cylindrical etch results of the structure of FIG. ID;
  • FIG. 8 is a graph showing the etch rates for ⁇ 100> intrinsic silicon in 34% KOH at 60°C normalized by 18.29 ⁇ m/hr of the structures of FIGs. 1A-1D;
  • FIG. 9 is a photograph of a top view of a micromachined proof mass;
  • FIG. 10 is a block diagram of a process for fabricating an SiGe-on-insulator structure
  • FIG. 11A-1 IF are schematic diagrams of the fabrication process for SiGeOI
  • FIGs. 12A and 12B are IR transmission images of intrinsic voids due to particles at the bonding interface, and a demonstration of void-free bonding, and crack due to Maszara surface energy test for SiGe bonded to oxide prior to annealing, respectively;
  • FIG. 13 is a graph of oxide thickness versus oxidation time, for 700°C wet oxidation of SiGe alloys for various Ge concentration;
  • FIG. 14 is a graph showing the etching results using a
  • FIG. 15 is a cross-sectional TEM micrograph of a final exemplary SiGe on oxide structure
  • FIG. 16 is an atomic force microscope surface map of the remaining strained Si layer in the SiGeOI structure, after the 30 minute HF:H 2 O 2 :CH 3 COOH (1:2:3) etch.
  • the Si:B lattice is vertically contracted as it is horizontally expanded, leading to a smaller vertical lattice constant than the equilibrium value.
  • the material For thin layers of Si:B, it is energetically favorable for the material to be elastically strained like this, i.e., "pseudomorphic".
  • Dislocation loops are heterogeneously nucleated at the film surface or film edges and grow larger, gliding towards the substrate-film interface. When a loop meets the interface, the two ends (now called “threading” dislocations because they traverse the thickness of the film) continue to travel away from each other, trailing a line defect at the interface known as a "misfit" dislocation.
  • misfit dislocations accommodate the lattice-mismatch stress, relieving the horizontal and vertical strains and restoring the in-plane and pe ⁇ endicular lattice constants to the equilibrium value, i.e., "relaxing" the material.
  • a mesh of orthogonal ⁇ 110> misfit dislocations is the most likely configuration because of the ⁇ 111 ⁇ 110> easy slip system for these crystal structures at elevated temperatures, such as those involved in diffusion and most CND processes.
  • the effects of any dissimilar-sized substitutional atom on the silicon microstructure are the same as those of boron.
  • Electrochem. Soc. 137 , pp. 3626-31 (1990), inco ⁇ orated herein by reference, is widely considered the appropriate model.
  • specifics like absolute etch rate and dissolution products may differ, the general concept is valid for all anisotropic etchants, as they are all aqueous alkaline solutions and the contribution of the etchant is modeled as nothing more specific than H O and OH". Indeed, the existing literature shows consistent behavior among the etchants.
  • etch-rate decrease is sensitive to hole concentration and not to atomic concentration of boron or stress. They observed an etch rate drop that was proportional to the fourth power of the increase in boron concentration beyond about 3x10*9 cm"3. Four electrons are required by a red-ox etching process they described, leading them to explain the etch-stop effect in p++ material as an increased probability that the electrons are lost to Auger recombination because of the higher hole concentrations.
  • Si:B(2xl ⁇ 20cm"3) in aqueous KOH by in situ ellipsometric measurements In the case of p + -Si, a large number of holes at the surface causes spontaneous passivation with a thin oxide-like layer. The layer is not completely networked like thermal oxide, so it is etched faster and there is still transport of reactants and etch products across the layer, leading to some finite overall etch rate. The lattice strain induced by a high dopant concentration could enhance the layer's growth. Furthermore, the etch rate reduction is not a Fermi-level effect since the phenomenon is exhibited by both heavily doped p- and n-silicon. Chen et al., J. Electrochem. Soc.
  • etch stopping is attributed to the enhancement of the oxide film growth rate under high carrier concentration.
  • the key process is hole-driven oxidation at the interface, which inhibits etching by competing with a reaction for Si-Si bonds and hydroxyl radicals, but more importantly, by building the SiO x barrier.
  • p++ silicon a sufficient quantity of holes for etch-stop behavior is supplied as the converse of the electron action outlined by Seidel et al. That is, instead of electrons thermally escaping the potential well or tunneling through into the bulk crystal, holes from the bulk crystal thermally overcome or tunnel through the potential barrier to the interface.
  • this etch-stop process is dynamic, i.e., it is a continuous competition of silicon dissolution and formation/ dissolution of the oxide-like layer, whose net result is a nonzero etch rate.
  • Germanium is appealing as an etch-resistant additive because it is isoelectronic to, and perfectly miscible in, silicon and diffuses much less readily than dopants and impurities in silicon. Furthermore, the epitaxy of silicon-germanium alloys is selective with respect to silicon oxide, facilitating patterning and structuring, and even affords higher carrier mobilities to electronics monolithically integrated with MEMS.
  • isotropic etchants for pure germanium exist. Common to all of these is an oxidizer, such as HNO 3 or H 2 O 2 , and a complexing agent to remove the oxide, like HF or H 3 PO 4 .
  • an oxidizer such as HNO 3 or H 2 O 2
  • a complexing agent to remove the oxide like HF or H 3 PO 4 .
  • isotropic germanium etching by solutions such as "Superoxol", a commercially available H2O2-HF recipe. More recently, investigations have been made on various combinations of HNO3, HNO2, HF, H 2 SO4, H2SO2,CH3COOH, H2O2, and H2O.
  • the mixture does not etch pure germanium, but etches pure silicon at 5.67 ⁇ m/hr, a weak pace for micromachining prnposes. Both systems are isotropic.
  • Shang's team improved the selectivity in the same KOH-propanol-K2Cr2 ⁇ 7 solution to about 40.
  • Narozny et al., IEEE IEDM (1988) 563 were the first to use such a "strain-selective" recipe, but only realized a selectivity of 20 (for 30% germanium doped with 10*° cm"3 boron) and a sluggish etch rate of 1.5 ⁇ m/hr at room temperature for pure silicon. 26 Although the results of Shang et al. and Narozny et al. might have simply been from the well-established etch-stop ability of boron, Godbey et al., Appl. Phys. Lett. 56, p. 374 (1990), achieved a selectivity of 17 with undoped Si ⁇ .7Geo.3.
  • the invention provides a SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate.
  • the etch-stop material system can vary in exact composition, but is a doped or undoped Sii- x Ge x alloy with x generally between 0.2 and
  • the etch-stop material itself is uniform in composition.
  • the etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/ pyrocatechol/ pyrazine (EDP), TMAH, and hydrazine.
  • a cantilever can be made of this etch-stop material system, then released from its substrate and surrounding material, i.e., "micromachined", by exposure to one of these etchants.
  • These solutions generally etch any silicon containing less than 7x10 cm " of boron or undoped Si ⁇ - x Ge x alloys with x less than approximately 18.
  • the etch-stop of the invention includes the use of a graded-composition buffer between the silicon substrate and the SiGe etch-stop material.
  • the buffer has a linearly-changing composition with respect to thickness, from pure silicon at the substrate/ buffer interface to a composition of germanium, and dopant if also present, at the buffer/ etch-stop interface which can still be etched at an appreciable rate.
  • germanium and concentration there is a strategic jump in germanium and concentration from the buffer side of the interface to the etch-stop material, such that the etch-stop layer is considerably more resistant to the etchant.
  • the buffer could grade up to Sio.s5Geo. 1 5, then jump to a uniform etch-stop layer of Sio. Geo,3.
  • the composition gradient in the buffer is 5-10% Ge/micron, and the jump in Ge concentration is 5-15 relative atomic percent Ge.
  • the buffer and etch-stop materials are deposited epitaxially on a standard silicon substrate, such as by chemical vapor deposition (CND) or molecular beam epitaxy (MBE).
  • CND chemical vapor deposition
  • MBE molecular beam epitaxy
  • the germanium concentration leads to etch stop behavior, and therefore doping concentrations in the etch stop can be varied independently, without affecting etch selectivity.
  • the influence of defects is minimal.
  • the use of a graded buffer suppresses the threading dislocation density (TDD) in the top etch-stop layer, which leads to a uniform, nearly defect-free S ⁇ - x Ge x etch stop.
  • TDD threading dislocation density
  • the significance of the jump in concentration(s) at the end of the graded region is that the part must be well defined and dimensions well controlled. Thus, a high selectivity should exist between the top etch-stop layer and the end of the graded region for abrupt, predictable etch-stop behavior. A smooth compositional transition from buffer to etch-stop layer would lead to curved edges and greater dimensional variability in the micromachined part, whereas compositional jumps would yield clean, sha ⁇ edges and precise dimensions in the released structure. However, if the jump is too large, e.g., greater than ⁇ 20-25 atomic% Ge, the corresponding change in lattice constant, i.e., the lattice mismatch, would create defects.
  • the Sii- x G ⁇ x etch-stop material system which can be substituted for heavily boron-diffused layers, broadens the spectrum of available etch-stop materials, including undoped (isoelectronic) materials, thus improving the design flexibility for micromachined structures.
  • standard micromachining processes limit the dimensions of silicon sensor structures to a single uniform thickness.
  • Resonant devices for inertial sensing would benefit considerably from more flexible design in which the resonators are thinner than the seismic mass.
  • the invention provides an enabling technology for such a multi-thickness structure.
  • Such a fundamental advantage makes the novel technology widely applicable to the fabrication of MEMS by silicon micromachining.
  • a tremendously significant application is the ability to integrate mechanical and electronic devices on the same material.
  • Germanium is perfectly miscible in silicon and diffuses much less readily than dopants and impurities.
  • KOH and EDP were used in the etching.
  • KOH is a commonly studied etchant , the simplest and easiest to consider, and relatively easy and safe to use. Although details of absolute etch rate differ, various anisotropic silicon etchants have behaved consistently. Seidel et al.'s well-subscribed theory of anisotropic etching is explicitly etchant-nonspecific. Results, discussions, and conclusions regarding anisotropic etching and etch-stopping of silicon are widely considered to be valid for any anisotropic etchant. Cylindrical etching and patterned oxide masks were both used to determine the efficacy of Ge concentration on etch rate.
  • FIG. 1A is a functional block diagram of an epitaxial SiGe etch stop structure 100 (WU_2) configured on a silicon substrate 102.
  • the structure includes a plurality of relaxed graded layers 104 that vary from Si 0 . 98 Geo.o2, 5xl0 20 cm “3 B at the substrate surface, to the top surface layer of Sio.7 Ge 0 . 2 ⁇ , 10 18 cm “3 P. The thickness of each layer are provided in ⁇ m.
  • FIG. IB is a functional block diagram of an epitaxial SiGe etch stop structure 110 (WU_3) configured on a silicon substrate 112.
  • the structure includes a plurality of relaxed graded layers 114 that vary from Sio.99Geo.oi at the substrate surface, to the top surface layer of Sio. 8 Geo. ⁇ 6 .
  • FIG. 1C is a functional block diagram of an epitaxial SiGe etch stop structure 120 (WU_4) configured on a silicon substrate 122.
  • the structure includes a relaxed graded layer 124 of Si 0 . 66 Geo. 3 .
  • FIG. ID is a functional block diagram of an epitaxial SiGe etch stop structure 130 (WU_4) configured on a silicon substrate 132.
  • the structure includes a ⁇ ⁇ ⁇ plurality of relaxed graded layers 134 that vary from Sio. 9 7Ge 0 .o 3 , 3x10 cm " B at the substrate surface, to the top surface layer of Sio. 66 Geo. 34 , 4xl0 16 cm '3 B.
  • the compositional grading is known to considerably relax the superficial epitaxial layer while effectively suppressing the TDD.
  • the slow grading rate and generous thickness of these epistructures assure a well-relaxed top film.
  • the graded buffer enables etching experiments on relaxed, high quality, high germanium content alloys, an etching regime that has never been accessible before.
  • prior research dealt with pseudomo ⁇ hic Sii- ⁇ Ge x layers or low concentrations of germanium to minimize dislocations, or heavy germanium alloys saturated with threading dislocations.
  • the grading technique permits one to use the intrinsic etch-stop properties of Sii- x Ge ⁇ solid solutions.
  • FIG. 2 is a cross-sectional TEM micrograph of structure 110 (WU_3). The top surface is in the upper right direction. The parallel lines (misfit dislocations) define the graded buffer. No threading dislocations can be found, which confirms high crystalline quality. The blurred vertical bands are "bend contours", an artifact of TEM, not threading dislocations. The absence of threading dislocations in FIG. 2 confirms that structures 110
  • FIG. 3 is a cross-sectional TEM micrograph of structure 120 (WU_4). The top surface is to the right. In contrast to FIG. 2, this film is saturated with threading dislocations, which confirms poor crystalline quality. The misfit dislocations in all four of these samples are buried under such a thick overlayer that they cannot possibly affect etching from the top surface.
  • Dopant concentrations of structures 100 (WU_2) and 130 (UHV_17) are shown in the graphs of FIGs. 4 and 5 respectively.
  • the dopant concentrations were calculated from the mobilities of pure silicon and pure germanium, as indicated. Since structure 130 (UHN_17) contains 30% germanium, the true boron content lies somewhere in between, closer to the pure silicon line. Regardless, it is clear that the boron doping does not approach the levels needed for etch stopping.
  • Structure 130 was doped p-type to investigate potential interactions or synergies with germanium that were suppressed in structure 100 by intentional background n-doping.
  • top layer The characteristics of these materials (top layer) that are relevant to etching are summarized in the following table.
  • Structure 100 was used to identify the critical germanium concentration by cylindrically etching and to obtain etch rate values by etching from the top surface.
  • the cylindrical etch results of structure 100 confirm the etch-stop behavior of germanium and narrowed the threshold germanium concentration to the range of 16-22%. It was ensured that there were no effects from boron by doping the film n-type.
  • the terraces on the left of the graph, defined by the round dots, represent the layers in the epistructure. The left scale reflects the depth of each layer while the right scale relates the nominal germanium concentration of each layer.
  • the arc is the initial groove surface, and the square dots trace the etched surface.
  • FIG. 6B is a magnification of the left side of FIG. 6 A. It is clear that the etch rate increases dramatically somewhere around 18-20% germanium, suggesting that the critical germanium concentration is in that vicinity.
  • the profiles of each side of the groove are shown. The lower bar marks where the profile begins to deviate from the initial grooved shape. The depth of this point appears to be 4.8-5.0 ⁇ m below the top surface.
  • WU_2, WU_3, and UHV_17 relaxed materials with low TDDs, controvert the speculation that lattice defects serving as recombination centers cause the etch stop behavior with germanium or isoelectronic additives, respectively. Furthermore, a comparison of the etch rate of structure 120 (WU_4) to the KOH- germanium trendline indicates that even a high TDD does not influence etch stopping dramatically (if at all), nor in a predictable fashion.
  • germanium atom just as much credit as the silicon atom, since it is no longer a dopant, but rather an alloying species in the truest sense.
  • the silicon-germanium alloys in question should show a palpable influence from the etching characteristics of pure germanium, which include a slow rate in KOH.
  • FIG. 8 shows that the germanium-KOH curve is remarkably similar in shape, but not necessarily slope, to the boron-EDP curve, which ascribes its shape to the electronic etch-stop theory. It is difficult to imagine that the germanium- KOH data would just happen to resemble the boron-EDP data, based on a completely different model that warns of no applicability to germanium. That is, it is highly improbable that the true etch-stop mechanism for germanium is entirely unrelated to the true mechanism for boron when the shapes agree so well.
  • the Sii- ⁇ Ge x data resemble the p++ Si:B data, including the critical concentration and power-law dependence of the remnant etch rate, and the ⁇ ++ Si:B data is explained well by energy band effects. At these quantities, germanium is known to markedly change the band structure of silicon.
  • Germanium also has a smaller electron affinity, ⁇ , than silicon,
  • germanium decreases the electron affinity as well.
  • the shrinking bandgap and electron affinity reduce the band-bending, the potential well in the conduction band, and the potential barrier in the valence band.
  • ⁇ c and ⁇ v are the effective density of states in the conduction and valence bands, respectively, k is Boltzmann's constant, and T is temperature.
  • N c and N v will be assumed to be constant and equal to the values for pure silicon. Again, if Eg's dependence on germanium concentration is considered linear, then pi is exponentially related to germanium concentration.
  • the equilibrium hole concentration, p is defined as:
  • FIG. 9 is a photograph of a top view of a micromachined proof mass 900. Even at these low Ge concentrations, etched parts like the proof mass in FIG. 9 are possible. Higher Ge concentrations in the uniform layer ( 30%) result in extremely hard etch stops, with selectivities approaching 1000:1.
  • Si wafer that is coated with silicon dioxide. If one of the wafers is thinned, then a thin layer of Si on silicon dioxide/Si is created. Such structures are useful in low power electronics and high speed electronics since the Si active layer is isolated from a bulk Si substrate via the silicon dioxide layer.
  • the main disadvantage of this process is the difficulty in thinning one side of the silicon substrate-silicon dioxide-silicon substrate sandwich.
  • the entire wafer In order to have high reproducibility and high yield, the entire wafer must be thinned uniformly and very accurately. Buried etch stops have been used with little success. Even buried, thin layers of strained SiGe have been used, but as mentioned earlier these etch demonstrate etch selectivities «100, and therefore are not sufficient.
  • the relaxed SiGe alloys of the invention are ideally suited for this type of etch stop.
  • the etch-stop of the invention can be used to create a very uniform relaxed SiGe alloy on silicon dioxide, which in turn is on a silicon wafer. This process is shown schematically in FIG. 10.
  • the finished structure 1014 is a SiGe-on-insulator substrate. It will be appreciated that the structure 1008 can also be a bulk insulating material, such as glass or a glass ceramic.
  • Germanium is isoelectronic to and perfectly soluble in silicon, and hardly diffuses in it.
  • the deposition of silicon-germanium is selective with respect to oxide. Defects do not weaken the etch-stop efficacy.
  • the etch-stop material can be completely undoped, and according to the proposed band structure model, nondegenerate doping does not influence the etch-stop behavior. This affords enormous utility and design flexibility, especially to integration with microelectronics. To this end, germanium would even afford higher carrier mobilities.
  • this etch stop system can easily be used to integrate various strained Si electronics on relaxed SiGe on any desired substrate (eg, insulating or semiconductor substrates), where one such system is SiGe on insulator (SiGeOI). More details of this procedure are provided in the following description.
  • SIMOX separation-by-implanted-oxygen
  • wafer bonding followeded by etch-back
  • SIMOX involves implantation by oxygen followed by a high temperature anneal, and hence is attractive due to its apparent simplicity. This technique has shown some success for low Ge compositions, but for higher Ge fractions, in particular for Sio. 5 Geo. 5 , the buried oxide structure was not demonstrated, due to the thermodynamic instability of Si ⁇ - x Ge x O 2 . Simply stated, Ge is not inco ⁇ orated into the oxide, due to the volatile nature of GeO 2 , and therefore for high Ge fractions, there are insufficient Si atoms to form a stable oxide.
  • the bonding technique which involves the bonding of a SiGe wafer to an oxidized handle wafer followed by the removal of excess material, can be applied to any Ge fraction, without the problem of an unstable oxide.
  • the procedure is general, one can create SiGe on any desired substrate, including any insulating wafer.
  • the process flow for the bond/etch-back SiGeOI fabrication technique is shown schematically in FIGs. 11 A-l IF.
  • the process is separated into growth: (a) UHNCND growth of relaxed SiGe graded buffer followed by CMP, (b) re-growth of strained Si ( ⁇ -Si) and SiGe bonding layer, and bond/etch-back steps: (c) wafer bonding to insulating substrate, (d) backside grinding, (e) Si etch stopping in the graded layer, (f) SiGe etch stopping on the strained Si.
  • a relaxed 2.5 ⁇ m compositionally graded SiGe buffer a relaxed 2.5 ⁇ m compositionally graded SiGe buffer
  • the graded buffer minimizes threading dislocations and ensures that misfit are only present in the graded layers and not in the uniform composition cap, but these underlying misfits still generate strain fields which cause the formation of surface cross-hatch during growth.
  • the wafer was polished (using chemical- mechanical polishing, CMP) until the cross-hatch was no longer visible using ⁇ omarsky microscopy.
  • a strained Si structure 1104 consisting of 12 nm of strained Si, followed by a layer 1106 of 150 nm of Si 0 . 75 Geo. 25 , was grown at 650°C via UHNCVD onto the polished SiGe wafers.
  • the low growth temperature ensures minimal surface exchange and inter-diffusion, and hence guarantees a sha ⁇ interface between the Si and SiGe layers.
  • the strained Si layer acts as an etch stop during the final etch step, and depending on the thickness requirement and surface roughness constraint for the strained Si channel, may possibly also be used as a MOSFET device channel.
  • the SiGe wafer was then bonded to a thermally oxidized Si wafer 1108, with an oxide layer 1110 thickness of 200 nm.
  • a hydrophobic pre- bonding clean was performed on the wafers.
  • the standard RCA clean cannot be employed for this pu ⁇ ose since the SCI bath etches Ge and hence roughens the SiGe surface. Instead, a piranha clean (10 minutes) followed by a 50:1 HF dip (30 seconds) was used, which leaves the surface hydrophobic.
  • the wafers must also be bonded in an ultra-clean environment to ensure no intrinsic voids (as shown in the IR image in FIG. 12 A) due to particles at the wafer interfaces.
  • the wafer pair was annealed for 2 hours at 800°C in a nitrogen ambient. The moderate temperature ensures strong bonding, but is low enough to minimize the diffusion of Ge into the strained Si layer. In addition, the 2 hour anneal at this temperature allows the intrinsic hydrogen voids formed during initial annealing to diffuse.
  • the resulting pair was found to be void free using infrared imaging, and the fracture surface energy deduced with the Maszara razor test technique (FIG. 13B) was 3.7 J/m 2 (which is similar to the surface fracture energy found for Si to oxide bonding), demonstrating that the bonding is indeed strong enough to undergo further material processing, without the risk of delamination.
  • the pair was coated with nitride to protect the backside of the handle wafer during etching.
  • the backside of the SiGe wafer was then ground as at 1112, removing approximately 450 ⁇ m, and a first etch as at 1114 was performed on the wafers to remove the remaining Si from the SiGe wafers.
  • Any etch which attacks Si and not SiGe can be used (eg, KOH, TMAH).
  • KOH, TMAH a KOH mixture (30% KOH by weight in water) at 80°C, with an etching time of 2 hours can be employed to remove the backside Si from the SiGe wafer.
  • the next etch 1116 was employed to remove the remaining SiGe, and stop on the strained Si layer 1104.
  • the active ingredient of this etch consists of any Ge oxidizing agent (eg, H 2 O , HNO 3 , low temperature wet oxidation), combined with an oxide stripping agent (eg, HF).
  • a low temperature (650°C-750 °C) wet oxidation has been found to oxidize SiGe at much faster rates than Si, as shown in FIG.
  • a test sample consisting of 400 nm relaxed Sio. 7 sGeo. 2 5 on 12 nm strained Si was partially masked and the etch depth versus time was measured using a profilometer.
  • the results in FIG. 14 clearly show the high selectivity, in addition to the relatively fast etch rate of the Sio.
  • FIG. 15 shows a TEM cross-sectional image of the SiGeOI structure fabricated using the proposed technique. No structural defects, such as threading dislocations, were observed in the cross-sectional TEM of the SiGe layer. A low density of threads in the 10 5 cm “2 range was confirmed via EPD (etch pit density) of both the as-grown and bonded SiGe, which proves that there is no substantial increase in threading dislocations due to the proposed process. This is in contrast to SIMOX, which can possibly introduce many additional defects depending on the material system being implanted. In particular, the threading dislocation for implanted SiGe of various Ge fractions has not yet been reported in the literature.
  • EPD etch pit density
  • FIG. 16 An AFM scan of the strained Si surface after the final etching, is shown in FIG. 16.
  • the rms roughness was found to be roughly 1.0 nm, with a maximum peak-to- valley difference of 6.4 nm.
  • the Si etch stop layer might not be smooth enough to double as a device channel, since the surface roughness may affect device performance. If this is so, the easiest and most general approach simply requires the removal of the Si etch stop layer with KOH, or any another Si etch that is selective to the Ge composition being used.
  • the desired device structure can then be grown onto the SiGeOI substrate, including a strained Si surface channel or any other more elaborate structure.

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Abstract

L'invention concerne un système de matériau d'arrêt de gravure monocristallin SiGe sur un substrat de silicium monocristallin. La composition exacte dudit système de matériau d'arrêt de gravure peut varier, celui-ci étant constitué d'un alliage dopé ou non dopé Si1-xGex, et x étant en général compris entre 0,2 et 0,5. Dans son épaisseur, le matériau d'arrêt de gravure comprend une composition uniforme. Le matériau d'arrêt de gravure s'utilise dans le micro-usinage à l'aide d'agents de gravure aqueux anisotropes de silicium tels que l'hydroxyde de potassium, l'hydroxyde de sodium, l'hydroxide de lithium, l'éthylènediamine/pyrocatéchol/pyrazine (EDP), TMAH, et l'hydrazine. Ces solutions permettent en général de graver un silicium quelconque contenant moins de 7x1019 cm-3 d'alliages de bore ou de Si¿1-x?Gex non dopé, x étant approximativement inférieur à 18. Le silicium d'alliage avec des concentrations modérées de germanium permet d'obtenir d'excellentes sélectivités de gravure, c'est-à-dire des différences de vitesse de gravure par rapport au silicium pur non dopé. Ceci est attribué à la modification de la structure de la bande d'énergie par l'addition de germanium. De plus, le dopage non dégénéré de l'alliage Si1-xGex ne doit pas affecter le comportement du matériau d'arrêt de gravure. Le système d'arrêt de gravure de l'invention comprend l'utilisation d'un tampon à composition classée entre le substrat de silicium et le matériau d'arrêt de gravure SiGe. Le tampon possède essentiellement une composition changeant linéairement par rapport à l'épaisseur, du silicium pur à l'interface substrat/tampon à une composition de germanium et, éventuellement, de dopant, à l'interface tampon/arrêt de gravure, avec une possibilité de gravure à une vitesse appréciable. Dans le cas présent, l'augmentation stratégique de germanium et de la concentration du côté tampon de l'interface au matériau d'arrêt de gravure permet d'obtenir une couche d'arrêt de gravure nettement plus résistante à l'agent de gravure. Ce processus et la structure de la couche permettent d'utiliser toute une gamme de nouveaux matériaux de microélectronique. Les capacités d'arrêt de gravure introduisent de nouveaux processus et structures tels que les alliages SiGe relaxés sur Si, SiO2, et SiO2/Si. Ces matériaux peuvent être utilisés dans les futurs dispositifs et circuits Si MOSFET contraints.
PCT/US2001/019613 2000-06-22 2001-06-20 Systeme de couche d'arret de gravure WO2001099169A2 (fr)

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WO2002071495A1 (fr) * 2001-03-02 2002-09-12 Amberwave Systems Corporation Plate-forme de silicium germanium relachee pour electronique cmos tres rapide et circuits analogiques tres rapides
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US6555839B2 (en) 2000-05-26 2003-04-29 Amberwave Systems Corporation Buried channel strained silicon FET using a supply layer created through ion implantation
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US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
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US6991956B2 (en) 2002-07-09 2006-01-31 S.O.I.Tec Silicon On Insulator Technologies S.A. Methods for transferring a thin layer from a wafer having a buffer layer
US7018910B2 (en) 2002-07-09 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Transfer of a thin layer from a wafer comprising a buffer layer
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US7138649B2 (en) 2001-08-09 2006-11-21 Amberwave Systems Corporation Dual-channel CMOS transistors with differentially strained channels
FR2892733A1 (fr) * 2005-10-28 2007-05-04 Soitec Silicon On Insulator Relaxation de couches
EP1836725A1 (fr) * 2004-09-09 2007-09-26 Sez Ag Procédé de gravure sélective
CN100370586C (zh) * 2002-11-19 2008-02-20 国际商业机器公司 通过离子注入和热退火获得的在Si或绝缘体上硅衬底上的弛豫SiGe层
US7495266B2 (en) 2004-06-16 2009-02-24 Massachusetts Institute Of Technology Strained silicon-on-silicon by wafer bonding and layer transfer
US7535089B2 (en) 2005-11-01 2009-05-19 Massachusetts Institute Of Technology Monolithically integrated light emitting devices
US7709828B2 (en) 2001-09-24 2010-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. RF circuits including transistors having strained material layers
US8063397B2 (en) 2006-06-28 2011-11-22 Massachusetts Institute Of Technology Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission
US8129821B2 (en) 2002-06-25 2012-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Reacted conductive gate electrodes
US8748292B2 (en) 2002-06-07 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming strained-semiconductor-on-insulator device structures
US9093478B1 (en) 2014-04-11 2015-07-28 International Business Machines Corporation Integrated circuit structure with bulk silicon FinFET and methods of forming
US9842913B1 (en) 2016-05-18 2017-12-12 Globalfoundries Inc. Integrated circuit fabrication with boron etch-stop layer
US20210366763A1 (en) * 2017-03-21 2021-11-25 Soitec Semiconductor on insulator structure for a front side type imager
EP4123692A1 (fr) * 2021-07-23 2023-01-25 Commissariat à l'énergie atomique et aux énergies alternatives Procede de fabrication d'un substrat semi-conducteur sur isolant de type soi ou sigeoi par besoi et structure pour fabriquer un tel substrat

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7781850B2 (en) * 2002-09-20 2010-08-24 Qualcomm Mems Technologies, Inc. Controlling electromechanical behavior of structures within a microelectromechanical systems device
US7176041B2 (en) * 2003-07-01 2007-02-13 Samsung Electronics Co., Ltd. PAA-based etchant, methods of using same, and resultant structures
DE102010042570B4 (de) 2010-10-18 2012-07-26 Jörg Funke Falt- und teilweise zerlegbares Fahrrad

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
EP0828296A2 (fr) * 1996-09-03 1998-03-11 International Business Machines Corporation Supraconductivité à haute température dans une jonction contrainte Si/SiGe
WO1999053539A1 (fr) * 1998-04-10 1999-10-21 Massachusetts Institute Of Technology Systeme de couche d'arret d'attaque chimique au silicium et au germanium
US6059895A (en) * 1997-04-30 2000-05-09 International Business Machines Corporation Strained Si/SiGe layers on insulator

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
EP0828296A2 (fr) * 1996-09-03 1998-03-11 International Business Machines Corporation Supraconductivité à haute température dans une jonction contrainte Si/SiGe
US6059895A (en) * 1997-04-30 2000-05-09 International Business Machines Corporation Strained Si/SiGe layers on insulator
WO1999053539A1 (fr) * 1998-04-10 1999-10-21 Massachusetts Institute Of Technology Systeme de couche d'arret d'attaque chimique au silicium et au germanium

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
CHANG G K ET AL: "SELECTIVE ETCHING OF SIGE ON SIGE/SI HETEROSTRUCTURES" JOURNAL OF THE ELECTROCHEMICAL SOCIETY, ELECTROCHEMICAL SOCIETY. MANCHESTER, NEW HAMPSHIRE, US, vol. 138, no. 1, 1991, pages 202-204, XP000177327 ISSN: 0013-4651 *
ISMAIL K: "Si/SiGe high-speed field-effect transistors" ELECTRON DEVICES MEETING, 1995., INTERNATIONAL WASHINGTON, DC, USA 10-13 DEC. 1995, NEW YORK, NY, USA,IEEE, US, 10 December 1995 (1995-12-10), pages 509-512, XP010161136 ISBN: 0-7803-2700-4 *
MASZARA W P: "SILICON-ON-INSULATOR BY WAFER BONDING: A REVIEW" JOURNAL OF THE ELECTROCHEMICAL SOCIETY, ELECTROCHEMICAL SOCIETY. MANCHESTER, NEW HAMPSHIRE, US, vol. 138, no. 1, 1991, pages 341-347, XP000177334 ISSN: 0013-4651 *

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US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
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US6916727B2 (en) 2001-06-21 2005-07-12 Massachusetts Institute Of Technology Enhancement of P-type metal-oxide-semiconductor field effect transistors
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WO2003069658A3 (fr) * 2002-02-11 2004-02-19 Ibm Couche contrainte a base de si conçue par uhv-cvd et dispositifs associes
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