AU2001268577A1 - Etch stop layer system - Google Patents

Etch stop layer system

Info

Publication number
AU2001268577A1
AU2001268577A1 AU2001268577A AU6857701A AU2001268577A1 AU 2001268577 A1 AU2001268577 A1 AU 2001268577A1 AU 2001268577 A AU2001268577 A AU 2001268577A AU 6857701 A AU6857701 A AU 6857701A AU 2001268577 A1 AU2001268577 A1 AU 2001268577A1
Authority
AU
Australia
Prior art keywords
stop layer
etch stop
layer system
etch
stop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001268577A
Inventor
Jeffrey T Borenstein
Eugene A. Fitzgerald
Gianna Taraschi
Kenneth C. Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Massachusetts Institute of Technology
Original Assignee
Massachusetts Institute of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/599,260 external-priority patent/US6689211B1/en
Application filed by Massachusetts Institute of Technology filed Critical Massachusetts Institute of Technology
Publication of AU2001268577A1 publication Critical patent/AU2001268577A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
AU2001268577A 2000-06-22 2001-06-20 Etch stop layer system Abandoned AU2001268577A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/599,260 US6689211B1 (en) 1999-04-09 2000-06-22 Etch stop layer system
US09599260 2000-06-22
PCT/US2001/019613 WO2001099169A2 (en) 2000-06-22 2001-06-20 Etch stop layer system for sige devices

Publications (1)

Publication Number Publication Date
AU2001268577A1 true AU2001268577A1 (en) 2002-01-02

Family

ID=24398918

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001268577A Abandoned AU2001268577A1 (en) 2000-06-22 2001-06-20 Etch stop layer system

Country Status (4)

Country Link
EP (1) EP1295319A2 (en)
JP (1) JP2003536273A (en)
AU (1) AU2001268577A1 (en)
WO (1) WO2001099169A2 (en)

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US6602613B1 (en) 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6750130B1 (en) 2000-01-20 2004-06-15 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6555839B2 (en) 2000-05-26 2003-04-29 Amberwave Systems Corporation Buried channel strained silicon FET using a supply layer created through ion implantation
US6573126B2 (en) 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6593641B1 (en) 2001-03-02 2003-07-15 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
EP1364411A1 (en) * 2001-03-02 2003-11-26 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed cmos electronics and high speed analog circuits
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6900103B2 (en) 2001-03-02 2005-05-31 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
WO2002082514A1 (en) * 2001-04-04 2002-10-17 Massachusetts Institute Of Technology A method for semiconductor device fabrication
US6855649B2 (en) * 2001-06-12 2005-02-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US6900094B2 (en) 2001-06-14 2005-05-31 Amberwave Systems Corporation Method of selective removal of SiGe alloys
JP2004531901A (en) 2001-06-21 2004-10-14 マサチューセッツ　インスティテュート　オブ　テクノロジー MOSFET with strained semiconductor layer
US6730551B2 (en) 2001-08-06 2004-05-04 Massachusetts Institute Of Technology Formation of planar strained layers
US6974735B2 (en) 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
US7138649B2 (en) 2001-08-09 2006-11-21 Amberwave Systems Corporation Dual-channel CMOS transistors with differentially strained channels
WO2003028106A2 (en) 2001-09-24 2003-04-03 Amberwave Systems Corporation Rf circuits including transistors having strained material layers
US6649492B2 (en) * 2002-02-11 2003-11-18 International Business Machines Corporation Strained Si based layer made by UHV-CVD, and devices therein
WO2003079415A2 (en) * 2002-03-14 2003-09-25 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
AU2003238963A1 (en) 2002-06-07 2003-12-22 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
FR2842350B1 (en) * 2002-07-09 2005-05-13 METHOD FOR TRANSFERRING A LAYER OF CONCEALED SEMICONDUCTOR MATERIAL
FR2842349B1 (en) 2002-07-09 2005-02-18 TRANSFERRING A THIN LAYER FROM A PLATE COMPRISING A BUFFER LAYER
US7018910B2 (en) 2002-07-09 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Transfer of a thin layer from a wafer comprising a buffer layer
US6953736B2 (en) 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
US7781850B2 (en) * 2002-09-20 2010-08-24 Qualcomm Mems Technologies, Inc. Controlling electromechanical behavior of structures within a microelectromechanical systems device
DE10260860B4 (en) * 2002-12-23 2008-07-10 Robert Bosch Gmbh Layer of Si1-xGex, process for their preparation and micromechanical device with it
US6808953B2 (en) * 2002-12-31 2004-10-26 Robert Bosch Gmbh Gap tuning for surface micromachined structures in an epitaxial reactor
US7176041B2 (en) * 2003-07-01 2007-02-13 Samsung Electronics Co., Ltd. PAA-based etchant, methods of using same, and resultant structures
US7495266B2 (en) 2004-06-16 2009-02-24 Massachusetts Institute Of Technology Strained silicon-on-silicon by wafer bonding and layer transfer
TWI283442B (en) 2004-09-09 2007-07-01 Sez Ag Method for selective etching
FR2892733B1 (en) * 2005-10-28 2008-02-01 Soitec Silicon On Insulator RELAXATION OF LAYERS
KR101316947B1 (en) 2005-11-01 2013-10-15 메사추세츠 인스티튜트 오브 테크놀로지 Monolithically integrated semiconductor materials and devices
US8063397B2 (en) 2006-06-28 2011-11-22 Massachusetts Institute Of Technology Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission
DE102010042570B4 (en) 2010-10-18 2012-07-26 Jörg Funke Folding and partially dismountable bicycle
US9093478B1 (en) 2014-04-11 2015-07-28 International Business Machines Corporation Integrated circuit structure with bulk silicon FinFET and methods of forming
US9842913B1 (en) 2016-05-18 2017-12-12 Globalfoundries Inc. Integrated circuit fabrication with boron etch-stop layer
FR3064398B1 (en) * 2017-03-21 2019-06-07 Soitec SEMICONDUCTOR TYPE STRUCTURE ON INSULATION, ESPECIALLY FOR A FRONT-SIDE TYPE IMAGE SENSOR, AND METHOD FOR MANUFACTURING SUCH STRUCTURE
FR3125631A1 (en) * 2021-07-23 2023-01-27 Commissariat A L'energie Atomique Et Aux Energies Alternatives METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE ON INSULATOR OF THE SOI OR SIGEOI TYPE BY REQUIREMENTS AND STRUCTURE FOR MANUFACTURING SUCH A SUBSTRATE

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
TW335558B (en) * 1996-09-03 1998-07-01 Ibm High temperature superconductivity in strained SiSiGe
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
WO1999053539A1 (en) * 1998-04-10 1999-10-21 Massachusetts Institute Of Technology Silicon-germanium etch stop layer system

Also Published As

Publication number Publication date
WO2001099169A2 (en) 2001-12-27
EP1295319A2 (en) 2003-03-26
JP2003536273A (en) 2003-12-02
WO2001099169A3 (en) 2002-04-25

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