WO2001099169A3 - Systeme de couche d'arret de gravure - Google Patents
Systeme de couche d'arret de gravure Download PDFInfo
- Publication number
- WO2001099169A3 WO2001099169A3 PCT/US2001/019613 US0119613W WO0199169A3 WO 2001099169 A3 WO2001099169 A3 WO 2001099169A3 US 0119613 W US0119613 W US 0119613W WO 0199169 A3 WO0199169 A3 WO 0199169A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- etch
- stop layer
- etch stop
- layer system
- sige
- Prior art date
Links
- 239000000463 material Substances 0.000 abstract 4
- 239000000203 mixture Substances 0.000 abstract 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 229910006990 Si1-xGex Inorganic materials 0.000 abstract 1
- 229910007020 Si1−xGex Inorganic materials 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910045601 alloy Inorganic materials 0.000 abstract 1
- 239000000956 alloy Substances 0.000 abstract 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30608—Anisotropic liquid etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Weting (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2001268577A AU2001268577A1 (en) | 2000-06-22 | 2001-06-20 | Etch stop layer system |
EP01946546A EP1295319A2 (fr) | 2000-06-22 | 2001-06-20 | Systeme de couche d'arret de gravure |
JP2002503924A JP2003536273A (ja) | 2000-06-22 | 2001-06-20 | エッチング阻止層システム |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/599,260 US6689211B1 (en) | 1999-04-09 | 2000-06-22 | Etch stop layer system |
US09/599,260 | 2000-06-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001099169A2 WO2001099169A2 (fr) | 2001-12-27 |
WO2001099169A3 true WO2001099169A3 (fr) | 2002-04-25 |
Family
ID=24398918
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/019613 WO2001099169A2 (fr) | 2000-06-22 | 2001-06-20 | Systeme de couche d'arret de gravure |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1295319A2 (fr) |
JP (1) | JP2003536273A (fr) |
AU (1) | AU2001268577A1 (fr) |
WO (1) | WO2001099169A2 (fr) |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6750130B1 (en) | 2000-01-20 | 2004-06-15 | Amberwave Systems Corporation | Heterointegration of materials using deposition and bonding |
US6602613B1 (en) | 2000-01-20 | 2003-08-05 | Amberwave Systems Corporation | Heterointegration of materials using deposition and bonding |
US6969875B2 (en) | 2000-05-26 | 2005-11-29 | Amberwave Systems Corporation | Buried channel strained silicon FET using a supply layer created through ion implantation |
JP2004507084A (ja) | 2000-08-16 | 2004-03-04 | マサチューセッツ インスティテュート オブ テクノロジー | グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス |
US6593641B1 (en) | 2001-03-02 | 2003-07-15 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6830976B2 (en) | 2001-03-02 | 2004-12-14 | Amberwave Systems Corproation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
WO2002071495A1 (fr) * | 2001-03-02 | 2002-09-12 | Amberwave Systems Corporation | Plate-forme de silicium germanium relachee pour electronique cmos tres rapide et circuits analogiques tres rapides |
US6900103B2 (en) | 2001-03-02 | 2005-05-31 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6724008B2 (en) | 2001-03-02 | 2004-04-20 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
WO2002082514A1 (fr) * | 2001-04-04 | 2002-10-17 | Massachusetts Institute Of Technology | Procede de fabrication d'un dispositif semi-conducteur |
US6855649B2 (en) * | 2001-06-12 | 2005-02-15 | International Business Machines Corporation | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
US6900094B2 (en) | 2001-06-14 | 2005-05-31 | Amberwave Systems Corporation | Method of selective removal of SiGe alloys |
US6916727B2 (en) | 2001-06-21 | 2005-07-12 | Massachusetts Institute Of Technology | Enhancement of P-type metal-oxide-semiconductor field effect transistors |
WO2003015142A2 (fr) | 2001-08-06 | 2003-02-20 | Massachusetts Institute Of Technology | Formation de couches planes soumises a des contraintes |
US7138649B2 (en) | 2001-08-09 | 2006-11-21 | Amberwave Systems Corporation | Dual-channel CMOS transistors with differentially strained channels |
US6974735B2 (en) | 2001-08-09 | 2005-12-13 | Amberwave Systems Corporation | Dual layer Semiconductor Devices |
WO2003028106A2 (fr) | 2001-09-24 | 2003-04-03 | Amberwave Systems Corporation | Circuits r.f. comprenant des transistors a couches de materiau contraintes |
US6649492B2 (en) * | 2002-02-11 | 2003-11-18 | International Business Machines Corporation | Strained Si based layer made by UHV-CVD, and devices therein |
AU2003222003A1 (en) * | 2002-03-14 | 2003-09-29 | Amberwave Systems Corporation | Methods for fabricating strained layers on semiconductor substrates |
AU2003238963A1 (en) | 2002-06-07 | 2003-12-22 | Amberwave Systems Corporation | Semiconductor devices having strained dual channel layers |
US20030227057A1 (en) | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
US6982474B2 (en) | 2002-06-25 | 2006-01-03 | Amberwave Systems Corporation | Reacted conductive gate electrodes |
FR2842350B1 (fr) * | 2002-07-09 | 2005-05-13 | Procede de transfert d'une couche de materiau semiconducteur contraint | |
US7018910B2 (en) | 2002-07-09 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Transfer of a thin layer from a wafer comprising a buffer layer |
FR2842349B1 (fr) | 2002-07-09 | 2005-02-18 | Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon | |
US6953736B2 (en) | 2002-07-09 | 2005-10-11 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Process for transferring a layer of strained semiconductor material |
US7781850B2 (en) * | 2002-09-20 | 2010-08-24 | Qualcomm Mems Technologies, Inc. | Controlling electromechanical behavior of structures within a microelectromechanical systems device |
DE10260860B4 (de) * | 2002-12-23 | 2008-07-10 | Robert Bosch Gmbh | Schicht aus Si1-xGex, Verfahren zu deren Herstellung und mikromechanisches Bauelement damit |
US6808953B2 (en) * | 2002-12-31 | 2004-10-26 | Robert Bosch Gmbh | Gap tuning for surface micromachined structures in an epitaxial reactor |
US7176041B2 (en) * | 2003-07-01 | 2007-02-13 | Samsung Electronics Co., Ltd. | PAA-based etchant, methods of using same, and resultant structures |
US7495266B2 (en) | 2004-06-16 | 2009-02-24 | Massachusetts Institute Of Technology | Strained silicon-on-silicon by wafer bonding and layer transfer |
TWI283442B (en) | 2004-09-09 | 2007-07-01 | Sez Ag | Method for selective etching |
FR2892733B1 (fr) | 2005-10-28 | 2008-02-01 | Soitec Silicon On Insulator | Relaxation de couches |
US7705370B2 (en) | 2005-11-01 | 2010-04-27 | Massachusetts Institute Of Technology | Monolithically integrated photodetectors |
US8063397B2 (en) | 2006-06-28 | 2011-11-22 | Massachusetts Institute Of Technology | Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission |
DE102010042570B4 (de) | 2010-10-18 | 2012-07-26 | Jörg Funke | Falt- und teilweise zerlegbares Fahrrad |
US9093478B1 (en) | 2014-04-11 | 2015-07-28 | International Business Machines Corporation | Integrated circuit structure with bulk silicon FinFET and methods of forming |
US9842913B1 (en) | 2016-05-18 | 2017-12-12 | Globalfoundries Inc. | Integrated circuit fabrication with boron etch-stop layer |
FR3064398B1 (fr) * | 2017-03-21 | 2019-06-07 | Soitec | Structure de type semi-conducteur sur isolant, notamment pour un capteur d'image de type face avant, et procede de fabrication d'une telle structure |
FR3125631A1 (fr) * | 2021-07-23 | 2023-01-27 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de fabrication d’un substrat semi-conducteur sur isolant de type soi ou sigeoi par besoi et structure pour fabriquer un tel substrat |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5013681A (en) * | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
EP0828296A2 (fr) * | 1996-09-03 | 1998-03-11 | International Business Machines Corporation | Supraconductivité à haute température dans une jonction contrainte Si/SiGe |
WO1999053539A1 (fr) * | 1998-04-10 | 1999-10-21 | Massachusetts Institute Of Technology | Systeme de couche d'arret d'attaque chimique au silicium et au germanium |
US6059895A (en) * | 1997-04-30 | 2000-05-09 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
-
2001
- 2001-06-20 EP EP01946546A patent/EP1295319A2/fr not_active Withdrawn
- 2001-06-20 JP JP2002503924A patent/JP2003536273A/ja not_active Withdrawn
- 2001-06-20 WO PCT/US2001/019613 patent/WO2001099169A2/fr active Application Filing
- 2001-06-20 AU AU2001268577A patent/AU2001268577A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5013681A (en) * | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
EP0828296A2 (fr) * | 1996-09-03 | 1998-03-11 | International Business Machines Corporation | Supraconductivité à haute température dans une jonction contrainte Si/SiGe |
US6059895A (en) * | 1997-04-30 | 2000-05-09 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
WO1999053539A1 (fr) * | 1998-04-10 | 1999-10-21 | Massachusetts Institute Of Technology | Systeme de couche d'arret d'attaque chimique au silicium et au germanium |
Non-Patent Citations (3)
Title |
---|
CHANG G K ET AL: "SELECTIVE ETCHING OF SIGE ON SIGE/SI HETEROSTRUCTURES", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, ELECTROCHEMICAL SOCIETY. MANCHESTER, NEW HAMPSHIRE, US, vol. 138, no. 1, 1991, pages 202 - 204, XP000177327, ISSN: 0013-4651 * |
ISMAIL K: "Si/SiGe high-speed field-effect transistors", ELECTRON DEVICES MEETING, 1995., INTERNATIONAL WASHINGTON, DC, USA 10-13 DEC. 1995, NEW YORK, NY, USA,IEEE, US, 10 December 1995 (1995-12-10), pages 509 - 512, XP010161136, ISBN: 0-7803-2700-4 * |
MASZARA W P: "SILICON-ON-INSULATOR BY WAFER BONDING: A REVIEW", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, ELECTROCHEMICAL SOCIETY. MANCHESTER, NEW HAMPSHIRE, US, vol. 138, no. 1, 1991, pages 341 - 347, XP000177334, ISSN: 0013-4651 * |
Also Published As
Publication number | Publication date |
---|---|
JP2003536273A (ja) | 2003-12-02 |
AU2001268577A1 (en) | 2002-01-02 |
EP1295319A2 (fr) | 2003-03-26 |
WO2001099169A2 (fr) | 2001-12-27 |
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