FR2969815B1 - Procédé de fabrication d'un dispositif semi-conducteur - Google Patents

Procédé de fabrication d'un dispositif semi-conducteur

Info

Publication number
FR2969815B1
FR2969815B1 FR1005133A FR1005133A FR2969815B1 FR 2969815 B1 FR2969815 B1 FR 2969815B1 FR 1005133 A FR1005133 A FR 1005133A FR 1005133 A FR1005133 A FR 1005133A FR 2969815 B1 FR2969815 B1 FR 2969815B1
Authority
FR
France
Prior art keywords
semiconductor layer
semiconductor device
dislocations
manufacturing semiconductor
relates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1005133A
Other languages
English (en)
Other versions
FR2969815A1 (fr
Inventor
Oleg Kononchuk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR1005133A priority Critical patent/FR2969815B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to DE112011106083.1T priority patent/DE112011106083T8/de
Priority to CN201180075548.7A priority patent/CN104025268A/zh
Priority to KR1020187022619A priority patent/KR20180091955A/ko
Priority to CN201910541192.XA priority patent/CN110189996A/zh
Priority to US14/362,305 priority patent/US20140370695A1/en
Priority to PCT/EP2011/006350 priority patent/WO2012089315A1/fr
Priority to SG11201403121YA priority patent/SG11201403121YA/en
Priority to JP2014546325A priority patent/JP6064232B2/ja
Priority to KR1020147015100A priority patent/KR20140098769A/ko
Priority to TW100148387A priority patent/TWI584380B/zh
Publication of FR2969815A1 publication Critical patent/FR2969815A1/fr
Application granted granted Critical
Publication of FR2969815B1 publication Critical patent/FR2969815B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66143—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

La présente invention se rapporte à un procédé de fabrication d'une structure semiconductrice comprenant une couche semiconductrice (5) et une couche métallique (7) afin d'améliorer les propriétés de tension de claquage du composant et réduire les courants de fuite, le procédé comprend les étapes consistant à : a) fournir une couche semiconductrice comprenant des défauts et/ou des dislocations, b) enlever de la matière au niveau d'un ou de plusieurs emplacements des défauts et/ou des dislocations, ce qui forme ainsi des cuvettes (13a à 13d) dans la couche semiconductrice, c) effectuer une passivation des cuvettes (13a à 13d) et c) placer la couche métallique (7) par-dessus la couche semiconductrice (5). L'invention se rapporte également à une structure semiconductrice correspondante.
FR1005133A 2010-12-27 2010-12-27 Procédé de fabrication d'un dispositif semi-conducteur Active FR2969815B1 (fr)

Priority Applications (11)

Application Number Priority Date Filing Date Title
FR1005133A FR2969815B1 (fr) 2010-12-27 2010-12-27 Procédé de fabrication d'un dispositif semi-conducteur
JP2014546325A JP6064232B2 (ja) 2010-12-27 2011-12-15 半導体デバイスを製造するための方法
KR1020187022619A KR20180091955A (ko) 2010-12-27 2011-12-15 반도체 소자의 제조 방법
CN201910541192.XA CN110189996A (zh) 2010-12-27 2011-12-15 半导体结构及其制造方法、使用该半导体结构的器件
US14/362,305 US20140370695A1 (en) 2010-12-27 2011-12-15 Method for fabricating a semiconductor device
PCT/EP2011/006350 WO2012089315A1 (fr) 2010-12-27 2011-12-15 Procédé de fabrication d'un dispositif à semi-conducteur
DE112011106083.1T DE112011106083T8 (de) 2010-12-27 2011-12-15 Verfahren zum Herstellen eines Halbleiterbauelementes
CN201180075548.7A CN104025268A (zh) 2010-12-27 2011-12-15 制造半导体器件的方法
KR1020147015100A KR20140098769A (ko) 2010-12-27 2011-12-15 반도체 소자의 제조 방법
SG11201403121YA SG11201403121YA (en) 2010-12-27 2011-12-15 A method for fabricating a semiconductor device
TW100148387A TWI584380B (zh) 2010-12-27 2011-12-23 半導體裝置的製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1005133A FR2969815B1 (fr) 2010-12-27 2010-12-27 Procédé de fabrication d'un dispositif semi-conducteur

Publications (2)

Publication Number Publication Date
FR2969815A1 FR2969815A1 (fr) 2012-06-29
FR2969815B1 true FR2969815B1 (fr) 2013-11-22

Family

ID=45463528

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1005133A Active FR2969815B1 (fr) 2010-12-27 2010-12-27 Procédé de fabrication d'un dispositif semi-conducteur

Country Status (9)

Country Link
US (1) US20140370695A1 (fr)
JP (1) JP6064232B2 (fr)
KR (2) KR20140098769A (fr)
CN (2) CN104025268A (fr)
DE (1) DE112011106083T8 (fr)
FR (1) FR2969815B1 (fr)
SG (1) SG11201403121YA (fr)
TW (1) TWI584380B (fr)
WO (1) WO2012089315A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014049616A (ja) * 2012-08-31 2014-03-17 Sony Corp ダイオードおよびダイオードの製造方法
CN103280502B (zh) 2013-05-23 2016-12-28 安徽三安光电有限公司 发光器件及其制作方法
US20170275779A1 (en) * 2015-10-07 2017-09-28 Sumitomo Electric Industries, Ltd. Silicon carbide epitaxial substrate and method for manufacturing silicon carbide semiconductor device
FR3060837B1 (fr) * 2016-12-15 2019-05-10 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de fabrication d'un dispositif comprenant une couche de materiau iii-n avec des defauts de surface
CN113445131A (zh) * 2021-06-28 2021-09-28 中国科学院上海光学精密机械研究所 抑制来自氮化镓籽晶缺陷的方法及氮化镓单晶和应用

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3806771A (en) * 1969-05-05 1974-04-23 Gen Electric Smoothly beveled semiconductor device with thick glass passivant
US4062038A (en) * 1976-01-28 1977-12-06 International Business Machines Corporation Radiation responsive device
US4320168A (en) * 1976-12-16 1982-03-16 Solarex Corporation Method of forming semicrystalline silicon article and product produced thereby
NL191525C (nl) * 1977-02-02 1995-08-21 Shinkokai Zaidan Hojin Handot Halfgeleiderinrichting omvattende een stroomkanaalgebied van een eerste geleidingstype dat wordt omsloten door een van een stuurelektrode voorzien stuurgebied van het tweede geleidingstype.
US4197141A (en) * 1978-01-31 1980-04-08 Massachusetts Institute Of Technology Method for passivating imperfections in semiconductor materials
US4431858A (en) * 1982-05-12 1984-02-14 University Of Florida Method of making quasi-grain boundary-free polycrystalline solar cell structure and solar cell structure obtained thereby
FR2631488B1 (fr) * 1988-05-10 1990-07-27 Thomson Hybrides Microondes Circuit integre hyperfrequence de type planar, comportant au moins un composant mesa, et son procede de fabrication
US20040144999A1 (en) * 1995-06-07 2004-07-29 Li Chou H. Integrated circuit device
US5889295A (en) * 1996-02-26 1999-03-30 Kabushiki Kaisha Toshiba Semiconductor device
JPH10120496A (ja) * 1996-10-17 1998-05-12 Denso Corp 炭化珪素基板の欠陥除去方法
JP3594826B2 (ja) * 1999-02-09 2004-12-02 パイオニア株式会社 窒化物半導体発光素子及びその製造方法
US6447604B1 (en) * 2000-03-13 2002-09-10 Advanced Technology Materials, Inc. Method for achieving improved epitaxy quality (surface texture and defect density) on free-standing (aluminum, indium, gallium) nitride ((al,in,ga)n) substrates for opto-electronic and electronic devices
JP4556300B2 (ja) * 2000-07-18 2010-10-06 ソニー株式会社 結晶成長方法
JP3988018B2 (ja) * 2001-01-18 2007-10-10 ソニー株式会社 結晶膜、結晶基板および半導体装置
US6784074B2 (en) * 2001-05-09 2004-08-31 Nsc-Nanosemiconductor Gmbh Defect-free semiconductor templates for epitaxial growth and method of making same
JP3690326B2 (ja) * 2001-10-12 2005-08-31 豊田合成株式会社 Ｉｉｉ族窒化物系化合物半導体の製造方法
EP1306890A2 (fr) * 2001-10-25 2003-05-02 Matsushita Electric Industrial Co., Ltd. Substrat et dispositif semiconducteur comprenant SiC et procédé de la fabrication
JP3801091B2 (ja) * 2002-05-09 2006-07-26 富士電機デバイステクノロジー株式会社 炭化珪素半導体装置およびその製造方法
TW587346B (en) * 2003-03-28 2004-05-11 United Epitaxy Co Ltd Optoelectronic device made by semiconductor compound
KR100624449B1 (ko) * 2004-12-08 2006-09-18 삼성전기주식회사 요철 구조를 포함하는 발광 소자 및 그 제조 방법
US20070145386A1 (en) * 2004-12-08 2007-06-28 Samsung Electro-Mechanics Co., Ltd. Semiconductor light emitting device and method of manufacturing the same
KR100657941B1 (ko) * 2004-12-31 2006-12-14 삼성전기주식회사 요철 구조를 포함하는 발광 소자 및 그 제조 방법
JP4432827B2 (ja) * 2005-04-26 2010-03-17 住友電気工業株式会社 Ｉｉｉ族窒化物半導体素子およびエピタキシャル基板
JP2007243080A (ja) * 2006-03-13 2007-09-20 Fuji Electric Holdings Co Ltd 半導体装置およびその製造方法
US7560364B2 (en) * 2006-05-05 2009-07-14 Applied Materials, Inc. Dislocation-specific lateral epitaxial overgrowth to reduce dislocation density of nitride films
US7459380B2 (en) * 2006-05-05 2008-12-02 Applied Materials, Inc. Dislocation-specific dielectric mask deposition and lateral epitaxial overgrowth to reduce dislocation density of nitride films
US8236593B2 (en) * 2007-05-14 2012-08-07 Soitec Methods for improving the quality of epitaxially-grown semiconductor materials
GB0806556D0 (en) * 2008-04-11 2008-05-14 Isis Innovation Silicon wafers
TWI401729B (zh) * 2008-10-16 2013-07-11 Advanced Optoelectronic Tech 阻斷半導體差排缺陷之方法
CN102301447B (zh) * 2008-11-14 2014-05-14 S.O.I.Tec绝缘体上硅技术公司 用于提高包括半导体材料的结构的质量的方法
KR20100093872A (ko) * 2009-02-17 2010-08-26 삼성엘이디 주식회사 질화물 반도체 발광소자 및 그 제조방법
US8178427B2 (en) * 2009-03-31 2012-05-15 Commissariat A. L'energie Atomique Epitaxial methods for reducing surface dislocation density in semiconductor materials
US8232568B2 (en) * 2009-08-21 2012-07-31 Bridgelux, Inc. High brightness LED utilizing a roughened active layer and conformal cladding
JP2011134815A (ja) * 2009-12-23 2011-07-07 Denso Corp ショットキーダイオードと製造方法と製造装置
CN101771088A (zh) * 2010-01-21 2010-07-07 复旦大学 Pn结和肖特基结混合式二极管及其制备方法
US20110221039A1 (en) * 2010-03-12 2011-09-15 Sinmat, Inc. Defect capping for reduced defect density epitaxial articles
US9142631B2 (en) * 2010-03-17 2015-09-22 Cree, Inc. Multilayer diffusion barriers for wide bandgap Schottky barrier devices
US8450190B2 (en) * 2010-03-23 2013-05-28 Academia Sinica Fabrication of GaN substrate by defect selective passivation
KR101051561B1 (ko) * 2010-04-14 2011-07-22 삼성전기주식회사 질화물계 반도체 소자 및 그 제조 방법
US9287452B2 (en) * 2010-08-09 2016-03-15 Micron Technology, Inc. Solid state lighting devices with dielectric insulation and methods of manufacturing
FR2969813B1 (fr) * 2010-12-27 2013-11-08 Soitec Silicon On Insulator Procédé de fabrication d'un dispositif semi-conducteur
US8409892B2 (en) * 2011-04-14 2013-04-02 Opto Tech Corporation Method of selective photo-enhanced wet oxidation for nitride layer regrowth on substrates
KR101881064B1 (ko) * 2012-03-05 2018-07-24 삼성전자주식회사 질화물 반도체 발광소자 및 그 제조방법
TWI436424B (zh) * 2012-04-03 2014-05-01 Univ Nat Taiwan 半導體元件及其製造方法

Also Published As

Publication number Publication date
JP2015500572A (ja) 2015-01-05
FR2969815A1 (fr) 2012-06-29
KR20180091955A (ko) 2018-08-16
SG11201403121YA (en) 2014-10-30
TWI584380B (zh) 2017-05-21
DE112011106083T8 (de) 2015-03-26
CN110189996A (zh) 2019-08-30
CN104025268A (zh) 2014-09-03
US20140370695A1 (en) 2014-12-18
KR20140098769A (ko) 2014-08-08
JP6064232B2 (ja) 2017-01-25
WO2012089315A1 (fr) 2012-07-05
TW201234491A (en) 2012-08-16
DE112011106083T5 (de) 2014-12-31

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