SG11201903019XA - Method for dissolving a buried oxide in a silicon-on-insulator wafer - Google Patents

Method for dissolving a buried oxide in a silicon-on-insulator wafer

Info

Publication number
SG11201903019XA
SG11201903019XA SG11201903019XA SG11201903019XA SG11201903019XA SG 11201903019X A SG11201903019X A SG 11201903019XA SG 11201903019X A SG11201903019X A SG 11201903019XA SG 11201903019X A SG11201903019X A SG 11201903019XA SG 11201903019X A SG11201903019X A SG 11201903019XA
Authority
SG
Singapore
Prior art keywords
silicon
international
buried oxide
insulator wafer
dissolving
Prior art date
Application number
SG11201903019XA
Inventor
Frédéric Allibert
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11201903019XA publication Critical patent/SG11201903019XA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Title: METHOD FOR DISSOLVING A BURIED OXIDE IN A SILICON-ON-INSULATOR WAFER 100 104 101 hS hBOX 103 FIG. 1 102 (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 19 April 2018 (19.04.2018) WIP0 1 PCT omit VIII °nolo III 1101 VIII 0101101010 Imo oimIE (10) International Publication Number WO 2018/069067 Al (51) International Patent Classification: H01L 21/3105 (2006.01) HO1L 21/762 (2006.01) (21) International Application Number: PCT/EP2017/074823 (22) International Filing Date: 29 September 2017 (29.09.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 1659917 13 October 2016 (13.10.2016) FR (71) Applicant: SOITEC [FR/FR]; Parc Technologique des Fontaines, Chemin des Franques, 38190 Bernin (FR). (72) Inventor: ALLIBERT, Frederic; 30 Rue Gay Lussac, 38100 Grenoble (FR). (74) Agent: GRUNECKER PATENT- UND RECHTSAN- WALTE PARTG MBB; Leopoldstrasse 4, 80802 Munich (DE). = (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3)) 1-1 N O cc O C (57) : The present invention relates to a method for dissolving a buried oxide in a silicon-on-insulator wafer, comprising providing a silicon-on-insulator wafer (100, 300, 400, 500) having a silicon layer (101, 301, 401, 501) attached to a carrier substrate (103, 303, 403, 503) via a buried oxide layer (102, 302, 402, 502), and annealing said silicon-on-insulation wafer (100, 300, 400, 500) to at least partially dissolve the buried oxide layer (102, 302, 402, 502). The inventive method further comprises a step of providing an oxygen scavenging layer (104, 304, 404, 504) on or over the silicon layer (101, 301, 401, 501) before the annealing step.
SG11201903019XA 2016-10-13 2017-09-29 Method for dissolving a buried oxide in a silicon-on-insulator wafer SG11201903019XA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1659917A FR3057705B1 (en) 2016-10-13 2016-10-13 PROCESS FOR DISSOLVING A BLEED OXIDE IN A SILICON INSULATED WAFER
PCT/EP2017/074823 WO2018069067A1 (en) 2016-10-13 2017-09-29 Method for dissolving a buried oxide in a silicon-on-insulator wafer

Publications (1)

Publication Number Publication Date
SG11201903019XA true SG11201903019XA (en) 2019-05-30

Family

ID=57583305

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201903019XA SG11201903019XA (en) 2016-10-13 2017-09-29 Method for dissolving a buried oxide in a silicon-on-insulator wafer

Country Status (9)

Country Link
US (1) US10847370B2 (en)
JP (1) JP6801154B2 (en)
KR (1) KR102217707B1 (en)
CN (1) CN109844911B (en)
DE (1) DE112017005180T5 (en)
FR (1) FR3057705B1 (en)
SG (1) SG11201903019XA (en)
TW (1) TWI641040B (en)
WO (1) WO2018069067A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11069560B2 (en) * 2016-11-01 2021-07-20 Shin-Etsu Chemical Co., Ltd. Method of transferring device layer to transfer substrate and highly thermal conductive substrate

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003078116A (en) * 2001-08-31 2003-03-14 Canon Inc Method of manufacturing semiconductor member and semiconductor device
US6784072B2 (en) * 2002-07-22 2004-08-31 International Business Machines Corporation Control of buried oxide in SIMOX
US6664598B1 (en) * 2002-09-05 2003-12-16 International Business Machines Corporation Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control
US20050170570A1 (en) * 2004-01-30 2005-08-04 International Business Machines Corporation High electrical quality buried oxide in simox
US8138061B2 (en) * 2005-01-07 2012-03-20 International Business Machines Corporation Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide
JP5380838B2 (en) * 2005-06-22 2014-01-08 日本電気株式会社 Manufacturing method of semiconductor device
JP2007180416A (en) * 2005-12-28 2007-07-12 Siltronic Ag Method of manufacturing soi wafer
FR2936356B1 (en) * 2008-09-23 2010-10-22 Soitec Silicon On Insulator PROCESS FOR LOCALLY DISSOLVING THE OXIDE LAYER IN A SEMICONDUCTOR TYPE STRUCTURE ON INSULATION
FR2937794A1 (en) * 2008-10-28 2010-04-30 Soitec Silicon On Insulator Semiconductor-on-insulator type structure i.e. silicon-on-insulator structure, treating method for fabricating e.g. memory component of microprocessor, involves applying heat treatment in neutral/controlled reduction atmosphere
FR2938118B1 (en) * 2008-10-30 2011-04-22 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A STACK OF THIN SEMICONDUCTOR LAYERS
FR2941324B1 (en) * 2009-01-22 2011-04-29 Soitec Silicon On Insulator PROCESS FOR DISSOLVING THE OXIDE LAYER IN THE CROWN OF A SEMICONDUCTOR TYPE STRUCTURE ON AN INSULATION
US20100244206A1 (en) 2009-03-31 2010-09-30 International Business Machines Corporation Method and structure for threshold voltage control and drive current improvement for high-k metal gate transistors
EP2381470B1 (en) * 2010-04-22 2012-08-22 Soitec Semiconductor device comprising a field-effect transistor in a silicon-on-insulator structure
US8796116B2 (en) * 2011-01-31 2014-08-05 Sunedison Semiconductor Limited Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods
JP2012204501A (en) * 2011-03-24 2012-10-22 Sony Corp Semiconductor device, electronic device, and semiconductor device manufacturing method
FR2980916B1 (en) * 2011-10-03 2014-03-28 Soitec Silicon On Insulator PROCESS FOR PRODUCING A SILICON TYPE STRUCTURE ON INSULATION
US8637381B2 (en) * 2011-10-17 2014-01-28 International Business Machines Corporation High-k dielectric and silicon nitride box region
JP2013157586A (en) * 2012-01-27 2013-08-15 Mtec:Kk Compound semiconductor
US8633118B2 (en) * 2012-02-01 2014-01-21 Tokyo Electron Limited Method of forming thin metal and semi-metal layers by thermal remote oxygen scavenging
FR3003684B1 (en) * 2013-03-25 2015-03-27 Soitec Silicon On Insulator PROCESS FOR DISSOLVING A SILICON DIOXIDE LAYER
KR102336517B1 (en) 2015-09-24 2021-12-07 에스케이텔레콤 주식회사 Method and apparatus for inputting symbols

Also Published As

Publication number Publication date
CN109844911A (en) 2019-06-04
FR3057705A1 (en) 2018-04-20
KR20190047083A (en) 2019-05-07
FR3057705B1 (en) 2019-04-12
US20190259617A1 (en) 2019-08-22
TW201814785A (en) 2018-04-16
US10847370B2 (en) 2020-11-24
JP6801154B2 (en) 2020-12-16
TWI641040B (en) 2018-11-11
KR102217707B1 (en) 2021-02-19
JP2019535144A (en) 2019-12-05
DE112017005180T5 (en) 2019-07-04
WO2018069067A1 (en) 2018-04-19
CN109844911B (en) 2023-03-24

Similar Documents

Publication Publication Date Title
SG11201806798XA (en) Systems and methods for allowing a user to access blocked media
SG11201909949XA (en) Targeted immunotolerance
SG11201809064QA (en) Chimeric neurotoxins
SG11201807252QA (en) Anti-lag-3 antibodies
SG11201807705RA (en) Directional lock for interface headgear arrangement
SG11201809857TA (en) Anti-CTLA-4 Antibodies
SG11201807741SA (en) Conductive structures, systems and devices including conductive structures and related methods
SG11201811465WA (en) Semiconductor package and method of forming the same
SG11201810443SA (en) Invasive medical devices including magnetic region and systems and methods
SG11201407424TA (en) Methods for determining information about a communication parameter and communication devices
SG11201811765TA (en) Methods and systems for providing transportation service
SG11201907532VA (en) Active boundary quilt architecture memory
SG11201408451WA (en) Use of vacuum chucks to hold a wafer or wafer sub-stack
SG11201810486VA (en) High resistivity single crystal silicon ingot and wafer having improved mechanical strength
SG11201908075UA (en) A microneedle device
SG11201811269RA (en) Method of processing wafer having protrusions on the back side
CA3102046C (en) Sliding device for a vehicle seat provided with an improved locking arrangement
SG11201908275XA (en) Peptides and methods for the treatment of diabetes
SG11201909003YA (en) Integrated vascular access device and anchor pad
SG11201809473QA (en) Humanized anti-basigin antibodies and the use thereof
SG11201900123TA (en) Compositions and methods for treating frontotemporal dementia
SG11201903602RA (en) Use of beta-catenin as a biomarker for treating cancers using anti-dkk-1 antibody
SG11201803972XA (en) Multilayer construction including barrier layer and sealing layer
SG11201809551TA (en) Selection of bacterial strains useful in allergy treatment
SG11201811339SA (en) Sensors having integrated protection circuitry