JP2013157586A

JP2013157586A - Compound semiconductor

Info

Publication number: JP2013157586A
Application number: JP2012029935A
Authority: JP
Inventors: Mitsuharu Kato; 光治加藤; Tomoatsu Makino; 友厚牧野
Original assignee: MTEC KK
Current assignee: MTEC KK
Priority date: 2012-01-27
Filing date: 2012-01-27
Publication date: 2013-08-15

Abstract

PROBLEM TO BE SOLVED: To reduce costs of an element substrate such as SiC for a high voltage drive element.SOLUTION: A structure for forming a single crystal SiC substrate on an inexpensive poly-SiC substrate, is realized. An ultrathin silicon 21 is formed on the poly-SiC substrate 20, a smart cut layer 5 of hydrogen is provided on the crystal SiC substrate 2 to form an ultrathin silicon oxide film 4 on its surface, the ultrathin silicon surface 21 and the silicon oxide film surface 4 of each substrates are bonded each other, then it is cleaved at the smart cut surface to separate substrates, a thin crystal SiC layer 5 is formed on the poly-SiC substrate 20, a SiC film 6 is homoepitaxial-grown to a desired thickness, and the ultrathin silicon oxide film 4 disperses all that time.

Description

本発明はパワー系化合物半導体、とりわけＳｉＣ基板やＧａＮ基板を用いる半導体装置の基板構造と素子構造に関するものである。 The present invention relates to a substrate structure and an element structure of a semiconductor device using a power compound semiconductor, particularly a SiC substrate or a GaN substrate.

図１において、従来から公表されている単結晶ＳｉＣ基板に形成する縦構造のＭＯＳＦＥＴを示す。図１−ａはＳｉＣ基板１を示す。図１−ｂはその基板に形成した縦構造のＭＯＳＦＥＴの断面図を示す。表面にソース部１１、ドレイン部１２、ゲート部１３、Ｐウエル１４とを設けて、ドレイン部は縦方向に電流方向を設けドレイン電極１９から電流をとる公知の構造である。ＮチャンネルＭＯＳＦＥＴの事例ではＳｉＣ基板は全体がＮ⁻層、ソース部１１とドレイン部１２はＮ^＋層、チャンネル部がＰ層１５から構成される。図１−ｃはＭＯＳＦＥＴがオフの時、すなわちドレインに逆バイアス電圧が印加される場合のＰ層の空乏層の拡がりを表している。事例では、空乏層到達点１８は１０μｍの深さとなっている。ＳｉＣ基板の厚さは、作業性を考慮して４００μｍとなっている。FIG. 1 shows a vertically structured MOSFET formed on a single crystal SiC substrate that has been publicly disclosed. FIG. 1A shows the SiC substrate 1. FIG. 1B shows a cross-sectional view of a vertical MOSFET formed on the substrate. A source portion 11, a drain portion 12, a gate portion 13, and a P-well 14 are provided on the surface, and the drain portion has a known structure in which a current direction is provided in the vertical direction and current is taken from the drain electrode 19. In the case of the N channel MOSFET, the entire SiC substrate is composed of an N ⁻ layer, the source portion 11 and the drain portion 12 are composed of an N ⁺ layer, and the channel portion is composed of a P layer 15. FIG. 1C shows the expansion of the depletion layer of the P layer when the MOSFET is off, that is, when a reverse bias voltage is applied to the drain. In the example, the depletion layer arrival point 18 has a depth of 10 μm. The thickness of the SiC substrate is 400 μm in consideration of workability.

この構造の素子の課題は、ＳｉＣ基板のコストが高いことである。４Ｈ構造のＳｉＣ基板においては昇華法と呼ばれる方式で基板を作るために小さな基板口径となっているのが現実で、大口径化するためには結晶欠陥を減らすために各種の工夫を要しコストはさらに高くなってしまう。また、３Ｃ構造のＳｉＣ基板においてはＳｉ基板にＳｉＣを成長させ、そのＳｉＣを基板として利用するものである。しかし、ＳｉとＳｉＣとの格子定数の違いにより結晶欠陥が多く、それを減らすために様々な工夫が必要なためコスト高になっている。このように４Ｈ構造の基板、３Ｃ構造の基板共に各種工夫により結晶欠陥が低減され、その基板にＭＯＳＦＥＴやショットキーダイオードを形成しても実用上問題ないレベルには到達してきた。しかし、結晶欠陥を減らすために製造工程は複雑になりコスト高となっている。課題はコスト低減ができる基板の作り方にある。The subject of the element of this structure is that the cost of the SiC substrate is high. In the SiC substrate of 4H structure, it is actually a small substrate diameter to make the substrate by a method called a sublimation method, and in order to increase the diameter, various devices are required to reduce crystal defects and cost. Will be even higher. In the SiC substrate having the 3C structure, SiC is grown on the Si substrate, and the SiC is used as the substrate. However, there are many crystal defects due to the difference in lattice constant between Si and SiC, and the cost is high because various devices are required to reduce them. As described above, the crystal defects are reduced by various devices in both the 4H structure substrate and the 3C structure substrate, and even if a MOSFET or a Schottky diode is formed on the substrate, the level has reached a level where there is no practical problem. However, the manufacturing process is complicated and costly in order to reduce crystal defects. The problem is how to make a substrate that can reduce costs.

図１−ｂにおいてＭＯＳＦＥＴと基板の関係をコスト低減の観点から着眼すると、ＳｉＣ基板の厚さ４００μｍに対して、ＭＯＳＦＥＴとして必要なのは表層の１０μｍ程度であることに着目することができる。When focusing on the relationship between the MOSFET and the substrate in FIG. 1B from the viewpoint of cost reduction, it can be noted that the surface layer requires about 10 μm for the thickness of the SiC substrate of 400 μm.

より具体的には、図１−ｃにおいてＭＯＳＦＥＴが逆バイアスの時に空乏層が縦方向に広がり降伏電圧印加時に到達する空乏層の深さは約１０μｍである。従って、図１−ｃの破線で示す空乏層到達点１８より深い方向のＳｉＣ層は結晶欠陥の少ないＳｉＣ層である必要はないことに着目することができる。More specifically, in FIG. 1-c, when the MOSFET is reverse-biased, the depletion layer extends in the vertical direction, and the depth of the depletion layer reached when the breakdown voltage is applied is about 10 μm. Accordingly, it can be noted that the SiC layer deeper than the depletion layer arrival point 18 shown by the broken line in FIG. 1C does not need to be a SiC layer with few crystal defects.

但し、ＳｉＣに形成するＭＯＳＦＥＴのソース、ドレイン、Ｐウエルなどの不純物拡散層の不純物を活性化するために１６００℃以上の高温度熱処理が必要であるため、この破線以下の層は、高温度に耐えうる半導体、或いは導体であることが要件である。However, a high temperature heat treatment of 1600 ° C. or higher is required to activate impurities in the impurity diffusion layer such as the source, drain, and P well of the MOSFET formed in SiC. The requirement is to be a semiconductor or conductor that can withstand.

図１の事例では縦構造のＭＯＳＦＥＴの事例を示しているが、ＳｉＣ基板に縦構造のショットキーダイオードを形成する場合においても同様である。すなわちＭＯＳＦＥＴの場合もショットキーダイオードの場合もＳｉＣ基板の表層の１０μｍ程度だけが用いられているのが実情である。The case of FIG. 1 shows an example of a vertical MOSFET, but the same applies to the case where a vertical Schottky diode is formed on a SiC substrate. That is, in the case of MOSFET and Schottky diode, only about 10 μm of the surface layer of the SiC substrate is actually used.

この様な考察に基づいたＭＯＳＦＥＴやショットキーダイオードを形成するための基板はこれまで開示されていない。また、それに必要な基板の作成方法は開示されていない。A substrate for forming a MOSFET or a Schottky diode based on such consideration has not been disclosed so far. Further, a method for producing a substrate necessary for this is not disclosed.

高電圧駆動素子の用途が拡大するにつれてそれらの素子のコストダウン、より性能の高い素子の実用化が重要な課題となってきている。ＳｉＣ基板やＧａＮ基板上に形成するＭＯＳＦＥＴやジャンクションゲートＦＥＴやショットキーダイオードはこのニーズに合ったものである。以下の事例では、ＳｉＣ基板を例に発明内容を開示するがＧａＮ基板、その他の化合物半導体基板においても同様である。As the use of high voltage driving elements expands, the cost reduction of those elements and the practical application of higher performance elements have become important issues. MOSFETs, junction gate FETs, and Schottky diodes formed on SiC substrates and GaN substrates meet this need. In the following cases, the contents of the invention will be disclosed by taking a SiC substrate as an example, but the same applies to a GaN substrate and other compound semiconductor substrates.

本発明が解決しようとする課題は、高価格になりがちの化合物半導体の基板を素子に必要な部分だけに高価な化合物半導体を用いて、それ以外の基板となるところを安価な材料で構成することにある。より具体的には、素子を形成する層には単結晶のＳｉＣ層を用いて、基板となるところは安価なポリＳｉＣ層を用いることである。そして、その２層構造の素子の作り易い手段を実用化することにある。The problem to be solved by the present invention is to use a compound semiconductor substrate, which tends to be expensive, in an expensive compound semiconductor only for the part necessary for the device, and to configure the other substrate with an inexpensive material. There is. More specifically, a single crystal SiC layer is used as a layer for forming an element, and an inexpensive poly SiC layer is used as a substrate. Then, it is to put into practical use a means that makes it easy to produce an element having the two-layer structure.

本発明の構成は、図１の考察に基づく安価なポリＳｉＣ基板上に薄い単結晶ＳｉＣ層に形成し、そこにＭＯＳＦＥＴやショットキーダイオードを形成するものである。In the configuration of the present invention, a thin single crystal SiC layer is formed on an inexpensive poly SiC substrate based on the consideration of FIG. 1, and a MOSFET and a Schottky diode are formed there.

ポリＳｉＣ基板に単結晶ＳｉＣを形成する手法としては、単結晶の種結晶基板の表層の１μｍ程度に水素を注入して、ポリＳｉＣ基板と貼り合わせた後にスマートカット技術により水素層にて劈開せしめるという近年実用化が進んでいるスマートカット手法にて行うことができる。劈開後の種結晶基板は、表面を１μｍ程度研磨して再利用することができる。これにより、当初４００μｍの基板はスマートカットと研磨で２μｍずつ減少するが、２００μｍ厚まで使用するとすれば、１００回のＳｉＣ層の移植に利用することができる。また、劈開後のポリＳｉＣ上の単結晶ＳｉＣ層は研磨して表層の欠陥を除去した後に、公知のホモエピタキシャル成長技術により必要な厚さ、例えば、１０μｍの厚さまで、単結晶ＳｉＣを成長させることができる。As a method for forming single crystal SiC on a poly SiC substrate, hydrogen is injected into the surface layer of the single crystal seed crystal substrate at about 1 μm, and after bonding to the poly SiC substrate, the silicon layer is cleaved with a smart cut technique. It can be performed by the smart cut method that has been practically used in recent years. The seed crystal substrate after cleavage can be reused by polishing the surface by about 1 μm. As a result, the initial 400 μm substrate is reduced by 2 μm by smart cutting and polishing, but if it is used up to a thickness of 200 μm, it can be used for transplanting 100 SiC layers. In addition, the single crystal SiC layer on the poly-SiC after cleavage is polished to remove surface layer defects, and then single crystal SiC is grown to a necessary thickness, for example, 10 μm by a known homoepitaxial growth technique. Can do.

このスマートカット層形成後の貼り合わせ基板の作成における課題は、ポリＳｉＣ基板とスマートカット層を形成した単結晶ＳｉＣの貼り合わせである。貼り合わせ工程に高圧、高温度を印加すれば貼り合わせは可能であるが、スマートカット面がその途中で劈開してしまい好ましくない。A problem in creating a bonded substrate after the formation of the smart cut layer is bonding of a single-crystal SiC having a poly SiC substrate and a smart cut layer formed thereon. Bonding is possible if high pressure and high temperature are applied to the bonding step, but the smart cut surface is cleaved in the middle, which is not preferable.

本発明においては、ポリＳｉＣの基板表面に極めて薄いシリコン膜を形成し、スマートカット層形成後の単結晶ＳｉＣ基板の表面には極薄いシリコン酸化膜を形成して、両方の基板のシリコン膜面とシリコン酸化膜面を貼り合わせる手法を提供するものである。このシリコン膜とシリコン酸化膜は必ずしもこの組み合わせである必要はなく、シリコン酸化膜面同士でも、シリコン膜同士の面の貼り合せ、或いは一方にシリコン酸化膜だけを設けた面での貼り合わせでも良い。シリコン基板で既に実績があるシリコン酸化膜面同士の貼り合せ、或いはシリコン酸化膜が一方に基板に存在してシリコン酸化膜を介して貼り合わせることは室温で可能であることは知られている。この知見をＳｉＣに適用するものである。このシリコン酸化膜は絶縁物であるが、シリコン酸化膜が極薄いために、その後のＳｉＣ膜のエピタキシャル成長中や不純物の高温度熱処理中に酸素が吸収されて絶縁物では無くなる、シリコンはポリＳｉＣに溶融して、絶縁物であるシリコン酸化膜層が消失するというのが本発明の要点である。In the present invention, an extremely thin silicon film is formed on the surface of the poly SiC substrate, and an extremely thin silicon oxide film is formed on the surface of the single crystal SiC substrate after the smart cut layer is formed. And a method of bonding the silicon oxide film surfaces together. The silicon film and the silicon oxide film do not necessarily need to be a combination of these, and the silicon oxide film surfaces may be bonded to each other, or the surfaces of the silicon films may be bonded to each other, or may be bonded to the surface on which only the silicon oxide film is provided. . It is known that it is possible at room temperature to bond silicon oxide film surfaces that have already been proven in silicon substrates, or to bond silicon oxide films on one substrate via a silicon oxide film. This knowledge is applied to SiC. Although this silicon oxide film is an insulator, since the silicon oxide film is extremely thin, oxygen is absorbed during the subsequent epitaxial growth of the SiC film or during high-temperature heat treatment of impurities, and the silicon oxide is no longer an insulator. The main point of the present invention is that the silicon oxide film layer which is an insulator disappears when melted.

この基板にＭＯＳＦＥＴやショットキーダイオードを公知の構造にて形成することができる。Ｎ型半導体のＳｉＣ層に形成するｐウエル層の不純物として公知のアルミをイオン注入し、ソース、ドレインのＮ^＋層の不純物としてはリンをイオン注入して、その後に、約１６００℃以上にて活性化することにより形成することができる。MOSFETs and Schottky diodes can be formed on this substrate with a known structure. Known aluminum is ion-implanted as an impurity of the p-well layer formed in the SiC layer of the N-type semiconductor, and phosphorus is ion-implanted as an impurity of the N ⁺ layer of the source and drain, and then at about 1600 ° C. It can be formed by activation.

この様に本発明が目的としている素子基板は、シリコン酸化膜を介して低温度、低印加圧力で行う基板の貼合わせ技術、実用化が始まっているスマートカット技術をＳｉＣへ転用をすることと、本発明の特徴である極薄のシリコン酸化膜を消失させる手法により可能である。In this way, the element substrate targeted by the present invention is to divert the substrate bonding technology performed at a low temperature and a low applied pressure through the silicon oxide film to the SiC and the smart cut technology which has been put into practical use. This is possible by the technique of eliminating the ultrathin silicon oxide film, which is a feature of the present invention.

高電圧駆動に適したＳｉＣ基板の実用化の期待は大きいが、これまで基板の高価格が制約となってその用途の拡大が制限されている。ポリＳｉＣの基板への採用、スマートカット層形成、極薄シリコン酸化膜を介する貼合わせ、極薄シリコン酸化膜の消失という一連を手段により種基板の再利用を可能にならしめ、ＳｉＣ基板の低コスト化を提供する構造は画期的である。Although there are great expectations for the practical use of SiC substrates suitable for high-voltage driving, the expansion of applications has been limited so far due to the high price of the substrates. The use of poly-SiC for substrate, smart cut layer formation, bonding through ultra-thin silicon oxide film, and disappearance of ultra-thin silicon oxide film make it possible to reuse the seed substrate, making the SiC substrate low The structure that provides cost savings is groundbreaking.

公知のＳｉＣ基板とＭＯＳＦＥＴ素子の構造を示す断面図 Sectional drawing which shows structure of well-known SiC substrate and MOSFET element 本発明のポリＳｉＣ基板上の単結晶ＳｉＣ膜を形成する断面図 Sectional drawing which forms the single crystal SiC film | membrane on the poly SiC substrate of this invention

図２に本発明の実施例としてポリＳｉＣ基板２０の上に極薄シリコン膜２１を形成したシリコン酸化膜面とスマートカット層３を形成し極薄シリコン酸化膜４を形成した単結晶種結晶２の極薄シリコン酸化膜面とを貼り合わせて、その後、極薄シリコン酸化膜４が消失する工程の手順を示す。図２−ａはＳｉＣ種結晶２に１μｍの深さにスマートカット層３を形成し、表面に１ｎｍ程度の極薄シリコン酸化膜４を形成した状態を示す。
スマートカット層の表層側の薄いＳｉＣ層５がスマートカットでポリＳｉＣ側へ移されるＳｉＣ層である。図２−ｂは厚さ４００μｍのポリＳｉＣ基板２０に極薄シリコン膜２１を形成した状態を示す。ポリＳｉＣ２０は単結晶である必要はないので高速成長で作成した結晶欠陥密度を問わない低コストな基板である。図２−ｃ１は、図２−ａ、図２−ｂの基板を貼り合わせた状態を示す。シリコン酸化膜面での貼り合せであるために高圧をかけることなく、室温で貼り合わせができる。図２−ｃ２はポリＳｉＣ基板２０も、種結晶ＳｉＣ基板２も結晶欠陥のために反りがある場合に適用する手法である。図においてポリＳｉＣ基板２０も種単結晶ＳｉＣ基板２も平坦化ステージ３０、３２で反りを矯正されている。平坦化ステージ３０、３２は真空引きで吸引孔３１、３３により基板を吸着して平坦度を出している。これにより平坦化された状態で室温近傍の温度で貼り合わせを行うことができる。図２−ｄはその後、１０００℃程度でスマートカット層を劈開させ、表面を研磨で結晶性を良くした状態を示す。欠陥層の除去はＣＭＰ（ケミカル・メカニカル・ポリッシング）などで研磨することにより可能である。図２−ｅはその後、スマートカットでポリＳｉＣ基板に移したＳｉＣ層５にエピタキシャル成長で１０μｍまで成長させたＳｉＣ膜６の状態を示す。ＳｉＣ層５にエピタキシャル成長する１６００℃から１７００℃においてシリコン酸化膜はその融点を越える高温下で、ポリＳｉＣ基板２０あるいは、ＳｉＣ層５に溶解する。この状態でシリコン膜と絶縁物である極薄シリコン酸化膜は消失している。2 shows a single crystal seed crystal 2 in which an ultrathin silicon film 21 is formed on a poly SiC substrate 20 and a smart cut layer 3 is formed on a poly SiC substrate 20 to form an ultrathin silicon oxide film 4. The procedure of the process in which the ultrathin silicon oxide film 4 is pasted and then the ultrathin silicon oxide film 4 disappears is shown. FIG. 2A shows a state in which a smart cut layer 3 is formed on the SiC seed crystal 2 to a depth of 1 μm and an ultrathin silicon oxide film 4 of about 1 nm is formed on the surface.
The thin SiC layer 5 on the surface side of the smart cut layer is an SiC layer transferred to the poly SiC side by smart cut. FIG. 2B shows a state in which an ultrathin silicon film 21 is formed on a poly SiC substrate 20 having a thickness of 400 μm. Since poly SiC 20 does not need to be a single crystal, it is a low-cost substrate regardless of crystal defect density formed by high-speed growth. FIG. 2-c1 shows a state where the substrates of FIGS. 2-a and 2-b are bonded together. Since bonding is performed on the silicon oxide film surface, bonding can be performed at room temperature without applying high pressure. FIG. 2C2 shows a technique applied when both the poly SiC substrate 20 and the seed crystal SiC substrate 2 are warped due to crystal defects. In the figure, both the poly SiC substrate 20 and the seed single crystal SiC substrate 2 are corrected for warping by the flattening stages 30 and 32. The flattening stages 30 and 32 suck the substrate through the suction holes 31 and 33 by evacuation to obtain flatness. Thus, bonding can be performed at a temperature near room temperature in a flattened state. FIG. 2D shows a state in which the smart cut layer is cleaved at about 1000 ° C. and the surface is polished to improve the crystallinity. The defective layer can be removed by polishing by CMP (Chemical Mechanical Polishing) or the like. FIG. 2E shows a state of the SiC film 6 grown to 10 μm by epitaxial growth on the SiC layer 5 transferred to the poly SiC substrate by smart cut. The silicon oxide film dissolves in the poly SiC substrate 20 or the SiC layer 5 at a high temperature exceeding the melting point at 1600 ° C. to 1700 ° C. at which the SiC layer 5 is epitaxially grown. In this state, the silicon film and the ultrathin silicon oxide film that is an insulator disappear.

以上の様にして形成したポリＳｉＣ基板２０の上の単結晶ＳｉＣ膜５，６に図１−ｃで示した縦型のＭＯＳＦＥＴを作成することができる。空乏層の拡がり領域１７に相当することころが単結晶５、６内に存在する。従って、ＭＯＳＦＥＴはこの領域内にて構成され、それ以外の基板領域は安価なポリＳｉＣで構成することができる。種結晶２は結晶欠陥を減らした高価な基板であるが、この様にして本来必要な厚さだけを有効に使用することにより大幅なコストダウンが可能になる。以上の事例においては、ポリＳｉＣに形成した極薄のシリコン膜面とスマートカット層を設けた単結晶ＳｉＣに形成した極薄のシリコン酸化膜面とを貼り合せた事例であるが、ポリＳｉＣに形成した極薄のシリコン酸化膜面とスマートカット層を設けた単結晶ＳｉＣに形成した極薄のシリコン膜面との貼り合せもまったく同様な効果を生み出すことができる。The vertical MOSFET shown in FIG. 1-c can be formed on the single crystal SiC films 5 and 6 on the poly SiC substrate 20 formed as described above. A portion corresponding to the expansion region 17 of the depletion layer exists in the single crystals 5 and 6. Therefore, the MOSFET is formed in this region, and the other substrate region can be formed of inexpensive poly SiC. Although the seed crystal 2 is an expensive substrate with reduced crystal defects, the cost can be greatly reduced by effectively using only the originally required thickness in this way. In the above examples, the ultrathin silicon film surface formed on poly SiC and the ultrathin silicon oxide film surface formed on single crystal SiC provided with a smart cut layer are bonded together. Bonding the formed ultrathin silicon oxide film surface with the ultrathin silicon film surface formed on the single crystal SiC provided with the smart cut layer can produce the same effect.

以上の図の事例では極薄のシリコンと極薄のシリコン酸化膜の界面を介してポリＳｉＣ基板と単結晶積層ＳｉＣ膜の貼り合せの事例を説明したが、極薄のシリコン酸化膜同士の貼り合せ、極薄のシリコン同士の貼り合せでも、また一方の面をシリコン酸化膜とするだけでも貼り合せは可能であり、効果は同様である。また、ポリＳｉＣ基板とスマートカットを形成した単結晶ＳｉＣ基板との間に介在して貼り合わせを容易にするものは必ずしも半導体或いはその酸化物である必要はなく、面同士が貼り合せし易い白金の様な金属でも良い。また、本事例では単結晶化合物半導体としてＳｉＣを事例に説明したがＧａＮなど他の化合物半導体においても同様である。また基板としてはＳｉＣの他に化合物半導体に近い材料の使用も可能である。In the case of the above figure, the example of bonding the poly SiC substrate and the single crystal laminated SiC film through the interface between ultrathin silicon and ultrathin silicon oxide film has been explained. In addition, bonding can be performed by bonding ultra-thin silicon to each other or only by using one surface as a silicon oxide film, and the effect is the same. In addition, it is not always necessary to use a semiconductor or its oxide to interpose between a poly SiC substrate and a single crystal SiC substrate on which a smart cut is formed. A metal like In this example, SiC is described as an example of a single crystal compound semiconductor, but the same applies to other compound semiconductors such as GaN. In addition to SiC, a material close to a compound semiconductor can be used as the substrate.

Industrial applicability

ＳｉＣ基板やＧａＮ基板などを用いた高電圧駆動素子は、車においてはハイブリッド車普及、電気自動車の普及に伴ってますます重要度が増してくる。また、家庭においてはスマートグリッド化の普及に伴って家電製品の電動化やエネルギー管理のために高電圧素子の役割が重要になってくる。本発明によりポリＳｉＣ基板上に単結晶ＳｉＣ膜を形成し、安価な基板をできる基板構造を実用化することができ大きな効果を創出し、当該分野の素子の普及に大きく貢献するものとなる。ＧａＮなどの他の化合物半導体においても同様な期待がある。 High-voltage drive elements using SiC substrates, GaN substrates, and the like are becoming increasingly important with the spread of hybrid vehicles and electric vehicles. In addition, with the spread of smart grids in homes, the role of high voltage elements becomes important for the electrification and energy management of home appliances. According to the present invention, a single crystal SiC film can be formed on a poly SiC substrate, and a substrate structure capable of forming an inexpensive substrate can be put into practical use, creating a great effect and greatly contributing to the spread of devices in this field. There are similar expectations for other compound semiconductors such as GaN.

１・・・ＳｉＣ基板（Ｎ⁻層）２・・・ＳｉＣ種結晶基板（Ｎ⁻層）
３・・・スマートカット層４・・・極薄シリコン酸化膜
５・・・スマートカットで移されるＳｉＣ層６・・・１０μｍに成長させたＳｉＣ膜
１１・・・ソース（Ｎ^＋層）１２・・・ドレイン（Ｎ^＋層）１３・・・ゲート電極
１４・・・ゲート酸化膜１５・・・Ｐウエル１６・・・電流方向
１７・・・空乏層の拡がり１８・・・空乏層到達点１９・・・ドレイン電極
２０・・・ポリＳｉＣ基板（Ｎ^＋層）２１・・・極薄シリコン膜
３０・・・平坦化ステージ３１・・・吸引孔
３２・・・平坦化ステージ３３・・・吸引孔1 ... SiC substrate (N ^- layer) 2 ... SiC seed crystal substrate (N ^- layer)
3 ... Smart cut layer 4 ... Ultrathin silicon oxide film 5 ... SiC layer transferred by smart cut 6 ... SiC film grown to 10 μm 11 ... Source (N ⁺ layer) 12. ..Drain (N ⁺ layer) 13 ... Gate electrode 14 ... Gate oxide film 15 ... P well 16 ... Current direction 17 ... Expansion of depletion layer 18 ... Depletion layer arrival point 19 ... Drain electrode 20 ... Poly SiC substrate (N ⁺ layer) 21 ... Ultra-thin silicon film 30 ... Planarization stage 31 ... Suction hole 32 ... Planarization stage 33 ... Suction Hole

Claims

A compound semiconductor substrate having a structure in which a single crystal compound semiconductor layer is formed on a poly compound semiconductor substrate, and a semiconductor device using the substrate.

A single-crystal compound semiconductor provided with a smart cut layer for the purpose of smart cut by hydrogen ions or the like is bonded to the surface of the poly compound semiconductor substrate, and then both substrates are separated by the smart cut layer. A compound semiconductor substrate characterized by a structure in which a crystalline compound thin film layer is formed and a single crystal compound semiconductor is grown to a required thickness as required, and a semiconductor device using the substrate.

A thin layer of a conductor such as platinum on a single crystal compound semiconductor in which a thin layer of a conductor such as platinum is formed on a poly compound semiconductor substrate and a smart cut layer for the purpose of smart cut by hydrogen ions is provided on the surface. Then, both substrates are separated with a smart cut layer, a single crystal compound thin film layer is formed on the poly compound semiconductor, and a single crystal compound semiconductor is grown to the required thickness as required. And a semiconductor device using the substrate.

Insulating ultra-thin silicon oxide film, etc. on a single crystal compound semiconductor with a smart-cut layer for the purpose of smart-cutting by hydrogen ions etc. on the surface and the surface where a semiconductor film such as ultra-thin silicon film is formed on a poly compound semiconductor substrate A single-cut surface with a smart cut layer for the purpose of smart cut by hydrogen ions or the like is provided on the surface and surface on which an insulator such as an ultrathin silicon oxide film is formed on a poly compound semiconductor substrate. Bond the crystalline compound semiconductor to the surface on which a semiconductor such as an ultra-thin silicon film is formed, then separate both substrates with a smart cut layer, form a single crystal compound thin film layer on the poly compound semiconductor, and if necessary A single crystal compound semiconductor is grown to a required thickness, and the insulating film such as the ultrathin silicon oxide film is formed during the growth and during the subsequent high temperature treatment Compound semiconductor substrate, wherein the eliminated structures Te semiconductor device using the substrate.

Each of the ultrathin film surfaces formed on the polycompound semiconductor substrate and the single crystal compound semiconductor provided with a smart cut layer for the purpose of smart cut by hydrogen ions on the surface are bonded together. The film is a semiconductor such as a silicon film, or an insulating film of a silicon oxide film. After bonding, both substrates are separated by a smart cut layer, and a single crystal compound thin film layer is formed on a poly compound semiconductor. A compound semiconductor substrate having a structure in which a single crystal compound semiconductor is grown to a necessary thickness and the semiconductor such as ultrathin silicon disappears during the growth and during the subsequent high-temperature treatment, and a semiconductor device using the substrate.

6. The compound according to claim 3, 4 or 5, wherein the thin metal layer, the ultrathin silicon oxide film, or the ultrathin silicon is formed on one of a poly compound semiconductor and a single crystal compound semiconductor and formed by a similar method. Semiconductor substrates and semiconductor devices using these semiconductor substrates.

Bonding the surface on which the ultra-thin silicon film is formed on the poly-SiC substrate and the surface on which the ultra-thin silicon oxide film is formed on the single-crystal SiC substrate provided with a smart cut layer for the purpose of smart cut with hydrogen ions etc. Alternatively, a surface on which an ultrathin silicon oxide film is formed on a poly SiC substrate and a surface on which an ultrathin silicon film is formed on a single crystal SiC substrate provided with a smartcut layer for the purpose of smartcutting with hydrogen ions or the like on the surface. Bonding or a surface on which an ultrathin silicon film is formed on a poly SiC substrate and a surface on which an ultrathin silicon film is formed on a single crystal SiC substrate provided with a smartcut layer for the purpose of smartcutting with hydrogen ions or the like on the surface Aiming at smart cut by hydrogen ion etc. on the surface and surface where ultra-thin silicon oxide film is formed on the poly SiC substrate The single crystal SiC substrate provided with the smart cut layer was bonded to the surface on which the ultrathin silicon oxide film was formed, and then both substrates were separated by the smart cut layer, and a single crystal SiC thin film layer was formed on the poly SiC. Furthermore, a SiC substrate characterized by a structure in which single crystal SiC is grown to a required thickness as required, and the ultrathin silicon oxide film disappears during and after the high temperature treatment, and this substrate was used. Semiconductor device.

In claim 7, the ultra-thin silicon oxide film or ultra-thin silicon is formed on either a poly SiC substrate or a single crystal SiC substrate, the two substrates are bonded together, and then both the substrates are separated by a smart cut layer, A single crystal SiC thin film layer is formed on poly SiC, and further, single crystal SiC is grown to a required thickness as required. SiC substrate characterized by disappearing structure and semiconductor device using this substrate.