JP2013106027A - Compound semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a novel structure element which solves an important problem in simplification of a SiC substrate or a GaN substrate for a high-voltage drive element, by forming a single crystal SiC film on a silicon oxide film on a Si substrate to form an insulator separation structure by trenches thereby to avoid an influence of crystal defects though a large number of crystal defects exist in the insulator separation structure.SOLUTION: A semiconductor device includes an element structure in which an electric field applied to a plane at a PN junction surface which composes a semiconductor element such as MOSFET formed on a SiC film and which is parallel with a substrate surface, is limited by a silicon oxide film in which a SiC film is formed or a Si layer serving as a substrate. In addition, by setting substrate potential at potential in a reverse direction to a drain voltage, the electric filed is further limited to become a crystal defect breakdown voltage or less of crystal defects occurring in the SiC film in a direction perpendicular to the substrate.

Description

  The present invention relates to a substrate structure and an element structure of a semiconductor device using a power compound semiconductor, particularly a SiC substrate or a GaN substrate.

FIG. 1 shows a conventionally disclosed method for forming a single crystal SiC substrate. After the SiC film 2 is grown on the Si substrate 1 as shown in FIG. 1-a, the SiC film 3 is further grown on the SiC film 2 from which the Si substrate 1 has been removed as shown in FIG. It is a method to obtain a proper thickness. A MOSFET comprising a source 11, a drain 12, a gate film 13, a gate electrode 14 and the like is formed thereon as shown in FIG. However, in such a substrate forming method, it takes time to form a thick SiC thin film with a slow growth rate.

Further, as shown in FIG. 2-a, there is a structure in which an element is formed as shown in FIG. 2-b in a state where the SiC film 3 is formed on the Si substrate 5, but both the SiC layer 3 and the Si layer 5 are formed. Since it is a conductive material and these are in contact with each other, the characteristic that SiC withstands a high voltage is impaired due to the Si layer, and the characteristic of SiC cannot be exhibited. Also, the structure of FIG. 2B is not preferable because a leakage current is generated due to crystal defects generated between the Si substrate and the SiC layer. In addition, if a SiC film can be formed on the silicon oxide film as in the structure of FIG. 2C, it may be possible to take advantage of the feature that SiC can withstand high voltages, but single crystal SiC is grown on the silicon oxide film. It is not possible.

FIG. 3 conceptually shows how the crystal defects are generated. As reported in each paper, a product defect occurs in a vertical direction from the interface of the Si substrate, and decreases rapidly as SiC moves away from the Si substrate interface, but does not become zero. Some reach the surface layer of SiC. As one example, the density is as large as about 10 ²⁰ pieces / cm ² at the interface, and the density is reduced to about 10 ¹⁰ pieces / cm ^{2 on} the surface with an SiC film thickness of 50 μm.

FIG. 4 shows an example of the detailed structure of the MOSFET of FIG. The structure of the MOSFET is similar to the structure prevalent in Si substrates. When the MOSFET is on, current flows from the drain electrode to the source electrode via the N ^- layer and the channel under the gate. In FIG. 4-c, important factors are shown as MOSFETs. Channel resistance in the on as shown in Figure 4-c, N ^- wants to resistance both small. In particular, in the power element, the N ^- resistance is dominant, and for this reason, the thickness of the N ^- layer and the impurity concentration are important factors. Crystal defects have no significant effect. When off, the source electrode is grounded, and a load voltage of several hundred volts or more is applied to the drain electrode. Gate voltage is MOSFET at the ground potential in FIG. 4-b is in the off N ^- P ^- a high voltage is applied between. As shown in FIG. 4D, the leakage current is an important factor when the switch is off. In particular, in the element using the SiC substrate, the leakage current due to the vertical crystal defect is a large value due to the presence of the crystal defect. That is, the leakage current at the gate of the MOSFET is not a problem, but the leakage at the PN junction is a problem due to crystal defects.

The actual case is shown in FIG. FIG. 5 shows measured values of the relationship between the current flowing through the reverse-biased PN junction and the reverse bias voltage applied to the PN junction, and FIG. 5-B models it. Leak does not occur up to a certain voltage, and when the crystal defect breakdown voltage Va is exceeded, the current along the defect starts to increase. When the breakdown voltage of the PN junction is reached, a large current starts to flow due to an electron avalanche. Thus, when the reverse bias voltage of PN is applied and the crystal defect breakdown voltage Va is exceeded, a leak current starts to flow, and a large leak current is generated before reaching the PN junction breakdown voltage Vb from this leak current. Reality. The leakage current generated by this crystal defect is a major obstacle to using a compound semiconductor for a power device. I want the device to have zero leakage current up to the breakdown voltage Vb of the PN junction, but due to the large number of vertical crystal defects unique to the SiC substrate, the application of the crystal defect breakdown voltage Va or higher at the PN junction plane parallel to the substrate The reality is that leakage current begins to occur due to voltage.

From this data, it can be considered that (A) if there is a PN junction surface only in a direction in which no electric field is applied to the crystal defect, a leakage current due to the defect does not occur, and (B) a PN junction is perpendicular to the direction of the crystal defect When a voltage is applied there, even if an electric field is generated along the crystal defect, the leakage current due to the crystal defect may be drastically reduced if the electric field is relaxed by some means.

One of the major needs of power devices is to control on / off of a large current, and for that purpose, to reduce the resistance value at the time of on-state. For this purpose, it is necessary to increase the thickness of the N ^- layer. On the other hand, in order to reduce the leakage current due to the defects in the vertical direction, the electric field applied to the PN junction surface is relaxed by some means such as (B) in the previous discussion. A means for establishing such a structure is desired.

FED Review Vol. 1 No. 16 2001

The problem to be solved by the present invention is to create a state in which even if there is a crystal defect, it does not lead to a leakage current, and the power device is put to practical use. The focus is to create a structure that does not lead to leakage current even if there is a crystal defect by relaxing the electric field of the PN junction surface perpendicular to the crystal defect with a PN junction that is reverse-biased in actual operation. If this structure can be realized, it will create great potential for the practical application of compound semiconductor power devices.

The configuration of the present invention is based on the practical application of a MOSFET formed on a single crystal SiC layer formed on an insulating film based on the consideration of FIGS. 4 and 5, and the practical application of a structure for reducing the leakage current of the MOSFET by electric field relaxation by the insulating film. And developing a technique for forming a single crystal SiC film on the insulating film.

The main point of the present invention is that the electric field strength applied to the PN junction surface such as the P well of the MOSFET formed on the insulating film is relaxed by the substrate voltage applied via the silicon oxide film, and the crystal defect is caused by the electric field at that portion. This realizes a structure in which the crystal defect leakage current generated along the line is reduced. The relaxation effect is increased by increasing the potential of the base substrate under the oxide film in the opposite direction to the drain potential as much as possible. That is, when the N-channel MOSFET shown in FIG. 4 is off, an electric field is applied by applying a voltage of about minus 100 volts or less to the base substrate in a practical state where the source is at the ground potential and the drain is at a potential of plus several hundred volts. It will increase the relaxation. Such a power source for applying a negative voltage can be formed and applied externally, or can be formed by a combination of its own elements by a circuit formed on a SiC substrate as in the present invention. If it can be formed in its own element as in the latter case, it becomes a self-supporting and innovative means for reducing leakage current.

As an element substrate for such an insulating isolation structure, the SiC film on the oxide film on the base substrate made of Si or the like has a thickness that allows electric field relaxation in the depletion layer of the oxide film and the PN junction surface, It is preferable to make the SiC film as thick as possible in order to reduce the on-resistance.

In a high-voltage driven lateral element, a PN distance is required to maintain the withstand voltage, but the PN junction distance of a portion that is simply generated by parasitic is wasted as a dead space. By forming this portion with an insulating isolation structure using a trench oxide film, the dead space can be reduced and the on-resistance per area can be reduced.

As a method for producing an element substrate having such a structure, first, a seed substrate with few crystal defects is produced, and an SiC layer having a thickness of about 1 μm is formed on the seed substrate by using a smart cut technique to form a silicon oxide film on the base substrate. Is to form on top. The smart cut technology and the bonding technology that have been put to practical use with Si are applied to the SiC substrate. The thick SiC layer can be formed by growing a SiC film on the SiC surface of the element substrate in which a thin SiC layer is formed on the silicon oxide film of the base substrate by smart cut.

Further, when forming a PN junction on the SiC substrate, the P-type layer and the N-type layer formed on the SiC layer require high temperature treatment of about 1600 ° C. for activation, and the junction depth is the heat In diffusion, since impurities hardly diffuse, there is a restriction that it is about 1 micron determined by the depth of ion implantation. When the base substrate is Si, the activation temperature is limited to about 1200 ° C., which is the melting temperature of Si, so it is necessary to select an impurity that can be activated at a low temperature. Although there are restrictions on reducing contact resistance, etc., it can be used depending on the application. On the other hand, for impurities that need to be activated at temperatures exceeding the melting point of silicon or the melting point of silicon oxide film, poly SiC is used for the base substrate, and if necessary, an insulating film can be used instead of the silicon oxide film. By using alumina, an activation treatment at 1600 ° C. or higher is possible. Thus, the activation temperature and the base substrate material can be selected according to the necessary contact resistance. In order to reduce the contact resistance, poly SiC that can be activated at a high temperature using aluminum or phosphorus is selected as the base substrate. When the contact resistance may be somewhat high, boron or phosphorus is used to increase the contact resistance to 1200. Si that can be activated at a temperature of about 0 ° C. can be selected as the base substrate.

In this way, the element substrate can be obtained by diverting the substrate bonding technology, trench technology, smart cut technology, which has been put into practical use, etc., which have been put into practical use in Si substrates, to SiC. As for the oxide film isolation structure, a trench is formed in the SiC film by trench etching technology, the SiC is removed, the silicon oxide film is exposed at the bottom of the trench groove, and the trench groove is filled with the silicon oxide film so that the SiC film is oxidized by silicon. A state in which the periphery and bottom surface are surrounded by a film can be created. By forming an element such as a MOSFET there, the individual elements are completely separated, and an integrated circuit can be formed by combining a plurality of high voltage elements. It is an epoch-making means that a reverse potential can be formed in the self-element in the base substrate using the integrated circuit.

There is a great expectation for the practical use of SiC substrates suitable for high-voltage driving. Up to now, the crystal defects in the vertical direction are large, and the influence thereof cannot be eliminated, and the reduction of crystal defects has been an issue. In order to reduce crystal defects, the element substrate manufacturing process becomes complicated, which increases the cost. The structure for relaxing the electric field applied to the PN junction of the MOSFET according to the present invention, in particular, a method of relaxing by setting the potential in the opposite direction to the voltage system using the base substrate potential, and a lateral element as means for realizing it The manufacturing method of the high-voltage driving element substrate and the element structure in which the SiC layer is formed on the base substrate through the insulating film and the SiC area is effectively utilized by the oxide film separation is also simple in the manufacturing method.

  Sectional drawing which shows the structure of a well-known SiC substrate   Cross-sectional view of the configuration of the SiC film on the Si substrate   Conceptual diagram of crystal defects occurring in SiC film on Si substrate   Cross-sectional view of MOSFET structure formed on SiC film on Si substrate and relationship diagram between applied voltage and leakage current   Actual current and reverse current generation model when reverse bias is applied   Sectional drawing of the structure of the MOS transistor formed in the thick SiC film on the silicon oxide film on the Si substrate of this invention   Electric field direction and electric field strength simulation example of PN junction formed in thick SiC film on silicon oxide film on Si substrate of the present invention   The figure which shows the relationship between the leakage current and the crystal defect breakdown voltage according to the structure of the present invention, the relationship between the base substrate potential, and the circuit diagram for generating the potential of the base substrate   Sectional view of the structure of the silicon oxide film and the thick SiC film on the Si substrate, the method of forming the device substrate of the trench structure, and the structure of the MOS transistor by the example using the smart cut method of the present invention   9 is a cross-sectional view of a method of forming a trench structure formed in the element substrate of FIG. 9 and the structure of a MOS transistor.

FIG. 6 shows a structure in which a MOSFET is formed on a thick single crystal SiC film 38 formed on a Si substrate via a silicon oxide film as an embodiment of the present invention. In the structure of FIG. 4B, an N ⁻ layer, a silicon oxide film layer 4 and a base substrate 5 exist on the lower surface of the P well. Further, in the figure, an example is shown in which a MOSFET is formed on a SiC film that is insulated and separated by a trench oxide film 52. In this structure, the periphery in the horizontal direction is insulated and separated by the trench oxide film 52. In the example, the thickness of the SiC film 38 is 10 μm, the depth of the source N ⁺ layer 65 and the drain N ⁺ layer 66 is 0.5 μm, the depth of the P well 58 serving as the channel portion is 1 μm, and the trench width is 1 μm. . In such a structure, when a load voltage is applied to the drain when the MOSFET is turned off, that is, when a reverse bias is applied to the PN junction, in the N ⁻ layer under the P well 58, the depletion layer and the oxide film due to the PN reverse bias are Electric field relaxation occurs due to a synergistic effect with the depletion layer due to the electric field. Therefore, even if longitudinal crystal defects exist, the voltage applied to the crystal defects is relaxed and it is difficult to reach the crystal defect breakdown voltage Va disclosed in FIG. A structure that does not become a current can be used. That is, the Va voltage in FIG. 5-b shifts to the high voltage side. In the present invention, a voltage in the direction opposite to the load voltage is applied to the base substrate to further increase the electric field relaxation in the N ⁻ layer under the P well 58.

FIG. 7A shows the state of electric field relaxation. The electric field from the drain is applied to the P well 58 by various routes, but the electric field from the oxide film is relaxed under the P well 58. FIG. 7B shows the state of electric field relaxation in the SOI (SiC on Insulator) structure. In the conventional structure of b1, the electric field from the drain wraps around under the P well, and there is a region with a high electric field. In the SOI structure, as shown in b2, the depletion layer under the P well is sandwiched between the P well and the oxide film and is pushed out from under the P well to be relaxed. In the figure, the source N ⁺ layer 65 and the drain N ⁺ layer 66 are 0.5 μm, and the channel P well layer 58 is 1 μm. On the oxide film, the N ^- layer 59 is 10 μm thick. Although the PN junction surface exists, the depletion layer can be enlarged due to the influence of the electric field from the underlying oxide film and the base substrate surface. It can be seen in the simulation diagram that the depletion layer in this region is spreading. This weakens the electric field strength and makes it difficult to reach the crystal defect breakdown voltage. At b3, by applying a negative voltage to the base substrate, the electric field under the P-well is further weakened, and even if there is a crystal defect 105 perpendicular to the substrate surface, the defect current does not flow along the crystal defect. Ideally, the Va point in FIG. 5B is shifted to the high voltage side to be the same as the Vb voltage.

In FIG. 8, a diagram similar to FIG. 5-b is 8-a, and shows that the Va voltage is shifted to a higher voltage side by setting the potential of the base substrate to a negative potential. FIG. 8B shows the actual values. By applying -200 volts to the base substrate potential, the Va point becomes 300 V, indicating that the generation of crystal defect current can be greatly suppressed. FIG. 8C shows a means for simply forming such a negative voltage. The self-oscillation 100 kHz voltage waveform shown in FIG. C-1 created in the SiC element is applied to the voltage application point 161 with the source potential 160 being the ground potential as a reference, and supplied to the negative voltage bias point 162 via the capacitor 150. To do. The potential at the negative voltage bias point is clamped by the diode 151 connected to the source potential 160 to give a negative voltage pulse signal shown in FIG. C-2 to the negative voltage bias point 162, and a stable negative voltage at the Vsub point 163 by the diode 152. It is a means for forming a voltage. At the Vsub point 163, the capacitance of the parasitic capacitor 153 is large, and the applied voltage applied via the capacitor 150 is smoothed. The Vsub point 163 is a base substrate of the SiC element, but all elements have an oxide film separation structure, and since there is no leakage current, a negative voltage having a value close to ΔV which is an amplitude voltage of self oscillation is generated. . Here, necessary oscillation circuits, diodes, capacitors, and the like can be formed in SiC separated by an oxide film.

6, 7, and 8 show examples of N-channel MOSFETs, it can be easily understood that P-channel MOSFETs can be formed based on the same concept. In addition, the insulated SiC layer shown in FIG. 10 can be not only a MOSFET but also a diode or a bipolar element. Thus, an integrated circuit can be formed by combining the SiC elements that are insulated and separated.

FIG. 9 shows a procedure for producing an element substrate in which a thick single crystal SiC film is formed on a silicon oxide film. FIG. 9A shows a seed SiC substrate 8 with as few crystal defects as possible. FIG. 9B is a cross-sectional view of the base substrate in which the silicon oxide film 4 is formed on the Si substrate 5. FIG. 9C shows a state in which hydrogen ions are implanted from the surface of the matching 9-a seed SiC substrate 8 to a depth of about 1 μm. This is for separating the SiC substrate at the interface of the hydrogen ion implantation layer later, and is a wafer thin film peeling method called smart cut which has been popular in recent years. The layer having a high concentration of hydrogen ions is a cleavage plane that separates the thin SiC film from the seed SiC substrate, and is referred to as a smart cut surface 34 in the present invention. FIG. 9D shows a state where the surface in the state of FIG. 9C and the surface of the silicon oxide film 4 formed on the Si substrate 5 in FIG. 9B are bonded together. Since the SiC substrate is warped due to a difference in internal defect density or the like, a flattening process such as using the flattening stage 20 is necessary. Depending on the size of the warp, there is a case where the element substrate is placed on the flattening stage and the suction from the suction hole 21 is insufficient. In that case, it is also necessary to apply pressure from the top of the figure to achieve flattening. After the bonding, the bonded wafer is cleaved at the smart cut layer 34 in which the hydrogen ions previously implanted are concentrated by bringing the bonded wafer to about 500 ° C., and FIG. The substrate 8 is separated. FIG. 9E shows a state in which the thin SiC film 35 on the surface of the seed SiC substrate is transferred onto the silicon oxide film 4 on the Si substrate 5 which is the base substrate by smart cut. The surface of the substrate shown in FIG. 9-e has the surface removed by CMP (Chemical Mechanical Polishing), the surface layer is planarized, and a SiC layer is laminated thereon. FIG. 9F shows a state where the SiC layer is thickened. The SiC layer, which was 1 μm thick in the stage of FIG. 9E, is as thick as 10 μm in this state.

When the substrate is made of silicon, the P-type layer and the N-type layer can be activated by a method in which only the surface of the SiC is heated and the base Si substrate is forcibly liquid-cooled. Alternatively, it can be activated by selecting an impurity material that can be activated below the melting point of Si. When it is desired to activate at a high temperature exceeding the melting point of Si, a poly SiC substrate or a sapphire substrate can be used as the base substrate.

The seed SiC substrate 8 separated by the smart cut technology from FIG. 9-d can be regenerated. That is, after CMP (Chemical Mechanical Polishing), it can be reused as FIG. If the thickness is reduced, SiC can be epitaxially grown on the seed SiC substrate 8 to increase the thickness. It is a well-known fact that the SiC film is grown on a seed crystal substrate with few crystal defects, and the grown SiC substrate can further reduce crystal defects. The feature of this method is that the seed crystal with few crystal defects can be reused.

In the example of FIG. 9, the Si substrate 5 and the seed SiC substrate 8 are bonded together after forming the silicon oxide film on the Si substrate via the silicon oxide film. It can be formed on a substrate and bonded to a Si substrate. Also, a silicon oxide film is formed on a SiC substrate, a silicon oxide film is also formed on the Si substrate, and the silicon oxide films are bonded to each other. It is also possible.

In the example of FIG. 9, an example in which the Si substrate 1 is used as a base substrate of an element substrate through a silicon oxide film is shown, but a poly SiC substrate can also be used as a low-cost substrate as the base substrate. The same applies to the description of FIG. 9 except that the Si substrate is replaced with a poly SiC substrate. When poly SiC is used as the base substrate, the maximum holding temperature after the single crystal compound semiconductor film is formed on the oxide film on the poly SiC base substrate by smart cutting is restricted by the Si material. Therefore, the P-type semiconductor layer and the N-type semiconductor layer can be formed and activated at a high temperature in the state shown in FIG. In the case of FIG. 9, the case of using a silicon oxide film as the insulator has been described. However, it is also possible to use a material having a high melting point such as alumina. This is particularly effective when poly SiC is used as the base substrate, and the activation process can be performed at a high temperature after bonding.

Although FIG. 9 shows a method of laminating the thick SiC layer 38 on the smart-cut thin SiC layer 35, the thickness is not limited. On the other hand, the thickness limit that can be smart cut by implanting hydrogen ions is less than 10 μm from the acceleration energy limit. Therefore, it is possible to select whether to form the SiC film only by the smart cut method or to select the method of FIG. 9 depending on the required SiC thickness.

In FIG. 10, in order to form a plurality of elements such as MOSFETs in the SiC film portion, a procedure for forming a structure in which the periphery of the element is surrounded by an oxide film and the periphery and the bottom are all surrounded by a silicon oxide film is shown. . This is realized by removing the surrounding SiC forming the element by a trench etching technique, forming a trench groove, and filling the trench groove with a silicon oxide film. FIG. 10A shows a thick SiC film 38 on the silicon oxide film 4 on the Si substrate 5 shown in FIG. 9F. Since the thin SiC film 35 transferred from the seed SiC crystal substrate by bonding is the same quality as the thick SiC film grown there, only the thick SiC film 38 is shown in FIG. FIG. 10B shows a state in which a resist mask 50 for forming a trench is formed in this state. FIG. 10C shows a state in which the trench groove 51 is formed by etching the thick SiC film 38 into a groove shape by trench etching. The underlying silicon oxide film is exposed in the trench portion. FIG. 10D shows a state in which the resist mask 50 is peeled off, the trench groove 51 is then filled with a silicon oxide film to form a trench oxide film 52, and then the surface is polished and flattened. This series of trench formation, silicon oxide film filling, and planarization is a known procedure. This is a technique that has been put to practical use in the Si film on the silicon oxide film on the Si substrate. As a result, the SiC film is insulatively isolated by surrounding the bottom and bottom surfaces with the silicon oxide film. FIG. 10E shows an example in which a MOSFET is formed on this substrate. The detailed structure of the MOSFET is shown in FIG. In this way, an element in which each element is completely insulated and separated by an oxide film can be formed. As a result, a plurality of MOS transistors are insulated and separated, and an epoch-making structure capable of forming an integrated circuit on the SiC film can be obtained.

9 and 10 show an example in which the Si substrate 5 is used as a base substrate of an element substrate via a silicon oxide film, but a poly SiC substrate can also be used as a low-cost substrate as the base substrate. The same applies to the description of FIGS. 9 and 10 except that the Si substrate is replaced with a poly SiC substrate. When poly SiC is used as a base substrate, the maximum holding temperature after bonding a seed SiC substrate and forming a single crystal compound semiconductor film on an oxide film on a poly SiC base substrate by smart cut is Si material. Therefore, the formation and activation treatment of the P-type semiconductor layer and the N-type semiconductor layer described in FIG. 9C can be performed at a high temperature in the state of FIG.

In the examples of FIGS. 9 and 10, the case of using a silicon oxide film as the insulator has been described, but a material having a high melting point such as alumina may be used. As the insulator of the trench portion, not only the silicon oxide film but also alumina or other insulators can be used. These are particularly effective when a poly SiC substrate is used as the base substrate, and the activation treatment can be performed at a high temperature after bonding.

In the examples of FIGS. 6 to 10 described above, SiC has been described as an example of a single crystal compound semiconductor, but the same applies to other compound semiconductors such as GaN. In addition to Si and SiC, a material having a lattice constant close to that of a compound semiconductor such as Ge can be used as the substrate, and an insulating substrate such as a sapphire substrate can also be used.

Industrial applicability

High-voltage drive elements using SiC substrates, GaN substrates, and the like are becoming increasingly important with the spread of hybrid vehicles and electric vehicles. In addition, with the spread of smart grids in homes, the role of high voltage elements becomes important for the electrification and energy management of home appliances. On the other hand, these high-voltage drive elements have not been put into practical use due to leakage current due to crystal defects. According to the present invention, in a device in which a single crystal SiC thin film is formed on an Si substrate via an oxide film and a device is formed thereon, a leak due to crystal defects does not occur in a PN junction in a planar direction that is reverse biased. A great effect can be produced, which greatly contributes to the spread of devices in this field. There are similar expectations for other compound semiconductors such as GaN. In addition, a method capable of forming an isolation element by an oxide film isolation structure is epoch-making as a compound semiconductor such as SiC or GaN, and is a base for practical application of an integrated circuit of a compound semiconductor.

DESCRIPTION OF SYMBOLS 1 ... Si substrate used as a seed substrate 2 ... SiC film 3 ... SiC film 4 ... Silicon oxide film 5 ... Si substrate 8 ... Seed crystal 10 ... 2nd SiC substrate DESCRIPTION OF SYMBOLS 11 ... MOSFET source part 12 ... MOSFET drain part 13 ... MOSFET gate insulating film 14 ... MOSFET gate electrode 15 ... N ⁺ layer 16 ... P ⁺ layer 20 ... -Flattening stage 21-Intake hole 32 of flattening stage-SiC layer with many crystal defects 33-SiC layer 34 with few crystal defects-Smart cut layer 35-Thin film SiC layer 37- .... Thin SiC layer 38 ... Thick SiC layer 40 ... Silicon oxide film 41 ... Silicon oxide film 50 ... Resist mask 51 ... Trench groove 52 ... Trench oxide film 58 ... P Well 9 · · · N ^- layer 61 · · · MOSFET source electrode 62 the gate electrode 65 of the gate film 64 · · · MOSFET drain electrode 63 · · · MOSFET of · · · MOSFET · · · source N-type layer 66 .. Drain N-type layer 68 ... element isolation part 69 ... on-current path 101 ... short crystal defect 102 ... long crystal defect 104 ... crystal defect 105 ... crystal defect at the PN junction surface 110 ... Channel current 111 ... Depletion layer leakage current 112 ... Crystal defect current 150 ... Capacitor 151 ... Clamp diode 152 ... Smoothing diode 153 ... Parasitic diode 160 ... Source potential 161 ... Voltage application point 162 ... Negative voltage bias point 163 ... Vsub point

Claims (7)

A compound semiconductor having a single crystal compound semiconductor layer through an insulating film layer using a material such as a Si substrate, a SiC substrate, or a Ge substrate that is close to the lattice constant of the single crystal compound semiconductor layer formed over the insulating film as a base substrate A trench is formed in a single crystal compound semiconductor layer formed on the insulating film layer of the substrate or on the insulating film layer of the substrate, the trench reaches the insulating film layer, and an insulating film is formed in the trench portion. A single-crystal compound semiconductor layer is composed of a semiconductor element of a combination of a P-type semiconductor and an N-type semiconductor formed on a single-crystal compound semiconductor layer using an element substrate having one or a plurality of insulating and separated shapes, and is parallel to the substrate surface. In the PN junction surface where the reverse bias is applied in the direction, the device structure is such that the electric field strength is relaxed and applied to the PN junction surface by the insulating film or the base substrate The semiconductor device according to claim. 2. The PN junction surface comprising a semiconductor element of a combination of a P-type semiconductor and an N-type semiconductor formed in a compound semiconductor layer, wherein a reverse bias is applied in a direction parallel to the substrate surface. Alternatively, it is an element structure in which the electric field strength is relaxed and applied by the base substrate, and the electric field relaxation is increased by applying a voltage having a polarity opposite to the voltage of the power supply system for operating the element to the base substrate. Even if the applied voltage of the entire device is a high value, the electric field is relaxed so as to be lower than the defect breakdown voltage due to the crystal defect in the vertical direction existing on the PN junction surface that is reverse-biased in the direction parallel to the substrate surface. A semiconductor device configured. 2. The semiconductor device according to claim 1, wherein the semiconductor element is a combination of a P-type semiconductor and an N-type semiconductor formed in a single crystal compound semiconductor layer. In a semiconductor element having an element structure in which an electric field strength is relaxed by an insulating film layer or a base substrate, even if the applied voltage of the entire element is a high value determined by the intrinsic breakdown voltage of the PN junction A semiconductor device characterized by a structure in which an electric field is relaxed on a PN junction surface, which is reverse-biased in a direction parallel to a base substrate surface, so as to be lower than a defect breakdown voltage due to a crystal defect in a vertical direction. 4. The semiconductor element according to claim 1, wherein the semiconductor element is formed by a circuit of an SiC portion as means for applying a voltage having a reverse polarity. Claims 1, 2, 3, and 4 include: a seed that forms a smart cut layer by implanting ions such as hydrogen into a surface layer of a seed single crystal compound semiconductor substrate that is a source of a single crystal compound semiconductor layer. The surface of the single crystal compound semiconductor substrate is bonded to the surface of the base substrate Si or compound semiconductor via an insulating film, and then cleaved in the smart cut layer to remove the seed single crystal compound semiconductor substrate, and then on the base substrate. An element substrate and a semiconductor device using the element substrate, wherein the single crystal compound semiconductor layer remaining on the insulating film layer is polished and produced. Claims 1, 2, 3, and 4 include: a seed that forms a smart cut layer by implanting ions such as hydrogen into a surface layer of a seed single crystal compound semiconductor substrate that is a source of a single crystal compound semiconductor layer. The surface of the single crystal compound semiconductor substrate is bonded to the surface of the base substrate Si or compound semiconductor via an insulating film, and then cleaved in the smart cut layer to remove the seed single crystal compound semiconductor substrate, and then on the base substrate. An element substrate formed by growing the same single crystal compound semiconductor layer on a single crystal compound semiconductor layer remaining on the insulating film, and a semiconductor device using the element substrate. 7. The method according to claim 5 or 6, wherein as an attachment method through an insulating film, an insulating material is provided in advance on either or both of the seed single crystal compound semiconductor substrate and the base substrate, and the attachment is performed by an activation process. An element substrate and a semiconductor device using the element substrate.

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