JP5301091B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device with a little introduction of a crystal defect, by which an impurity layer at a thick back side is formed by a heat treatment not higher than a heat history which is added at the time of forming a surface structure. <P>SOLUTION: The method includes the steps of: mechanically grinding a backside 7 of an n semiconductor substrate 1 to flatten the backside 7, forming an FS layer 9 on a flattened backside 8 by using an epitaxial growing, and forming a p collector layer 12 on a surface layer thereof. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a punch-through element manufactured using an FZ (floating zone) wafer, that is, a MOSFET (MOS gate type field effect transistor), a PT type (FS type) IGBT (IGBT: insulated gate bipolar transistor). The present invention also relates to a method for manufacturing a semiconductor device such as a reverse blocking IGBT. PT represents punch through, and FS represents field stop.

  In recent years, development of punch-through elements using inexpensive FZ (floating zone) wafers has been progressing. An NPT (non-punch through) IGBT using an FZ wafer as shown in FIG. 5 was developed and put to practical use first. In this NPT type IGBT manufacturing method, after forming the surface cell structure of the IGBT, the surface electrode as the emitter electrode 10 is formed of aluminum to form the surface structure, and then the back surface is ground to a predetermined thickness, Boron ions are implanted and annealed at a low temperature of about 400 ° C. to form the p collector layer 31, and the back electrode as the collector electrode 13 is formed on the surface of the p collector layer 31 by vapor deposition or the like. This is an element structure in which the depletion layer 35 (high electric field region) does not reach the back collector layer 31 during forward blocking. In the figure, 1 is an n semiconductor substrate, 2 is a p base region, 3 is an n emitter region, 4 is a gate insulating film, 5 is a gate electrode, 6 is an interlayer insulating film, and 11 is a polyimide film as a protective film.

Thereafter, FS type IGBTs and reverse blocking IGBTs were developed by applying NPT type IGBT technology. As shown in FIG. 6, the FS type IGBT has an n ⁺ layer that is an n buffer layer 32 sandwiched between a p layer that is a p collector layer 33 on the back surface side and an n ⁻ layer (n semiconductor substrate 1) that is a drift layer. doing. The n ⁺ layer which is the n buffer layer 32 is called an FS (field stop) layer, and is formed by phosphorus ion implantation or the like. Unlike the NPT type IGBT, in the FS type IGBT, the depletion layer reaches the n ⁺ layer which is the n buffer layer 32 at the time of forward blocking, and thus the high electric field region develops to a position very close to the back surface (several microns).

As shown in FIG. 7, the reverse blocking IGBT is manufactured by covering the dicing region of the chip side surface (end 39) of the NPT type IGBT with a p isolation layer. When a reverse bias is applied to the IGBT, a depletion layer begins to extend from the p ⁺ / n ⁻ junction 40 of the p ⁺ layer as the p collector layer 15 and the n ⁻ layer (n semiconductor substrate 1) as the drift layer. The chip side surface (end portion 39) has many crystal defects. If the side surface is not covered with the p-isolation impurity layer 36, the depletion layer 35 is exposed to the chip side surface, and the reverse current is sufficiently reversed by the leakage current generated by the crystal defect. Pressure resistance cannot be obtained. If the p isolation impurity layer 36 is present, the depletion layer 35 cannot penetrate into the depth of the p isolation impurity layer 36 and does not reach the end 39, so that the leakage current does not increase. The p-collector layer 15 on the back side is formed by boron ion implantation and low-temperature annealing at 400 ° C. or lower as in the case of the NPT type IGBT. However, it is necessary to remove crystal damage due to mechanical grinding as much as possible by etching, etc. before ion implantation. However, crystal defects are not sufficiently removed due to low-temperature annealing, and leakage current is large (Fig. 3). Further, the thickness of the p collector layer 15 on the back surface side is usually 1 μm or less due to low temperature annealing, and therefore the depletion layer 35 approaches very close to the back surface 41. In the figure, 37 is an insulating film and 38 is a metal film. Although there is a method in which the thickness of the p collector layer is increased by high-speed ion implantation, the leakage current increases even if crystal defects are generated by ion implantation.

Even in an FZ type MOSFET (not shown), the depletion layer enters the vicinity of the back surface in the same manner as the FS type IGBT. A punch-through element manufactured using an FZ wafer and a reverse blocking IGBT both generate a high electric field near the back surface.
According to Patent Document 1, an n-type semiconductor region (drift region) formed in a middle layer region of a semiconductor substrate and an exposed bottom surface of a recess formed on the other main surface side of the semiconductor substrate, and an n-type semiconductor An n-type semiconductor region having an impurity density higher than that of the n-type semiconductor region, a p-type semiconductor region exposed on one main surface side of the semiconductor substrate, and joined to the n-type semiconductor region; The main operation of the element (diode) is constituted by the first main electrode layer formed in the exposed portion of the p-type semiconductor region and the second main electrode layer formed in the exposed portion of the n-type semiconductor region. It is disclosed that the thickness of the region can be reduced and a reduction in loss can be achieved.

  According to Patent Document 2, a step of bonding a silicon wafer to a support substrate through an oxide film, a step of grinding the silicon wafer to form a drain layer, a buffer layer and a high resistance layer on the collector layer And a step of forming a MOS gate on the surface of the high resistance layer. As a result, the high resistance layer that determines the breakdown voltage of the completed IGBT is formed by epitaxial growth with a small variation in specific resistance, so that a high-cost silicon wafer having a desired specific resistance is not required. Furthermore, it is disclosed that a buffer layer formed by epitaxial growth has a high concentration and narrow impurity concentration profile.

Patent Document 3 discloses that the junction depth is increased by diffusing an element having a large diffusion coefficient such as aluminum as an acceptor on the back surface to form a collector layer.
JP 2002-170963 A JP 2004-241534 A JP 2006-86414 A

For punch-through various elements and reverse blocking IGBTs manufactured using FZ wafers, scratches on the back surface become a major problem in the process from forming the back surface structure of the wafer to assembling the chip into the package. .
At the time of voltage blocking of each element, the high electric field region reaches the vicinity of the back surface. However, if a back surface scratch is applied to this electric field region, a leakage current is generated in this portion, and a predetermined breakdown voltage cannot be obtained. This is due to the electric field concentration due to the flaw shape, the current in the layering direction due to flaws on the flaw surface, and the current generated due to crystal defects introduced during the formation of the impurity layer on the back surface. If there is even one such scratch in the element area, there is a possibility that a withstand voltage failure will occur.

In order to prevent defects, it is necessary to separate the high electric field region from the back surface as much as possible during voltage blocking. This is to increase the thickness of the impurity layer on the back surface and bring the position of the pn junction away from the back surface of the wafer to the inside, and to reduce crystal defects introduced when forming the impurity layer on the back surface. There is nothing else.
However, in order to increase the thickness of the impurity layer on the back surface side, generally high-temperature and long-time thermal diffusion is required. For example, in order to diffuse phosphorus or boron by 10 μm, heat treatment at 1150 ° C. for about 20 hours is required. However, in the formation of the surface structure of the element, generally, such a heat history is not added, and if such a large heat history is added, the surface structure is greatly changed. For this reason, the originally designed characteristics cannot be obtained.

Patent Document 1 describes a diode, but does not mention an element having a MOS gate structure.
In Patent Document 2, a silicon wafer is bonded to a support substrate through an insulating film, and then the silicon wafer is ground and thinned, an epitaxial growth layer is formed thereon, and then a MOS gate structure is formed. The substrate and the insulating film are removed. In the present invention, after the MOS gate structure is formed on the front surface side, the back surface side is ground, and an epitaxial growth layer is formed on the ground back surface.

Further, in Patent Document 3, although the diffusion temperature is low at 1000 ° C., the junction depth is about 11 μm even for a long time diffusion of 6 hours, and the heat history (temperature × time) is large, which affects the surface structure. Arise.
An object of the present invention is to solve the above-described problems and form a thick back-side impurity layer by heat treatment less than the thermal history applied when the surface structure is formed, and a semiconductor device with less introduction of crystal defects. It is to provide a manufacturing method.

In order to achieve the above object, a step of forming a MOS gate structure on one main surface of a semiconductor substrate, a step of forming an interlayer insulating film on the MOS gate structure, and grinding and planarizing the other main surface A step of forming an epitaxial growth layer on the other planarized main surface, a step of forming a first main electrode on the interlayer insulating film after forming the epitaxial growth layer, and a second step on the epitaxial growth layer. and forming a main electrode in this order, said an area to be diced semiconductor substrate the semiconductor substrate and the different conductivity type impurity layer so that the side surfaces of each chip is covered after chip dicing of the semiconductor substrate Before the step of forming the MOS gate structure on one main surface, it is formed in a frame shape of each chip, and the epitaxial growth layer has a thickness of not less than 5 μm and not more than 50 μm. The manufacturing method is formed with a conductivity type different from that of the body substrate.

In addition, when forming the epitaxial growth layer, an etching gas is flowed simultaneously with the source gas, and the semiconductor layer is preferably epitaxially grown on the other planarized main surface.
The MOS gate structure may be a planar gate type or a trench gate type.

  According to the present invention, a MOS gate structure is formed on one main surface of a semiconductor substrate which is an FZ wafer, an interlayer insulating film is coated thereon, the other main surface is ground and flattened, and then a buffer is formed. A layer, a drain layer, or a collector layer is formed of an epitaxial growth layer, contact holes are formed in the interlayer insulating film to form an emitter electrode and a source electrode, and an epitaxial layer (in the case of a buffer layer, the collector layer is formed by diffusion or the like). By forming a drain electrode and a collector electrode on the upper surface of the substrate, it is possible to improve the resistance to scratches on the back surface of punch-through elements (FS-type IGBTs and MOSFETs) and reverse blocking IGBTs. Can improve the yield rate of products.

  Embodiments will be described in the following examples.

FIG. 1 shows a method of manufacturing a semiconductor device according to a first embodiment of the present invention. FIGS. 1A to 1C are cross-sectional views showing a main part manufacturing process shown in the order of steps. This semiconductor device is a planar gate type FS type IGBT having a withstand voltage of 1200V. In the following expressions, n is n-type and p is p-type.
A plurality of p base regions 2 are formed on the surface layer of the first main surface of the n semiconductor substrate 1 which is an FZ wafer having a thickness of 500 μm, and an n emitter region 3 is formed on the surface layer of the p base region 2. A gate electrode 5 is formed on the p base region 2 sandwiched between the region 3 and the n semiconductor substrate 1 via a gate insulating film 4 to form a planar cell structure on the surface, and then the surface is coated with 1 μm BPSG ( A boron phosphorous glass) film is covered with an interlayer insulating film 6 (FIG. 2A).

Next, the back surface 7 is mechanically ground to a wafer thickness of 120 μm. The back surface 7 is flattened by CMP (Chemical Mechanical Planarization) to make the wafer 110 μm. The flattened back surface 8 may be flattened by back surface spin etching with hydrofluoric acid-nitric acid mixed acid without being flattened by CMP. In an epitaxial (hereinafter abbreviated as epi) growth furnace at 970 ° C., 200 sccm of DCS (dichlorosilane) as a silicon source gas and 300 sccm of HCl as an etching gas are simultaneously supplied, and phosphine gas is further supplied as an n-type impurity. N-type episilicon (epitaxial silicon layer) is grown on the silicon surface of the back surface 8 without depositing silicon on the interlayer insulating film 6 on the front surface. The epi growth rate is 0.3 μm / min. In 40 minutes, 12 μm of n-type episilicon grows to become an FS layer 9 (n buffer layer) which is an n ⁺ layer. The surface structure is not affected due to the low thermal history. The n-type doping concentration is 2 × 10 ¹⁵ cm ⁻³ ((b) in the figure).

Next, a contact hole is formed in the interlayer insulating film 6 by photoetching, a surface metal layer is formed by sputtering of aluminum, and a surface electrode (emitter electrode 10) is formed by photoetching. A protective film is formed with the polyimide film 11 by polyimide coating and photoetching. A p ⁺ layer, which is the collector layer 12 on the back side, is formed by ion implantation of boron and annealing at 400 ° C. in a nitrogen atmosphere. Finally, the back electrode (collector electrode 13) is formed by four-layer deposition of Al / Ti / Ni / Au to complete the wafer process ((c) in the figure).

Next, although not shown, the product is completed by assembling into a package after chip dicing.
The position of the n ⁻ / n ⁺ junction 14 (interface) between the n ⁻ layer (n semiconductor substrate 1) and the n ⁺ layer (FS layer 9) on the back surface side is 12 μm away from the back surface 17 so that the depth is several microns during the process. Even if a back surface scratch (a scratch on the back surface 17) occurs, the breakdown voltage does not decrease. Conventionally, the FS layer is formed by phosphorus ion implantation, and the n ⁻ / n ⁺ junction depth of the n ⁻ layer and the n ⁺ layer is about 2 μm. did. In this embodiment, since the thick FS layer 9 is formed, it is possible to prevent a breakdown voltage failure due to scratches.

When the FS layer 9 which is the n ⁺ layer is formed by the epitaxial growth layer, the introduction of crystal defects and heavy metals is suppressed as compared with the case where the FS layer 9 is formed by thermal diffusion. it can. The thickness of the epitaxial growth layer can be increased. The thickness of the FS layer 9 before the formation of the p-type collector layer 12 - case for (from the back surface 16 ⁿ / ^{n +} distance to the junction 14) of the FS type IGBT, 2μm~50μm is practical range, 10 [mu] m If it is more than about, it is desirable that the leakage current can be suppressed even if there is a large scratch.

Incidentally, the above IGBT is the same effect can be expected in the case of is a planar gate type shown intention wrench gate.

FIG. 2 shows a method of manufacturing a semiconductor device according to a second embodiment of the present invention. FIGS. 2A to 2C are cross-sectional views of the main part manufacturing process shown in the order of steps. This semiconductor device is a planar gate type 1200V withstand voltage reverse blocking IGBT. Although only a part of the cell is shown in the figure, a plurality of line-symmetric shapes with respect to the cross section are formed, and a breakdown voltage structure including a p-isolation impurity layer is shown at the periphery of the chip.

  A plurality of frame-shaped p isolation impurity layers (not shown) (corresponding to the p isolation impurity layer 36 in FIG. 7) having a depth of 180 μm or more are formed from one main surface of the n semiconductor substrate 1 which is an FZ wafer toward the inside. A plurality of p base regions 2 are formed on the surface layer of the first main surface of the n semiconductor substrate 1 in the frame, and an n emitter region 3 is formed on the surface layer of the p base region 2. A gate electrode 5 is formed on a p base region 2 sandwiched between n semiconductor substrates 1 through a gate insulating film 4 to form a planar cell structure on the surface, and then a surface of the BPSG film having a 1 μm interlayer insulation. It is covered with a film 6 ((a) in the figure).

Next, the back surface 7 is mechanically ground until a p-isolation impurity layer (not shown) is reached, so that the wafer thickness is 190 μm. The back surface 7 is flattened by CMP to make the wafer 180 μm thick. The back side may be planarized by spin etching with a hydrofluoric acid-nitric acid mixed acid. At 970 ° C. in an epi furnace, 200 sccm of silicon source gas DCS (dichlorosilane) and 300 sccm of etching gas HCl are simultaneously supplied, and further, diborane gas is supplied as a p-type impurity. P-type epitaxial silicon is grown on the silicon surface on the back surface side without depositing silicon on the insulating film on the front surface side. The growth rate is 0.3 μm / min, and 6 μm of p-type episilicon is grown in 20 minutes to become a p collector layer 15 connected to a p isolation impurity layer (not shown). In the formation of the p collector layer 15, the surface structure is not affected because the thermal history is small. The p-type doping concentration is 2 × 10 ¹⁶ cm ⁻³ ((b) in the figure).

  Next, a contact hole is formed in the interlayer insulating film 6 by photoetching, a surface metal layer is formed by sputtering of aluminum, and a surface electrode (emitter electrode 10) is formed by photoetching. A protective film for the polyimide film 11 is formed by polyimide coating and photoetching. Finally, the back electrode (collector electrode 13) is formed by four-layer deposition of Al / Ti / Ni / Au to complete the wafer process ((c) in the figure).

Next, although not shown, the product is completed by assembling into a package after chip dicing.
The position of the n ⁻ / p ⁺ junction 16 of the n ⁻ layer and the p ⁺ layer on the back surface is 6 μm away from the back surface 17, so that the withstand voltage does not decrease even if a back surface scratch having a depth of 2 to 3 microns occurs during the process. . Conventionally, the p collector layer is formed by boron ion implantation and low-temperature annealing at 400 ° C. or lower, and the n ⁻ / p ⁺ junction depth of the n ⁻ layer and the p ⁺ layer is about 0.5 μm at most, If there is a micron order scratch, the breakdown voltage will be reduced. Even with small scratches of 0.5 μm or less, the crystal defects were not sufficiently recovered and the lifetime killer was short, so that the leakage current increased.

In the second embodiment, since the 6 μm thick p collector layer 15 is formed, it is possible to greatly prevent a breakdown voltage failure due to scratches. In the second embodiment, since the p collector layer 15 is formed of an epitaxially grown layer and annealing is sufficiently performed and the lifetime in the p collector layer 15 is long, the n ⁻ / p ⁺ junction 16 of the n ⁻ layer and the p ⁺ layer is used. The depth of is about 0.5 μm, and an increase in leakage current is suppressed.

FIG. 3 shows the reverse leakage current of the reverse blocking IGBT having a withstand voltage of 1200 V manufactured according to the second embodiment. A is the second embodiment and B is the conventional example. The reverse leakage current of the second embodiment is reduced to 1/5 of the reverse leakage current of the conventional reverse blocking IGBT.
In the case of a reverse blocking IGBT, the thickness of the p collector layer 15 formed of an epitaxial growth layer is in a practical range of 0.5 μm to 50 μm. It is possible and desirable. ^Usually, n - / ^{p +} towards the junction 16 is ⁿ - / ^{n +} hardly affected by the electric field strength than the junction 14, the junction depth is ⁿ - / ^{n +} shallower leak current from the junction 14 is suppressed Is done. Therefore, the minimum value in the practical range of the thickness of the p collector layer 15 may be 0.5 μm.

  The IGBT is a planar gate type, but the same effect can be expected in the case of a trench gate type (not shown).

FIG. 4 shows a method of manufacturing a semiconductor device according to a third embodiment of the present invention. FIGS. 4A to 4C are cross-sectional views of the main part manufacturing process shown in the order of processes. This semiconductor device is a planar gate type MOSFET.
A plurality of p base regions 2 are formed on the surface layer of the first main surface of the n semiconductor substrate 1 which is an FZ wafer, and an n source region 21 is formed on the surface layer of the p base region 2. The gate electrode 5 is formed on the p base region 2 sandwiched between the substrates 1 through the gate insulating film 4 to form a planar cell structure on the surface, and then the interlayer insulating film 6 of a BPSG film having a surface of 1 μm. Cover with ((a) of the figure).

Next, the back surface 7 is mechanically ground to a wafer thickness of 120 μm. The back surface 7 is flattened by CMP to make the wafer 110 μm. Planarization may be performed by back surface spin etching using a hydrofluoric acid-nitric acid mixed acid. In an epitaxial (hereinafter abbreviated as epi) growth furnace at 970 ° C., 200 sccm of DCS (dichlorosilane) as a silicon source gas and 300 sccm of HCl as an etching gas are simultaneously supplied, and phosphine gas is further supplied as an n-type impurity. N-type episilicon (epitaxial silicon layer) is grown on the silicon surface of the back surface 8 without depositing silicon on the interlayer insulating film 6 on the front surface. The growth rate is 0.3 μm / min. In 40 minutes, 12 μm of n-type episilicon grows to become an n drain layer 22 which is an n ⁺ layer. The surface structure is not affected due to the low thermal history. The n-type doping concentration is 1 × 10 ¹⁹ cm ⁻³ ((b) in the figure).

  Next, a contact hole is formed in the interlayer insulating film 6 by photoetching, a surface metal layer is formed by sputtering of aluminum, and a surface electrode (source electrode 23) is formed by photoetching. A protective film for the polyimide film 11 is formed by polyimide coating and photoetching. Finally, the back surface electrode (drain electrode 24) is formed by four-layer deposition of Al / Ti / Ni / Au, and the wafer process is completed ((c) in the figure).

Next, although not shown, the product is completed by assembling into a package after chip dicing.
The back surface side n ⁻ layer and the n ⁺ layer n ⁻ / n ⁺ junction 25 (interface) are separated from the back surface 10 by 10 μm, resulting in back surface scratches (scratches on the back surface) of several microns in the process. However, the pressure resistance does not decrease.
Also in this case, the thickness of the epitaxial growth layer is set to 2 μm to 50 μm, preferably about 10 μm or more, as in the first embodiment.

  Although the MOSFET is a planar gate type, the same effect can be expected in the case of a trench gate type (not shown).

BRIEF DESCRIPTION OF THE DRAWINGS It is a manufacturing method of the semiconductor device of 1st Example of this invention, (a)-(c) is principal part manufacturing process sectional drawing shown to process order FIG. 2 is a method for manufacturing a semiconductor device according to a second embodiment of the present invention, wherein FIGS. The figure which shows the reverse leakage current of the reverse blocking IGBT of 1200V withstand voltage | pressure manufactured by 2nd Example. FIG. 4 is a method for manufacturing a semiconductor device according to a third embodiment of the present invention, in which (a) to (c) are cross-sectional views of the main part manufacturing process shown in the order of processes; Cross-sectional view of main parts of NPT (non-punch through) IGBT Cross-sectional view of the main part of a conventional FS type IGBT Main part sectional drawing of the edge part of reverse blocking IGBT

Explanation of symbols

1 n semiconductor substrate 2 p base region 3 n emitter region 4 gate insulating film 5 gate electrode 6 interlayer insulating film 7 back surface (before grinding)
8 Back side (after flattening)
9 FS layer 10 Emitter electrode 11 Polyimide film 12, 15 p Collector layer 13 Collector electrode 14, 25 n ⁻ / n ⁺ junction 16 n ⁻ / p ⁺ junction 17 Back surface (surface of epitaxial growth layer)
21 n source region 22 n drain region 23 source electrode 24 drain electrode

Claims (3)

Forming a MOS gate structure on one main surface of the semiconductor substrate; forming an interlayer insulating film on the MOS gate structure; grinding and flattening the other main surface; forming an epitaxial growth layer on the main surface, forming a first main electrode on the interlayer insulating film after forming the epitaxial growth layer, and forming a second main electrode on the epitaxial growth layer on the turn having, a MOS gate structure on one principal surface of the semiconductor substrate with a conductivity type different from said semiconductor substrate an impurity layer of that side of each chip is covered an area which is diced the semiconductor substrate after chip dicing Before the forming step, each chip is formed in a frame shape, and the epitaxial growth layer is formed with a thickness of 5 μm or more and 50 μm or less and a conductivity type different from that of the semiconductor substrate. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein when the epitaxial growth layer is formed, an etching gas is flowed simultaneously with the source gas to epitaxially grow the semiconductor layer on the other planarized main surface. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the MOS gate structure is a planar gate type or a trench gate type.

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