JP4951872B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention is a high withstand voltage power having a deep planar type main junction such as MOSFET (insulated gate field effect transistor), IGBT (insulated gate bipolar transistor), super junction semiconductor device, BJT (bipolar junction transistor), thyristor, diode. More particularly, the present invention relates to a method for manufacturing a high breakdown voltage power semiconductor device that improves characteristics by reducing crystal defects or the like that adversely affect semiconductor characteristics by gettering. In particular, the present invention relates to a method for manufacturing a semiconductor device such as a reverse blocking IGBT used in a power conversion device or the like.

An IGBT (insulated gate bipolar transistor) having a conventional planar junction structure as shown in FIG. 15 is used under a direct current power source in an inverter circuit and a chopper circuit, which are the main mounted circuits. There was no problem as long as the withstand voltage was secured.
On the other hand, in a matrix converter developed for further improving power conversion efficiency, a reverse blocking IGBT has been required for a high-speed switching element to be mounted. Since the reverse blocking IGBT has a bidirectional withstand voltage characteristic, it is also referred to as a bidirectional IGBT.
A reverse blocking IGBT is shown in FIG. The reverse blocking IGBT has a separation layer 2 in which the impurity diffusion layer reaches from the one main surface of the semiconductor substrate 1 to the other main surface in order to ensure a reverse blocking breakdown voltage. The formation of the separation layer 2 requires high-temperature and long-time impurity diffusion in an oxygen atmosphere in order to prevent surface roughness of the first main surface of the silicon substrate 1. The impurity diffusion condition is, for example, about 1 hour at 1300 ° C. for a device with a withstand voltage of 600V and about 200 hours at 1300 ° C. with a withstand voltage device for 1200V. When such a high-temperature and long-time heat treatment is applied to the silicon substrate 1 in an oxygen atmosphere, the high-temperature silicon substrate 1 at 1300 ° C. has a very high oxygen diffusion coefficient and a long high-temperature treatment time (100 Over a period of time), oxygen is taken in a high concentration almost uniformly throughout the entire thickness of the substrate 1, so that the substrate 1 has a flat solid solution concentration distribution. In addition, the incorporated oxygen becomes a donor and increases the impurity concentration of the drift layer to lower the breakdown voltage, or causes crystal defects due to the high concentration oxygen, and increases the forward and reverse leakage currents of the reverse blocking IGBT. It has a problem of causing a decrease in breakdown voltage and reverse breakdown voltage.

As a countermeasure against such a problem, a gettering method is known as a technique for removing the crystal defects generated with the formation of the separation layer. For the above-described crystal defects caused by high-concentration oxygen, a method called extrinsic gettering (EG) for forming a gettering site on the second main surface of the substrate is used. In the EG method, there are a sand blast method for forming a mechanical strain layer and a poly back seal method (Poly-Si Back Seal: PBS (registered trademark)) for depositing a polycrystalline silicon film on the second main surface. A poly back seal method is used for the blocking IGBT.
In addition, as a known technique for reducing the adverse effect on the semiconductor characteristics due to the formation of the separation layer, when forming the reverse blocking IGBT having the separation layer, a trench is formed in advance at the formation position of the separation layer to shorten the diffusion time. Thus, an invention is known in which the stress caused by the above-described high-temperature and long-time heat treatment in an oxygen atmosphere is reduced to prevent deterioration of the breakdown voltage (Patent Document 1).
JP 2004-336008 A

However, as the EG, a polyback seal made of polycrystalline silicon having a thickness of 1.5 μm is formed on the second main surface side, and the oxide layer formed on the first main surface side is used as a mask to diffuse the separation layer, Then, after removing the mask oxide film on the first main surface side, a MOS gate structure is formed on the first main surface side, and the second main surface is reduced to the required thickness by grinding to the second main surface side. In the reverse blocking IGBT obtained by forming the collector layer, the polyback seal formed on the second main surface is already almost single-crystallized at the stage after the formation of the separation diffusion mask oxide film, and the gettering effect is It was hardly seen.
The present invention has been made in view of the problems associated with the above-described method for manufacturing a semiconductor device that requires high-temperature and long-time separation and diffusion. The object of the present invention is to accompany high-temperature and long-time separation and diffusion. Another object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the influence on the breakdown voltage characteristics due to crystal defects caused by high concentration oxygen introduced into the semiconductor substrate.

According to the invention of claim 1, wherein the appended claims, the object is first to introduce p-type impurity of the first major surface or found before Symbol semiconductor substrate an oxide film of the n-type semiconductor substrate as a mask And the process of
After the first step , a high-temperature heat treatment is performed in an oxygen atmosphere to form a p-type separation layer having a required depth. Along with this, a crystal defect caused by high concentration oxygen occurs in the semiconductor substrate. And the process of
After the second step, a high-concentration phosphorus- doped layer is formed on the first main surface and the second main surface by high-temperature heat treatment using a gas containing phosphorus element, and is formed on the second main surface. A third step in which the lattice mismatch caused by the phosphorus-doped layer causes dislocation and becomes a gettering source;
Later than the third step, the line Ukoto ion implantation argon second principal, a fourth step of forming a crystal strain layer on the second main surface serves as a gettering source,
After the fourth step , a required semiconductor functional region is formed on the first main surface by a step including heat treatment at 1000 ° C. or higher, and at the same time, a crystal caused by the high concentration oxygen from the operation region to the gettering source A fifth step of capturing defects and reducing the density of crystal defects in the operating region;
Later than the fifth step, a sixth step the separation layer to the thickness reduced from the second main surface side to expose with removing the phosphorus-doped layer of the second main surface side,
This is achieved by providing a method for manufacturing a semiconductor device characterized by comprising:
According to the second aspect of the present invention, the third step includes forming a gate insulating film and a polycrystalline silicon region in a predetermined region surrounded by the isolation layer on the first main surface. the phosphorus-doped by a row Ukoto on both sides of the first main surface and the second major surface, the polycrystalline silicon region of said first main surface as well as the phosphorus-doped conductive layer, said well to said second major surface phosphorous doping Forming a layer ,
In the fifth step , a required MOS structure is formed on the first main surface by the step .
The method of manufacturing a semiconductor device according to claim 1 is preferable.

According to the invention of claim 3, wherein in the claims, the first step includes a comprising forming said isolation layer on said semiconductor substrate polysilicon back seal is formed on the second main surface and more preferably in the method according to claim 2, wherein the range of the claims.
According to the invention of claim 4, wherein the range of patent claims, appended claims, which comprises using a material as phosphorus oxychloride or phosphine containing the phosphorus element to be used for formation of the phosphorus-doped layer 1 It is more desirable to use the method for manufacturing a semiconductor device according to any one of Items 1 to 3.

According to the invention described in claim 5 , the semiconductor device according to any one of claims 1 to 4 , wherein the semiconductor device is a reverse blocking IGBT (insulated gate bipolar transistor). It is preferable to use this manufacturing method.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device which can reduce the influence on the pressure | voltage resistance characteristic by the crystal defect resulting from the high concentration oxygen introduce | transduced into a semiconductor substrate with high temperature long time separation diffusion can be provided.

Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings, taking a reverse blocking IGBT as an example. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
The semiconductor device described below is an example of a reverse blocking IGBT having a withstand voltage of 1200V. The cross-sectional view described below is a cross section of a portion corresponding to one element of the IGBT in the silicon substrate. A polysilicon film having a thickness of 1.5 μm is formed on the second main surface 9-1 of the FZ-n type semiconductor substrate 1 (FIG. 1) having a thickness of 525 μm and an impurity concentration of 7.5 × 10 ¹³ cm ⁻³ by the CVD method. Thus, a poly back seal 1a is obtained (FIG. 2). The formation of the poly back seal is intended to getter the crystal strain layer. However, in the case of reverse blocking IGBT, a thick initial oxide film serving as a separation layer diffusion mask in the process after the poly back seal is formed. A large amount of oxygen-induced defects are generated by the long-time diffusion due to the formation of the oxide and the separation layer. At that time, the polysilicon becomes a single crystal and almost no gettering effect is obtained. With the poly back seal alone, the reverse blocking IGBT has a large forward / reverse leakage current, and the yield rate of the withstand voltage is reduced. The formation process can be omitted.

Subsequently, an initial oxide film 11 having a thickness of 2.4 μm (1.6 μm when the withstand voltage class is 600 V) is formed on the first main surface 9-2, and the p base region 2 is formed in a later process. An opening 12 having a width of 100 μm is formed in the periphery of the substrate by photoetching (FIG. 3). Next, after applying a boron source to the first main surface 9-2, a boron deposition region is formed by heat treatment, and the depth is 200 μm in an oxygen atmosphere at a temperature of 1200 ° C. or higher (100 μm when the withstand voltage class is 600 V). Boron is diffused until a separation layer 2 is formed (FIG. 4).
After removing the separation layer diffusion mask oxide film (FIG. 5), after forming the gate oxide film 5 and the polycrystalline silicon film 6 (FIG. 6), the polycrystalline silicon film 6 is made conductive so that the gate electrode and When phosphorus doping is performed, a gas such as POCl ₃ (phosphorus oxychloride) or PH ₃ (phosphine) is used after removing the gate oxide film 5 and the polycrystalline silicon film 6 on the second main surface side in advance. A high-concentration phosphorus-doped layer having a surface concentration of phosphorus of 1 × 10 ²⁰ cm ⁻³ can be obtained by performing high-temperature heat treatment, for example, using N ₂ (nitrogen) as a carrier gas and doping at 920 ° C. for 1 hour. It is also formed on the two principal surfaces (FIG. 7). The lattice mismatch caused by the high-concentration phosphorus-doped layer formed on the second main surface side causes dislocation, which becomes a gettering source. This gettering source improves the crystal strain layer formed during the separation and diffusion, and improves the crystallinity and improves the semiconductor characteristics. This ring getter process is the most important aspect of the present invention. Further, at this stage, Ar (argon) may be ion-implanted from the second main surface at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration voltage of 100 keV. A crystal strain layer serving as a gettering source is also formed on the second main surface by Ar ion implantation. Thereafter, required patterning is performed on the first main surface side (FIG. 8), and the p ⁺ well layer 3a is formed at 1100 ° C./200 minutes and the p base layer (channel layer) 3b is formed by 1150 by a self-alignment method or the like. C./120 minutes. During these high-temperature heat treatments at 1000 ° C. or higher, oxygen-induced defects can be taken into the gettering source from the IGBT operating region (extrinsic gettering), so that the density of crystal defects in the operating region can be reduced. Can be small. Next, the n ⁺ emitter layer 4 and the second p ⁺ layer 3c are formed by ion implantation of arsenic and boron, respectively, and activated by annealing at 1000 ° C./30 minutes to form the emitter metal electrode 7, Accordingly, a protective film (not shown) such as a polyimide film is applied (FIG. 9). Furthermore, an electron beam is introduced at 6 Mrad in order to reduce the reverse leakage current after forming the MOS structure on the first main surface of the IGBT. In addition, electron beam irradiation or helium irradiation may be performed in order to increase the speed.

Next, the second main surface is mechanically cut down to 200 μm (100 μm when the withstand voltage class is 600 V). Chemical etching or chemical mechanical polishing is performed in order to remove stress and strain when the second main surface is cut. In the case of chemical etching, the surface condition is improved by processing the chemical solution at an etching rate of 0.25 to 0.45 μm / sec. In the case of chemical mechanical polishing, the polishing amount is about 3 μm. When the chemical mechanical polishing process is performed, the rough surface after grinding can be made into a mirror surface. This is very effective in improving the reverse breakdown voltage characteristics of the reverse blocking IGBT (FIG. 10). Finally, the thickness of the FZ silicon substrate 1 is set to about 180 μm, and the p ⁺ type separation diffusion layer 2 is exposed on the shaving surface 10.
Next, boron having a dose of 5 × 10 ¹³ cm ⁻² is ion-implanted into the second main surface, and low-temperature annealing is performed at about 400 ° C. for about 1 hour. The peak concentration of activated boron is 1 × 10 ^17. A collector layer 8 having a thickness of about cm ⁻³ and a thickness of about 1 μm is formed (FIG. 11), and a collector electrode film 8-1 is formed on the second main surface so as to be in ohmic contact. Finally, the semiconductor substrate is cut at the center 2-1 of the separation layer to produce the reverse blocking IGBT shown in FIG. This reverse blocking IGBT is the same as the IGBT shown in FIG.

Further, when the peak concentration of the p ⁺ collector layer 8 on the second main surface is less than 5 × 10 ¹⁶ cm ⁻³ , the injection efficiency is lowered and the on-voltage is increased. In addition, the p ⁺ collector layer 8 is completely depleted when a reverse voltage is applied, and the reverse breakdown voltage is also reduced. On the other hand, since the number of injected minority carriers exceeding 1 × 10 ¹⁸ cm ⁻³ increases and the reverse recovery current also increases, the peak concentration is preferably 5 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less. .
FIG. 13 shows a comparison of the forward leakage current value at room temperature with and without the above-described ring getter process, and FIG. 14 shows a comparison of the reverse leakage current value at room temperature with and without the ring getter process. From these figures, it can be seen that when the ring getter process is performed, the forward leakage and reverse leakage current values are about half that of the case where the ring leakage process is not performed. As a result, by performing the ring getter process, the non-defective product ratio of the forward breakdown voltage and the reverse breakdown voltage can be made 90% or more.
Since the ring getter layer containing the crystal defect exhibits the gettering effect and is removed by the second main surface grinding step, it does not remain in the completed reverse blocking IGBT and does not have a secondary adverse effect.

  In the above-described embodiment, the manufacturing method of the reverse blocking IGBT has been described. However, the present invention is applied not only to the reverse blocking IGBT but also to other semiconductor devices such as a diode having a separation diffusion layer and a conventional IGBT. it can.

It is sectional drawing (the 1) which shows the manufacturing method of reverse blocking IGBT concerning this invention. It is sectional drawing (the 2) which shows the manufacturing method of reverse blocking IGBT concerning this invention. It is sectional drawing (the 3) which shows the manufacturing method of reverse blocking IGBT concerning this invention. It is sectional drawing (the 4) which shows the manufacturing method of reverse blocking IGBT concerning this invention. It is sectional drawing (the 5) which shows the manufacturing method of reverse blocking IGBT concerning this invention. It is sectional drawing (the 6) which shows the manufacturing method of reverse blocking IGBT concerning this invention. It is sectional drawing (the 7) which shows the manufacturing method of reverse blocking IGBT concerning this invention. It is sectional drawing (the 8) which shows the manufacturing method of reverse blocking IGBT concerning this invention. It is sectional drawing (the 9) which shows the manufacturing method of reverse blocking IGBT concerning this invention. It is sectional drawing (the 10) which shows the manufacturing method of reverse blocking IGBT concerning this invention. It is sectional drawing (the 11) which shows the manufacturing method of reverse blocking IGBT concerning this invention. It is sectional drawing (the 12) which shows the manufacturing method of reverse blocking IGBT concerning this invention. It is a graph which shows the effect of this invention. It is a graph which shows the effect of this invention. It is sectional drawing of the conventional forward direction IGBT. It is sectional drawing of reverse blocking IGBT obtained by this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, Semiconductor substrate 1a Polyback seal 2, Separation layer 3a, p well layer 3b, channel layer 3c, second p ⁺ layer 4, n emitter layer 5 gate oxide film 6 gate electrode 7 emitter electrode 8 collector layer 8-1, Collector electrode.

Claims (5)

a first step of introducing the p-type impurity to n-type first major surface or found before Symbol semiconductor substrate an oxide film of the semiconductor substrate as a mask,
After the first step , a high-temperature heat treatment is performed in an oxygen atmosphere to form a p-type separation layer having a required depth. Along with this, a crystal defect caused by high concentration oxygen occurs in the semiconductor substrate. And the process of
After the second step, a high-concentration phosphorus- doped layer is formed on the first main surface and the second main surface by high-temperature heat treatment using a gas containing phosphorus element, and is formed on the second main surface. A third step in which the lattice mismatch caused by the phosphorus-doped layer causes dislocation and becomes a gettering source;
Later than the third step, the line Ukoto ion implantation argon second principal, a fourth step of forming a crystal strain layer on the second main surface serves as a gettering source,
After the fourth step , a required semiconductor functional region is formed on the first main surface by a step including heat treatment at 1000 ° C. or higher, and at the same time, a crystal caused by the high concentration oxygen from the operation region to the gettering source A fifth step of capturing defects and reducing the density of crystal defects in the operating region;
Later than the fifth step, a sixth step the separation layer to the thickness reduced from the second main surface side to expose with removing the phosphorus-doped layer of the second main surface side,
A method for manufacturing a semiconductor device, comprising: The third step includes forming a gate insulating film and a polycrystalline silicon region in a predetermined region surrounded by the isolation layer on the first main surface, and then forming both on the first main surface and the second main surface. the rows Ukoto phosphorus-doped, the polysilicon region of the first main surface as well as the phosphorus-doped conductive layer, which also form the phosphorus-doped layer on said second major surface,
In the fifth step , a required MOS structure is formed on the first main surface by the step .
The method of manufacturing a semiconductor device according to claim 1. The first step is a method of manufacturing a semiconductor device according to claim 2, wherein forming said isolation layer on the semiconductor substrate having the a second main polysilicon back seal is formed. 4. The method of manufacturing a semiconductor device according to claim 1, wherein phosphorus oxychloride or phosphine is used as a material containing the phosphorus element used for forming the phosphorus doped layer. 5. The semiconductor device manufacturing method according to claim 1, wherein the semiconductor device is a reverse blocking IGBT.

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