JP5179703B2 - Method of manufacturing reverse blocking insulated gate bipolar transistor - Google Patents

Description

  The present invention relates to an insulated gate bipolar transistor (IGBT) used in a power converter and the like. More particularly, the present invention relates to a bidirectional IGBT device or a reverse blocking IGBT device having bidirectional withstand voltage characteristics.

An IGBT (insulated gate bipolar transistor) having a conventional planar type pn junction structure as shown in FIG. 4 is used under a direct current power source in an inverter circuit and a chopper circuit which are main applications. There was no problem as long as the withstand voltage could be secured, and it was made without considering the reverse withstand voltage from the element design stage.
However, recently, in a semiconductor power conversion device, a bi-directional switching element is used in a matrix converter such as a direct link type conversion circuit to perform AC (alternating current) / AC conversion, AC / DC (direct current) conversion, and DC / AC conversion. Research has been done to reduce the size, weight, efficiency, speed, and cost of the circuit. Therefore, in order to obtain the bidirectional switching element by connecting the IGBTs in reverse parallel, an IGBT having a reverse breakdown voltage has been demanded.

As described above, the conventional IGBT does not have an element design and manufacturing method for ensuring effective reverse blocking capability. Therefore, in order to ensure reverse breakdown voltage, a diode is connected in series and bidirectional switching is performed. It is necessary to configure the element. As a result, since the diodes are included in series, the generated loss is increased and the conversion efficiency of the conversion device is reduced. Furthermore, the number of elements increases, and it is difficult to reduce the size, weight, and cost of the conversion device. These improvements have the significance of the existence of IGBTs with reverse blocking ability.
FIG. 4 is a cross-sectional view of a main part of a conventional IGBT that does not substantially have the above-described reverse breakdown voltage. The IGBT will be described. A plurality of p base regions 102 are selectively formed on the first main surface 115 of the high resistivity n-type semiconductor substrate, and a p collector layer 103 is formed on the second main surface 116 on the back surface side. Yes. A region sandwiched between the p base region 102 and the p collector layer 103 in the thickness direction of the semiconductor substrate is an n base region 101 which is also a semiconductor substrate. An n emitter region 104 is selectively formed in a surface layer in the p base region 102 in the active region 114 indicated by an arrow. A breakdown voltage structure 113 such as a guard ring structure is formed on the surface of the planar pn junction indicated by an arrow outside the active region 114 to ensure the forward blocking breakdown voltage of the IGBT. A dotted line 118 indicates the n base side depletion layer when a forward voltage is applied. The breakdown voltage structure 113 is outside the active region 114 in the first main surface, and a plurality of p regions 111, oxide films 112, and a plurality of metal films 124 formed in a ring shape on the surface layer of the n-type semiconductor substrate. Etc. are combined. Gate electrodes 106 are respectively formed on the surface of the p base region 102 sandwiched between the n emitter region 104 and the n base region 101 and the surface of the n base region 101 between the plurality of p base regions 102 via the gate oxide film 105. It is formed. The surface of the n emitter region 104 is covered with an emitter electrode 108, and the surface of the p collector layer 103 is covered with a collector electrode 109. An insulating film 107 is provided between the emitter electrode 108 and the gate electrode 106.

Since the above-mentioned conventional IGBT is manufactured on the premise that it is not reverse-biased, the vicinity of the collector junction surface indicated by the symbol A where the electric field tends to concentrate when a reverse bias is applied with the emitter as the ground potential and the collector as the negative potential No processing is performed in the cutting portion 125 with mechanical cutting distortion due to dicing or the like, and a sufficient reverse breakdown voltage cannot be obtained.
Further, in the case of a separation layer type reverse blocking IGBT 300 in which the separation layer 120 as shown in FIG. 5 is formed only by diffusion from the surface (other functional regions are the same as those of the IGBT shown in FIG. Reference numeral 117 denotes a reverse bias depletion layer added to the pn junction between the p collector layer 103 and the n base layer 101. An NPT (Non Punch Through) wafer (100 μm) can be used. . In this case, by reducing the collector layer 103 and controlling the impurity concentration to be low, the trade-off relationship between the on-voltage characteristic and the turn-off loss, which has been a problem in the past, can be eliminated and both can be reduced.

  However, with respect to the formation of the separation layer, even a thin NPT wafer having a substrate thickness of about 100 μm as in the reverse blocking IGBT 300 shown in FIG. 5 is about 120 μm (reverse blocking breakdown voltage 600 V) due to boron diffusion from the surface. In order to make a separation layer 120 having a depth of 100 μm in the case of a device wafer, the separation layer width (in the direction parallel to the surface) starts thermal diffusion from an initial region of 50 μm on one side (per one side) In the lateral direction (direction parallel to the surface), the initial region is expanded by about 100 μm, so that the separation layer per chip is as large as 150 μm on one side. When both sides are combined, it becomes 300 μm. This greatly reduces the area of the active region and increases the chip area for the same current capacity, which not only results in poor chip area utilization efficiency but also is disadvantageous in terms of cost. When the thickness of the wafer (substrate) is 150 μm, the separation region 120 further expands in the horizontal direction, so that the utilization efficiency of the chip area is further deteriorated and the diffusion time becomes extremely long, which is not practical. (See Patent Documents 1 and 2 below).

Further, in FIG. 5, when manufacturing a semiconductor device using an n-type semiconductor substrate as a drift layer, the separation layer is formed by selectively applying a boron source to the substrate surface and diffusing it to a predetermined depth for a long time. Can be formed. In this case, for example, to perform diffusion at a depth of 200 μm, it is necessary to perform heat treatment at 1300 ° C. for 200 hours or more. Further, the p collector layer 103 on the back surface is formed by implanting p-type ions and annealing after the back surface is scraped to a depth at which the separation layer appears after completion of the surface process. This p collector layer is a case where a low-concentration n-type epitaxial layer is grown on a high-concentration p-type substrate to form a drift layer. It can also be realized by diffusing from the surface of the epitaxial layer to the position of the p-type substrate.
JP 2001-185727 A JP 2002-319676 A

As described above, in the case of the separation layer type reverse blocking IGBT in which the separation layer is formed only by diffusion from the surface, there is a problem that not only the use efficiency of the chip area is bad but also the cost is disadvantageous.
Further, boron diffusion for forming the p-type region needs to be performed in an atmosphere containing oxygen gas in order to suppress substrate surface roughness. Therefore, a high concentration of oxygen ions is taken into the substrate during boron diffusion. The incorporated oxygen is converted into a donor by a heat treatment at 400 ° C. to 500 ° C.
In the IGBT manufacturing process, since a large number of heat treatments are performed, the oxygen taken in by the thermal history is converted into a donor, and the profile of the drift layer changes greatly. In addition, when a p-collector layer is formed by performing ion implantation and heat treatment on the back surface after completion of the surface process after manufacturing using an n-type semiconductor substrate, the surface structure such as an electrode is not damaged at 500 ° C. or higher. It is difficult to perform annealing at. Therefore, in order to avoid significant donor formation, the back surface annealing temperature must be suppressed to 400 ° C. or lower. However, in such low temperature annealing, the implanted boron is not sufficiently activated, and crystal defects due to the implantation are not sufficiently repaired, so that a large leakage current is generated when a reverse bias is applied. In addition, even with low-temperature annealing at 400 ° C or lower, some of the oxygen that is incorporated becomes donors and the profile of the drift layer changes, so it is necessary to design this device while taking this phenomenon into account. There is difficulty in device design. For this reason, forming a separation layer so that a high concentration of oxygen is not taken into the drift layer is a major problem in the reverse blocking IGBT manufacturing technology.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a problem per chip which is a problem even in the case of a thin wafer (semiconductor substrate) that can avoid a trade-off between on-voltage characteristics and turn-off loss. It is an object of the present invention to provide a method for manufacturing a reverse blocking insulated gate bipolar transistor that can reduce the occupied area ratio of the isolation region and can reduce the influence of oxygen donor formation.

According to the first aspect of the present invention, the object is to provide a base region of the second conductivity type selectively formed on the surface of the drift layer of the first conductivity type, and a surface of the base region. A first conductivity type emitter region selectively formed; a gate electrode formed on the base region sandwiched between the drift layer and the emitter region via a gate insulating film; and a back surface of the drift layer A second conductivity type collector region formed so as to surround the periphery of the base region from side to side,
Surface insulating film layer of said drift layer, a resist was formed in this order, and a resist is thicker than the insulating film, wherein the surrounding region where the base region is formed so as to surround taken from the side side Forming an insulating film and a mask of the resist, and using the mask, forming a lattice-like trench having a width of 10 to 20 μm and a depth of 100 to 200 μm;
Forming an isolation layer to be a part of said impurity concentration to form an epitaxial layer of a second conductivity type 1 × 10 ¹⁷ cm ^-3 or more into the trench collector region, said epitaxial a back surface of the drift layer Cutting until reaching the layer, and forming a second conductivity type collector region on the back surface of the scraped drift layer by ion implantation;
Is achieved.

  According to the present invention, even in the case of a thin wafer (semiconductor substrate) that can avoid the trade-off between the on-voltage characteristics and the turn-off loss, it is possible to reduce the occupation area ratio of the separation region per chip, which is a problem. It is possible to provide a method of manufacturing a reverse blocking insulated gate bipolar transistor that can reduce the influence due to donor formation.

1 to 3 are each a manufacturing process diagram showing a manufacturing method of a reverse blocking insulated gate bipolar transistor (hereinafter abbreviated as IGBT) according to the present invention by a cross section of a main part of a silicon substrate. As long as the gist of the present invention is not exceeded, the present invention is not limited to the description of the examples described below. The above-described problem can be solved by forming a trench groove from the surface of the semiconductor substrate and growing a p-type epitaxial layer in the trench groove. However, when an oxide film (SiO ₂ ) is used as a mask material for forming the trench groove, the etching selectivity between the oxide film and silicon is generally about 50 even when optimized, and a trench groove having a depth of 200 μm is formed. The thickness of the oxide film required for the formation is about 5.0 μm in consideration of the margin. However, it is very difficult to form an oxide film having such a thickness, and when an IGBT is actually manufactured, the cost of forming the oxide film increases. Therefore, a resist is used as a mask material so that a 200 μm trench can be etched without increasing the thickness of the oxide film. The resist can be easily thickened. Since the width of the opening of the separation layer is 10 to 20 μm and there is no need for fine processing, the accuracy of patterning does not drop even if the resist is thickened.

An embodiment of a method for manufacturing a reverse blocking IGBT according to the present invention will be described in detail with reference to FIGS. 1 and 2 (each a sectional view). FIG. 1 and FIG. 2 are manufacturing process diagrams showing a method of manufacturing an IGBT by a cross section of a main part of a silicon substrate. As long as the gist of the present invention is not exceeded, the present invention is not limited to the description of the examples described below. This reverse blocking IGBT is a reverse blocking IGBT having a withstand voltage of 600V. First, an FZ silicon substrate (wafer) 1 having a thickness of 525 μm and an n conductivity type impurity concentration of 1.5 × 10 ¹⁴ cm ⁻³ (resistivity of about 30 Ωcm) is prepared (FIG. 1A). Then, an initial oxide film 12 having a thickness of 1.0 μm is formed on the surface of the FZ silicon substrate 1 (which will be a drift layer), and a resist 13 having a thickness of 10 μm is applied. Next, exposure and development are performed, and patterning is performed to form a window opening in a portion corresponding to the separation region on the outer periphery of the chip, thereby forming a ring-shaped or grid-shaped opening having a width of 10 μm (FIG. 1B). ). Subsequently, trench etching is performed using the resist on the patterned oxide film as a mask without removing the resist 13. The trench groove 23 having a width of 10 μm and a depth of 100 μm is etched in the opening by using the Bosch process method with SF ₆ as an etching gas and a C ₂ F ₈ gas flowing to form a sidewall protective film (FIG. 1 (c)). By performing such etching, the selectivity ratio between the resist and silicon is about 50. For example, when manufacturing a reverse blocking IGBT having a withstand voltage of 1200 V with a drift layer resistivity of 60 to 80 Ωcm, the trench depth is 180. In the case of the etching of 200 μm), the etching can be performed with a sufficient margin using the resist as a mask. Then, after completion of the trench etching, the resist 13 is removed.

Next, a high-concentration p-type epitaxial layer 3 having an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or higher is grown in the trench opening until the trench groove is completely filled. At this time, the epitaxial layer 3 does not grow on the oxide film 12 due to the selectivity of the epitaxial growth (FIG. 1D).
Next, as shown in FIG. 1E, the insulating film 12 is removed and the surface is flattened. Thereafter, as shown in FIG. 1F, ion implantation is performed in the same process as the planar IGBT. And the heat treatment, an active portion 4 having a p-type base region, a gate oxide film, a gate electrode, an n + -type emitter region, an emitter electrode and the like is formed in a region inside the high-concentration p-type epitaxial layer 3 to complete the surface structure. . The structure of the active part 4 may be either a planar type or a trench type. The cell shape may be any of a polygonal shape, a stripe shape, or a lattice shape. Further, although not shown, a breakdown voltage structure portion is provided between the isolation layer and the active portion 4. In the process of forming the active portion 4, a plurality of heat treatments are performed when forming each component. Then, the high-concentration p-type epitaxial layer 3 is also annealed by the heat treatment, causing thermal diffusion of the p-type impurities, and the separation layer 3a as shown in FIG. 1 (f) is formed. Since the heat treatment at this time is only performed for several hours at a total temperature of about 1100 ° C., the high-temperature heat treatment time is greatly shortened compared to the conventional method of thermally diffusing from the substrate surface over a long time, and the low concentration n-type silicon substrate Almost no oxygen is taken into 1.

After the formation of the active portion 4 and the separation layer 3a, as shown by a dotted line in FIG. 2A, the back surface of the FZ silicon substrate 1 is shaved until it reaches the separation layer 3a (FIG. 2B).
Then, as shown in FIG. 2 (c), high-concentration p-type impurities are ion-implanted into the back surface of the FZ silicon substrate 1 so that the surface structure such as the active portion 4 and the electrode is not damaged at 500 ° C. or lower. Annealing is performed to form the collector layer 5 which is the back surface high concentration p layer.
In order to sufficiently activate the p-type impurity ion-implanted into the back surface of the FZ silicon substrate 1 and repair crystal defects caused by the ion implantation, it is necessary to anneal at as high a temperature as possible. In the conventional separation layer forming method, since a high concentration of oxygen has been taken into the substrate, the annealing temperature has been limited to less than 400 ° C. in order to prevent the taken-in oxygen from becoming a donor. On the other hand, in Example 1, since almost no oxygen is taken into the FZ silicon substrate 1, it is not necessary to consider oxygen donor formation, and it is sufficient to consider only that the surface structure is not damaged. Therefore, annealing at 400 ° C. or higher and 500 ° C. or lower becomes possible.

In addition, since the trench formation and epitaxial growth described above can be performed up to an aspect ratio as high as about 1:10, coupled with the shortening of the high-temperature heat treatment time, the width of the isolation layer 3a region can be reduced compared with the conventional isolation layer forming method. Directional spread can be greatly reduced.
After the annealing of the p-type impurity ion-implanted on the back surface, dicing is performed at the position of each separation layer 3a (the position of the chain line in FIG. 2D) to divide into individual reverse blocking IGBTs.
In the IGBT forming method of the first embodiment, the upper end of the trench groove 23 is closed first during the epitaxial growth for filling the deep trench groove 23 having a high aspect ratio with the high-concentration p-type epitaxial layer 3. It should be noted that cavities can remain. Such a case can be dealt with by increasing the growth rate from the bottom of the trench 23. Further, as proposed in, for example, Japanese Patent Application Laid-Open No. 2003-229569, it is possible to use a method in which epitaxial growth is performed so that cavities do not remain, and the remaining cavities are closed by performing hydrogen reduction atmosphere annealing. .
[Reference Example 1]

Next, Reference Example 1 will be described.
FIG. 3 is a schematic explanatory diagram of the reverse blocking IGBT formation flow of Reference Example 1 .
As shown to (a), what made the low concentration n layer 21 used as a drift layer epitaxially grow on the high concentration p-type silicon substrate 20 is prepared. Then, as shown in (b), a 1.0 μm thick oxide film 22 and a 10 μm thick resist 24 serving as a mask for trench formation and epitaxial growth are formed in this order on the surface of the low concentration n layer 21. A window opening portion is formed at a location to be the separation layer.
Next, in the same manner as in Example 1 above, as shown in (c), the low-concentration n layer 21 in the window opening part is etched until the high-concentration p-type silicon substrate 20 is reached without peeling off the resist 24. A trench groove 23a is formed. After the trench etching is completed, the resist 24 is removed. Thereafter, as shown in (d), the high-concentration p-type epitaxial layer 25 is grown until the trench groove 23a is completely filled. Then, as shown in (e), the oxide film 22 is removed to flatten the surface. To do.

Finally, a planar or trench type active portion 26 is formed by ion implantation and heat treatment, as shown in FIG. By the heat treatment in the process of forming the active portion 26, the high-concentration p-type epitaxial layer 25 is annealed, and the separation layer 25a connected to the high-concentration p-type silicon substrate 20 as the collector layer is formed.
As described in the first embodiment, since the heat treatment in the formation process of the active portion 26 is only performed at a total temperature of about 1100 ° C. for several hours, the high temperature heat treatment time is significantly shortened compared to the conventional case, and the low concentration n High concentration of oxygen is not taken into the layer 21. In addition, the shortening of the high-temperature heat treatment time greatly reduces the lateral spread of the separation layer 25a, so that the edge region per element can be reduced.
As described above, by shortening the high-temperature heat treatment time in the formation of the reverse blocking IGBT, it is possible to reduce the oxygen uptake amount that can cause donor formation in the drift layer and to suppress the lateral extension of the separation layer. Thus, the edge area per element can be reduced. Thereby, it is possible to form a small and high quality reverse blocking IGBT.

(A)-(f) Process sectional drawing which shows the manufacturing method of the reverse blocking insulated gate bipolar transistor concerning this invention (A)-(d) is process sectional drawing following FIG.1 (f). (A)-(f) Process sectional drawing which shows the other manufacturing method of the reverse blocking type insulated gate bipolar transistor concerning this invention Schematic sectional view of a conventional insulated gate bipolar transistor Schematic cross section of a conventional reverse blocking insulated gate bipolar transistor

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 FZ silicon substrate 3, 25 High concentration p-type epitaxial layer 3a, 25a Separation layer 4, 26 Active part 12, 22 Oxide film 13, 24 Resist 20 High concentration p type silicon substrate 21 Low concentration n layer 23, 23a Trench groove 31 32 isolation region 35 polysilicon 102 p base region
103 p + collector layer 104 n + emitter region 105 gate oxide film
106 Gate electrode 108 Emitter electrode
109 Collector electrode

Claims (1)

A second conductivity type base region selectively formed on the surface of the first conductivity type drift layer; a first conductivity type emitter region selectively formed on the surface of the base region; and the drift layer; A gate electrode is formed on the base region sandwiched between the emitter regions via a gate insulating film, and is formed so as to surround the periphery of the base region from the back surface to the side of the drift layer. In a method for manufacturing a semiconductor device having a collector region of a second conductivity type,
Surface insulating film layer of said drift layer, a resist was formed in this order, and a resist is thicker than the insulating film, wherein the surrounding region where the base region is formed so as to surround taken from the side side Forming an insulating film and a mask of the resist, and using the mask, forming a lattice-like trench having a width of 10 to 20 μm and a depth of 100 to 200 μm;
Forming an isolation layer to be a part of said impurity concentration to form an epitaxial layer of a second conductivity type 1 × 10 ¹⁷ cm ^-3 or more into the trench collector region, said epitaxial a back surface of the drift layer Cutting until reaching the layer, and forming a second conductivity type collector region on the back surface of the scraped drift layer by ion implantation;
A method of manufacturing a reverse blocking insulated gate bipolar transistor characterized by comprising:

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