JP2008071916A - Testing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a testing method capable of protecting a back electrode against damage caused by the pressing force of a probe needle when a wafer is checked. <P>SOLUTION: The sum of the pressing forces of probe needles 42 applied to the surface electrode of a chip is limited to 50 gf or below when a wafer is checked. In this way, a scratch 36, made on a collector electrode 35 by a foreign object 43 etc. located on a wafer check stage 41, is prevented from penetrating through the collector electrode 35. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a test method for a semiconductor device, and more particularly to a test method for a power semiconductor device used in a power conversion device or the like.

  In recent years, field stop type insulated gate bipolar transistors (hereinafter referred to as FS type IGBTs) are becoming mainstream. For example, in the case of the n-channel type, the FS-type IGBT has a high-concentration n-type buffer layer between a low-concentration n-type drift layer and a high-concentration p-type collector layer on the back surface. Even if it takes, it has a structure that is unlikely to cause breakdown. Therefore, the FS type IGBT has characteristics of low loss and high breakdown voltage.

  As a method for manufacturing the FS type IGBT, there is a method using an epitaxial wafer. An epitaxial wafer is a wafer obtained by epitaxially growing a semiconductor layer serving as a buffer layer and a drift layer on a semiconductor substrate serving as a collector layer. As another method, there is a method in which a wafer is cut out from an FZ crystal produced by a floating zone (FZ) method. In this manufacturing method, after the surface element structure is formed on the FZ wafer, the back surface of the wafer is ground and shaved, and ion implantation and heat treatment are performed on the shaved surface to form a buffer layer and a collector layer. Then, a collector electrode is formed by vapor deposition or sputtering. In the method using the FZ wafer, the total dose of the collector layer can be easily controlled, so that there is an advantage that an IGBT with a small switching loss can be manufactured.

  On the other hand, an IGBT having a reverse breakdown voltage (hereinafter referred to as a reverse blocking IGBT) is required in the market as an IGBT suitable for applications such as a matrix converter. For example, an n-channel reverse blocking IGBT has a configuration in which a high-concentration p-type isolation region is formed on the side of a normal n-channel IGBT and this p-type isolation region is connected to a collector layer. When manufacturing a reverse blocking IGBT using an FZ wafer, first, an isolation region is formed by selectively diffusing impurities. Thereafter, as in the case of the FS type IGBT, formation of the surface element structure, grinding of the back surface of the wafer, ion implantation to the back surface of the wafer and activation heat treatment are sequentially performed, and a collector electrode is formed by vapor deposition or sputtering.

  In the FS type IGBT, a strong electric field is applied to the buffer layer when a forward bias is applied. Further, in the reverse blocking IGBT, a strong electric field is applied to the PN junction on the back side when a reverse bias is applied. However, in these semiconductor devices, since the PN junction depth on the back side is as thin as 0.3 μm, if a slight scratch is made on the surface on the back side, punch-through easily occurs and the original function of the semiconductor device is impaired. End up. On the other hand, when a metal such as Al is deposited or sputtered as the collector electrode, the metal protruding into the silicon at the interface between the silicon (Si) serving as the collector layer 3 and the metal electrode serving as the collector electrode 4 as shown in FIG. The spike 5 is likely to occur.

  In the FS type IGBT, when the spike 5 reaches the buffer layer 2, a leakage current failure is caused. In the reverse blocking IGBT, when the spike 5 reaches the PN junction 6 on the back surface side, reverse breakdown voltage failure or reverse leakage current failure is caused. Therefore, when manufacturing these semiconductor devices, it is important to prevent defects from penetrating the back electrode so as to reduce defects. In FIG. 6, reference numeral 1 denotes a drift layer.

  In general, in the manufacturing process of a semiconductor device, after completion of an element structure, before dicing, a wafer is placed on a wafer check stage with a back electrode facing down, and a probe is brought into contact with the front electrode to make electrical characteristics. A wafer check is performed to measure. During the wafer check, there may be a protrusion on the back surface of the wafer of several tens of micrometers, a protrusion on the wafer check stage, or a foreign matter on the wafer check stage.

  When performing a wafer check of a large current chip such as a normal IGBT, it is necessary to measure characteristics such as an on-voltage, and therefore a large current is applied by applying a multi-pin probe to the chip. Therefore, the total pressing force of the probe is several hundred gf to several kgf. However, in the above-described FS type IGBT and reverse blocking type IGBT, if the back electrode is scratched, a defect is easily generated. Therefore, a defect is likely to occur at the time of wafer check or assembly.

  When the inventors conducted an experiment with an FS type IGBT or reverse blocking type IGBT, it was confirmed that the back electrode could be damaged by an excessive pressing force on the chip, and that a defect occurred due to that. Further, it was found that even a chip that does not cause a defect may be damaged and may be defective in a subsequent test. The pressing force per probe having a diameter of 300 μm is approximately 25 gf although it depends on the structure of the probe card. In general, a current corresponding to 2.5 A flows per probe.

  Further, since four probes are connected to the gate and the emitter and the contact between the probe and the electrode pad is confirmed, a force of 100 gf is applied to the chip by this alone. However, if the probe is made thinner, it is reduced to about 50 gf. In the case of a 100A element, a total of 40 probes are required, so a force of about 1 kgf is applied to the chip. Therefore, it was confirmed that when the wafer check stage has a protrusion, a defect occurs in the chip at a position corresponding to the protrusion. It was also confirmed that even a slight scratch that does not become defective with the conventional pressing force may cause a defect in the subsequent assembly process.

  Recently, nanoimprint lithography has been proposed as a technique to replace photolithography, in which a hard mold having a concavo-convex pattern is pressed against a resist or a substrate to form a pattern by leaving an indentation. In this nanoimprint lithography, in order to perform uniform pressing, the entire surface of the mold pattern surface is pressurized by providing a flat plate of the same height on the part where the mold and the wafer do not face (outer peripheral part of the wafer), or to the mold It has been proposed to control the pressure so that the center of gravity of the pressure is located within the area where the mold and the wafer are actually facing each other (see, for example, Patent Document 1).

JP 2005-268675 A

  However, the method disclosed in Patent Document 1 is a technique for leaving an indentation by pressing the mold uniformly against the substrate, and has nothing to do with preventing the back electrode of the semiconductor device from being damaged. Therefore, the method disclosed in Patent Document 1 has a problem that it is impossible to prevent the back electrode from being damaged during wafer check.

  An object of the present invention is to provide a semiconductor device testing method capable of preventing the back electrode from being damaged at the time of wafer check in order to eliminate the above-mentioned problems caused by the prior art.

In order to solve the above-described problems and achieve the object, the present inventors have conducted extensive research. As a result, when the wafer is checked, if the force for pressing the probe against the front electrode of the chip is made smaller than before, the back electrode is damaged. It was found that it was difficult to stick and reproducibility was good. By further research, it was found that the yield rate and reproducibility are significantly improved if the total pressing force of all the probes pressed against the surface electrode of the chip is approximately 50 gf or less. Further, since the pressing force of the probe is proportional to the cross-sectional area of the probe, it has been found that if the total cross-sectional area of all the probes is 150,000 μm ² or less, a good wafer check can be performed.

  The present invention has been made on the basis of the above knowledge, and the invention of claim 1 is characterized in that a surface electrode is formed on the first main surface of the semiconductor wafer having the first main surface and the second main surface, and In a test method for a semiconductor device, in which a plurality of probes are brought into contact with the front surface electrode of a semiconductor device having a back electrode formed on the second main surface, the electrical characteristics of the semiconductor device are tested. The total force to be pressed against the surface electrode is 50 gf or less.

According to a second aspect of the present invention, a surface electrode is formed on the first main surface of a semiconductor wafer having a first main surface and a second main surface, and a back electrode is formed on the second main surface. In a test method of a semiconductor device in which a plurality of probes are brought into contact with the surface electrode of the manufactured semiconductor device to test the electrical characteristics of the semiconductor device, the total cross-sectional area of the probe is set to 150,000 μm ² or less. Features.

According to a third aspect of the present invention, a surface electrode is formed on the first main surface of a semiconductor wafer having a first main surface and a second main surface, and a back electrode is formed on the second main surface. In a test method of a semiconductor device in which a plurality of probes are brought into contact with the surface electrode of the semiconductor device, the electrical characteristics of the semiconductor device are tested, and the total force for pressing the probe against the surface electrode is 50 gf or less The total cross-sectional area of the probe is 150,000 μm ² or less.

  According to a fourth aspect of the invention, there is provided the semiconductor device according to any one of the first to third aspects, wherein the semiconductor device is electrically connected to the surface electrode in order from the first main surface side. A first conductivity type emitter region and a second conductivity type base region, a first conductivity type drift layer, and a second conductivity type electrically connected to the back electrode and surrounding the lower and side portions of the drift layer It is a reverse blocking insulated gate bipolar transistor having a collector region.

  The invention according to claim 5 is the invention according to any one of claims 1 to 3, wherein the semiconductor device is electrically connected to the surface electrode in order from the first main surface side. The first conductivity type emitter region and the second conductivity type base region, the first conductivity type drift layer, the first conductivity type buffer layer having a higher impurity concentration than the drift layer, and the back electrode are electrically connected. It is a field stop type insulated gate bipolar transistor having a second conductivity type collector region.

  According to the present invention, the probe is pressed against the front surface electrode of the chip with a force that does not damage the back surface electrode during the wafer check.

  According to the semiconductor device test method of the present invention, it is possible to prevent the back electrode from being damaged by the pressing force of the probe during wafer check.

  Exemplary embodiments of a semiconductor device testing method according to the present invention will be explained below in detail with reference to the accompanying drawings. Here, an example in which the method of the present invention is applied when an n-channel reverse blocking IGBT is manufactured using an FZ wafer will be described.

1 to 4 are cross-sectional views for explaining a method of manufacturing a reverse blocking IGBT. First, as shown in FIG. 1, a p-type isolation region 12 is formed by selectively thermally diffusing p-type ions from a low-concentration n ⁻ FZ wafer to be the drift layer 11. For example, when manufacturing an element having a rated voltage of 1200 V, p-type ions are diffused by about 200 μm.

  Next, as shown in FIG. 2, a p-type base region 13, n is formed on the surface side of the region surrounded by the isolation region 12 by selective ion implantation, heat treatment (annealing) and deposition of an insulating layer. A surface-side element structure portion is formed which includes a type emitter region 14, a gate oxide film 15, a gate electrode 16, an interlayer insulating film 17, an emitter electrode 18 and an insulating protective film (not shown). Next, as shown by a dotted line in FIG. 2, the back surface of the wafer is ground by back grinding or the like until the separation region 12 appears.

  Next, as shown in FIG. 3, p-type ions are implanted from the back surface of the wafer and heat treatment (annealing) is performed to form a p-type collector layer 19 on the back surface side of the wafer. By connecting the collector layer 19 and the isolation region 12, a collector region surrounding the lower and side portions of the drift layer 11 is formed. Thereafter, an aluminum film 20 having a thickness of, for example, 0.6 μm is formed on the surface of the collector layer 19 by vapor deposition or sputtering as a first conductive film of a collector electrode (back electrode) made of a multilayer film. Subsequently, as shown in FIG. 4, a plurality of metal films 21 such as titanium, nickel and gold are formed by vapor deposition or sputtering to form a collector electrode 22.

After the device fabrication is completed as described above, the wafer is set on the flow bar and a wafer check is performed. At that time, the total pressing force of all the probes is set to 50 gf or less. Alternatively, the total cross-sectional area of all the probes is set to 150,000 μm ² or less. The pressing force of the probe is proportional to the square of the probe diameter and the pressing amount (distortion amount), and inversely proportional to the spring length. Further, the total pressing force increases in proportion to the number of probes. Therefore, in the embodiment, four probes having a diameter of 130 μm (pressing amount 150 μm) are used, a wafer check is performed with the total pressing force being 20 gf, and tests such as withstand voltage, leakage current, threshold voltage Vth and gate shock are performed. Do.

  By doing in this way, the mechanical defect was reduced compared with the case where a wafer check is performed on the conventional conditions. In the conventional wafer check, 40 probes having a diameter of 300 μm (pressing amount: 200 μm) were used, and the total pressing force was about 1 kg. Finally, dicing is performed to divide into a plurality of chips.

  FIG. 5 is a sectional view showing an outline of a wafer check to which the test method according to the present invention is applied. In FIG. 5, reference numeral 31 denotes a wafer after device fabrication is completed. For example, an FS IGBT having a drift layer 32, a buffer layer 33, a collector layer 34, and a collector electrode 35 is fabricated on the wafer 31 from the top. Has been. Reference numeral 41 denotes a wafer check stage, and reference numeral 42 denotes a probe. The total pressing force of the probe 42 against the surface electrode (not shown) is 50 gf or less. In this case, even if there is a foreign matter 43 or the like on the wafer check stage 41 and the collector electrode 35 is damaged due to this, the scratch 36 does not penetrate the collector electrode 35.

  As described above, according to the embodiment, the number and the diameter of the probes to be pressed against the front surface electrode of the chip are reduced and the total pressing force is reduced. Therefore, it is possible to prevent a defect from occurring during the wafer check. Conventionally, a back surface electrode has a small flaw during wafer check, which causes a defect in a later assembly process. The occurrence of such a defect can be reduced. Furthermore, according to the embodiment, it is possible to suppress the leakage current failure of the FS-type IGBT and the reverse breakdown voltage failure or reverse leakage current failure of the reverse blocking IGBT, which are caused by the spiking of the back surface metal electrode.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the numerical values described in the embodiments are examples, and the present invention is not limited to these values. In the embodiment, the first conductivity type is n-type and the second conductivity type is p-type, and vice versa.

  As described above, the method for testing a semiconductor device according to the present invention is useful for testing a power semiconductor device used in a power conversion device or the like, and is particularly suitable for testing a reverse blocking type or field stop type IGBT. .

It is sectional drawing explaining the manufacturing method of reverse blocking IGBT. It is sectional drawing explaining the manufacturing method of reverse blocking IGBT. It is sectional drawing explaining the manufacturing method of reverse blocking IGBT. It is sectional drawing explaining the manufacturing method of reverse blocking IGBT. It is sectional drawing which shows the outline of the wafer check to which the test method concerning this invention is applied. It is sectional drawing explaining the spike extended in a silicon | silicone from a metal electrode.

Explanation of symbols

11, 32 Drift layer 12 Separation region 13 Base region 14 Emitter region 18 Emitter electrode 19, 34 Collector layer 22 Collector electrode 31 Wafer 33 Buffer layer 42 Probe

Claims (5)

A surface electrode of the semiconductor wafer having a first main surface and a second main surface is formed on the first main surface, and a back electrode is formed on the second main surface. In a test method of a semiconductor device for testing electrical characteristics of the semiconductor device by contacting a plurality of probes,
A test method for a semiconductor device, characterized in that a total force for pressing the probe against the surface electrode is 50 gf or less. A surface electrode of the semiconductor wafer having a first main surface and a second main surface is formed on the first main surface, and a back electrode is formed on the second main surface. In a test method of a semiconductor device for testing electrical characteristics of the semiconductor device by contacting a plurality of probes,
A test method for a semiconductor device, wherein a total cross-sectional area of the probe is 150,000 μm ² or less. A surface electrode of the semiconductor wafer having a first main surface and a second main surface is formed on the first main surface, and a back electrode is formed on the second main surface. In a test method of a semiconductor device for testing electrical characteristics of the semiconductor device by contacting a plurality of probes,
A test method for a semiconductor device, characterized in that a total force for pressing the probe against the surface electrode is 50 gf or less, and a total cross-sectional area of the probe is 150,000 μm ² or less.   The semiconductor device includes, in order from the first main surface side, a first conductivity type emitter region and a second conductivity type base region electrically connected to the surface electrode, a first conductivity type drift layer, and the 2. A reverse-blocking insulated gate bipolar transistor having a second conductivity type collector region electrically connected to a back electrode and surrounding a lower portion and a side portion of the drift layer. 4. The method for testing a semiconductor device according to any one of 3 above.   The semiconductor device includes, in order from the first main surface side, a first conductivity type emitter region and a second conductivity type base region electrically connected to the surface electrode, a first conductivity type drift layer, and the drift A field stop type insulated gate bipolar transistor having a first conductivity type buffer layer having a higher impurity concentration than the layer and a second conductivity type collector region electrically connected to the back electrode. The method for testing a semiconductor device according to claim 1.

Images