JP5636751B2 - Reverse blocking insulated gate bipolar transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to an insulated gate bipolar transistor (IGBT) used in a power converter and the like. More particularly, it relates to improvements in reverse blocking IGBT devices.

  A conventional IGBT (insulated gate type bipolar transistor) having a planar pn junction structure is used under a DC power source in an inverter circuit or a chopper circuit, which is a main application, so there is no problem as long as a forward breakdown voltage can be secured. In spite of the presence of reverse withstand voltage bonding, the junction end surface of the reverse withstand voltage junction has been made exposed on the side surface of the chip cut portion without considering the reliability from the element design stage.

  Recently, however, some DC (direct current) / AC conversion circuits, such as AC (alternating current) / AC conversion circuits, current type DC / AC conversion circuits, and new three-level circuits, which are direct link type conversion circuits such as matrix converters, etc. Therefore, it has been studied to use a switching element having a reverse breakdown voltage to reduce the size, weight, efficiency, speed response, and cost of the circuit. For this reason, an IGBT having a highly reliable reverse withstand voltage has been demanded. In the reverse blocking IGBT, a reverse blocking capability equivalent to the forward blocking capability is required. In order to ensure this reverse blocking capability, a structure is intended to ensure reliability by extending the junction termination surface of the pn junction on the back collector side that maintains the reverse breakdown voltage to the surface of the semiconductor chip instead of the side surface of the chip cutting portion. There is a need to. Thus, the diffusion layer for changing the junction termination surface of the pn junction on the back collector side from the side surface to the surface is the separation layer.

  FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of forming the separation layer of a conventional reverse blocking IGBT in the order of manufacturing steps. FIG. 8 shows a method of forming a separation layer by coating diffusion. First, a thermal oxide film 2 having a thickness of about 2.5 μm is formed on a semiconductor substrate (hereinafter referred to as a wafer 1) as a dopant mask (FIG. 8A). Next, an opening 3 for forming a separation layer is formed in the thermal oxide film 2 by patterning and etching (FIG. 8B). Next, a boron source 4 is applied to the opening 3 and then heat treatment is performed at a high temperature for a long time in a diffusion furnace to form a p-type diffusion layer having a depth of about several hundred μm (FIG. 8C). )). Thereafter, although not shown in FIG. 8C, as shown in the cross-sectional view of FIG. 9, after forming the MOS gate structure 10, the emitter electrode 8a, and the like on the front surface side of the wafer 1, FIG. In c), the wafer 1 is thinned by grinding to the position reaching the p-type diffusion layer indicated by the broken line. 9 is formed on the ground surface, the p-type diffusion layer is connected to the p collector layer 7 and separated from the separation layer 5. Become. As a result, the junction termination surface of the collector junction moves to the surface side by the p-type diffusion layer. This p-type diffusion layer is hereinafter referred to as a separation layer 5. When the wafer 1 is cut into a lattice shape by the scribe line 6 located at the center of the separation layer 5, a reverse blocking IGBT chip 100 is formed.

  FIG. 10 is a cross-sectional view of a principal part of a semiconductor substrate showing different methods for forming the separation layer of the conventional reverse blocking IGBT in the order of manufacturing steps. This FIG. 10 shows a sidewall of a deep trench having a high aspect ratio formed in a semiconductor substrate in order to avoid the high temperature and long time heat treatment necessary for forming the p-type diffusion layer as described in FIG. In this method, a diffusion layer is formed to form a separation layer. First, a thick oxide film 2 of several μm is formed on the surface of the wafer 1 (FIG. 10A). Next, a trench 11 having a depth of about several hundred μm from the surface of the wafer 1 is formed by dry etching (FIG. 10B). Next, impurities are introduced into the sidewalls of the trench by vapor phase diffusion and thermal diffusion is performed to form the separation layer 12 (FIG. 10C). After filling the trench 11 with a reinforcing material (not shown) such as polysilicon or insulating film, after forming the MOS gate structure and metal electrode on the surface side having the same structure as in FIG. 9, the scribe line 6 shown in FIG. When the IGBT chip is cut out from the wafer 1 by dicing along the line, a reverse blocking IGBT 200 is completed.

  As described above, with respect to the method of digging the trench 11 on the surface of the wafer 1 and forming the isolation layer 12 on the sidewall thereof, the trench is formed so as to surround the active portion from the device surface to the lower pn junction, and the trench is formed on the sidewall of the trench. A method is known in which a diffusion layer is formed and a separation layer is formed by extending the end of a reverse blocking pn junction on the lower side of the device to the surface of the device (Patent Document 1). Similarly, there is a description of a method in which a trench reaching the lower reverse blocking pn junction from the device surface is formed, and a diffusion layer is formed on the side wall of the trench to obtain a device having reverse blocking capability (Patent Document 2). 3).

JP-A-2-22869 JP 2001-185727 A JP 2002-76017 A

  However, in the method of forming the separation layer reaching from the front surface to the back surface of the semiconductor substrate by thermal diffusion of impurities, when the semiconductor substrate is made thicker in order to obtain a high breakdown voltage semiconductor device, a thick oxide film is formed accordingly. In addition, high temperature and / or long time diffusion is required for impurity diffusion. When the high temperature and the diffusion time become long, there is a problem that the quality of parts and the like used for the semiconductor characteristics and the diffusion furnace is greatly adversely affected.

  The problem will be specifically described below. In the method of forming the reverse blocking IGBT separation layer shown in FIG. 8 described above, boron source (boron liquid diffusion source) is applied from the surface, boron is diffused by heat treatment, and a diffusion depth of about several hundred μm is separated. When forming the layer, the higher the withstand voltage, the higher the temperature and the longer the diffusion treatment is required. As a result, sag of quartz jigs such as quartz boards, quartz tubes (quartz tubes), quartz nozzles constituting the diffusion furnace, contamination from heaters, strength reduction due to devitrification of the quartz jigs, and the like occur. Furthermore, the formation of the separation layer by this coating diffusion method requires the formation of a thick mask oxide film. It is indispensable for a thick, high-quality mask oxide film to withstand long-time boron diffusion. As a method for obtaining a silicon oxide film having a high mask resistance, that is, a good quality, a thermal oxidation method is most preferable. However, in order to prevent boron from penetrating the mask oxide film in the diffusion treatment of the separation layer with boron at a high temperature for a long time (for example, 1500 ° C., 200 hours), a thermal oxide film having a thickness of about 2.5 μm or more is formed. There is a need. In order to form a thermal oxide film having a thickness of 2.5 μm, for example, an oxidation time required at an oxidation temperature of 1150 ° C. requires about 200 hours in dry (dry oxygen atmosphere) oxidation in which a good quality oxide film can be obtained. is there. Wet or pyrogenic oxidation, which requires slightly shorter oxidation time than dry oxidation, requires a long oxidation time of about 15 hours, although the film quality is somewhat inferior. Furthermore, during these oxidation processes, a large amount of oxygen is introduced into the silicon wafer, so that crystal defects such as oxygen precipitates and oxidation-induced stacking faults are introduced, and oxygen donors are generated. Detrimental effects such as deterioration of characteristics and reliability occur.

  Furthermore, even during thermal diffusion after boron source coating, interstitial oxygen is introduced into the wafer because diffusion treatment is usually performed in an oxidizing atmosphere at a high temperature for a long time. Even in this process, oxygen precipitates and oxygen donor phenomenon Then, crystal defects such as oxidation-induced stacking faults (OSF: Oxidation Induced Stacking Fault) and slip dislocations are introduced. In a pn junction formed on a wafer having these crystal defects introduced, the leakage current tends to increase. Further, it is known that the withstand voltage and reliability of an insulating film formed on a wafer by thermal oxidation are greatly deteriorated. In addition, oxygen taken in during diffusion becomes a donor, which causes a negative effect that the breakdown voltage is reduced. Further, in the method for forming the separation layer shown in FIG. 8, since the diffusion by boron proceeds substantially isotropically from the opening of the mask oxide film to the silicon bulk, when performing boron diffusion of 200 μm in the depth direction, Naturally, boron is diffused by 160 μm also in the lateral direction, which is an obstacle to reduction in device pitch and chip size.

There is also a problem in the case where the isolation layer is formed using the trench shown in FIG. In this method, the trench 11 having a high aspect ratio is formed by anisotropic dry etching, and boron is introduced into the side wall of the formed trench 11 to form the separation layer 12. Thereafter, the trench 11 is filled with a reinforcing material such as an insulating film. The separation layer forming method shown in FIG. 10 is more advantageous for the purpose of reducing the device pitch than the forming method shown in FIG. However, the time required for etching with a depth of about 200 μm requires a processing time of about 100 minutes per sheet when a typical dry etching apparatus is used. Problems such as increase are inevitable. In addition, when a deep trench is formed by dry etching, if a silicon oxide film (SiO ₂ ) is used as a mask, the selection ratio is as small as 50 or less, so a thick silicon oxide film of about several μm is required. As a result, there arises a problem of an increase in cost and a reduction in the yield rate due to the introduction of process-induced crystal defects such as oxidation-induced stacking faults and oxygen precipitates. Further, in the separation layer forming process using the deep trench 11 having a high aspect ratio by anisotropic dry etching, a chemical residue 13a, a resist residue 13b, etc. are generated in the trench 11 as shown in FIG. There is also a problem of causing adverse effects such as a decrease and a decrease in reliability.

Usually, when a dopant such as phosphorus or boron is introduced into the side wall of the trench 11, the side wall of the trench 11 is vertical. Therefore, the dopant is applied to the side wall of the trench 11 by implanting ions with the wafer 1 inclined. We are introducing. However, introduction of the dopant into the sidewall of the trench 11 having a high aspect ratio results in a decrease in effective dose (accordingly, an increase in implantation time), a decrease in effective projection range, a loss in dose due to the screen oxide film, and a decrease in implantation uniformity. This causes harmful effects. For this reason, as a method for introducing impurities into the trench 11 having a high aspect ratio, the wafer is contained in a gasified dopant zero atmosphere such as PH ₃ (phosphine) or B ₂ H ₆ (diborane) instead of ion implantation. Is used, but is inferior to ion implantation in terms of precise control of dose. In addition, when the trench 11 having a high aspect ratio is filled with an insulating film, a gap called a void is formed in the trench 11, and problems such as reliability occur. Moreover, in the manufacturing method of the said patent documents 1-3, it is assumed that the process which fills a trench with a reinforcing material, cut | disconnects a wafer with a scribe line, and makes it a semiconductor chip becomes high, and manufacturing cost becomes high. .

  The present invention has been made in view of the above points, and an object of the present invention is to perform trench formation without performing high-temperature and long-time diffusion that adversely affects semiconductor characteristics or a diffusion furnace. There is provided a method for manufacturing a reverse blocking insulated gate bipolar transistor having a diffusion separation layer having a depth reaching the back surface from the surface of a thick semiconductor substrate for high breakdown voltage without causing a reduction in yield rate due to such long-time process processing. That is.

  In order to achieve the object of the present invention, the present invention provides a second conductivity type through region penetrating the first conductivity type semiconductor substrate at a position surrounding the semiconductor device region of the first conductivity type semiconductor substrate. Forming from one main surface or both main surfaces, and mirror-processing the plurality of first conductive semiconductor substrates, aligning the positions of the second conductive through regions, and bonding them in a vacuum. A method for manufacturing a semiconductor device is provided.

Further, the present invention provides a second conductive type first through region penetrating the first conductive type semiconductor substrate at a position surrounding the semiconductor device region of the first conductive type semiconductor substrate. forming from the surface, a plurality of the first conductivity type semiconductor substrate mirror finished, before Symbol align the second conductivity type first through region bonded in a vacuum, the first through the second conductivity type Forming a second conductive type semiconductor layer connected to the separation layer on one main surface of the bonded semiconductor substrate, the bonded semiconductor substrate having a separation layer on which the regions are overlaid; and the bonding Forming a second conductive type second through region, an active portion, and a breakdown voltage structure on one main surface of the first conductive type semiconductor substrate different from the semiconductor substrate; and the first conductive type semiconductor substrate different from the bonded semiconductor substrate The other lord of each other A purpose can be achieved of the present invention also by a method of manufacturing a semiconductor device and a step of second conductivity type first through region and to align the second through region bonded in vacuum.

Further, the present invention provides a second conductive type first through region penetrating the first conductive type semiconductor substrate at a position surrounding the semiconductor device region of the first conductive type semiconductor substrate. A step of forming from the surface, a first conductive type semiconductor substrate in which a plurality of the second conductive type first through regions are formed, and a first conductive type semiconductor substrate in which the second conductive type first through regions are not formed, The first conductive semiconductor substrate in which a plurality of the second conductive type first through regions are formed and the first conductive semiconductor substrate in which the second conductive type first through regions are not formed are mirror-finished. A step of aligning the positions of the second conductive type first through regions and bonding them in a vacuum to form a bonded semiconductor substrate, and one surrounded by the second conductive type first through regions formed in the bonded semiconductor substrate Active part and pressure-resistant structure are formed on the main surface Forming a tapered groove having a bottom reaching the second conductive type first through region on the other main surface on the opposite side, and then forming a second conductive semiconductor layer on the other main surface. The object of the present invention can be achieved by employing a method for manufacturing a semiconductor device.

Furthermore, the present invention provides a second conductive type first through region penetrating the first conductive type semiconductor substrate at a position surrounding the semiconductor device region of the first conductive type semiconductor substrate. A step of forming from the main surface, a plurality of first conductive semiconductor substrates in which the second conductive type first through regions are formed, and a first conductive semiconductor substrate in which the second conductive type first through regions are not formed And a first conductive type semiconductor substrate in which a plurality of the second conductive type first through regions are formed and a first conductive type semiconductor substrate in which the second conductive type first through regions are not formed. process and, side not the second conductive type first transmembrane region of the semiconductor substrate mating Ri該貼is formed to the semiconductor substrate bonded by bonding in a vacuum by aligning the second conductivity type first through region The bottom of the main surface of the second conductivity type first After forming the tapered grooves reaching the passing region, and forming a second conductive type semiconductor layer, the other main surface of the semiconductor substrate mating Ri該貼, separately formed and then becomes a second conductivity type second through region and an active the other main surface of the first conductivity type semiconductor substrate having a part and the breakdown voltage structure in the one main surface, a step of bonding in a vacuum by aligning the second conductivity type first through region and the second through region The object of the present invention can be achieved by a method for manufacturing a semiconductor device having

  Moreover, it is preferable to set it as the manufacturing method of the semiconductor device whose thickness of a 1st conductivity type semiconductor substrate is 50 micrometers-200 micrometers. Furthermore, the semiconductor device manufacturing method, wherein the second conductivity type semiconductor layer is a p-type collector layer, and the active portion is composed of a MOS gate structure and an emitter electrode. The semiconductor device is a reverse blocking insulated gate bipolar transistor. Is desirable.

  According to the present invention, there is no high temperature and long time diffusion that adversely affects the semiconductor characteristics or the diffusion furnace, and there is no decrease in the yield rate due to long time process processing such as trench formation. It is possible to provide a method of manufacturing a reverse blocking insulated gate bipolar transistor including a diffusion separation layer having a depth reaching the back surface from the surface of a thick semiconductor substrate.

It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process which forms the isolation | separation layer concerning this invention by bonding by vacuum bonding in order. It is principal part sectional drawing of the reverse blocking IGBT which used the bonded wafer formed in the said FIG. 1 concerning this invention. It is principal part sectional drawing of the semiconductor substrate which shows a manufacturing process in order in the different manufacturing method which forms the isolation | separation layer concerning this invention by bonding by vacuum bonding. It is principal part sectional drawing of the reverse blocking IGBT which used the bonded wafer formed in the said FIG. 3 concerning this invention. FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate showing a manufacturing process in order of a manufacturing method for forming a separation layer according to the present invention by bonding by vacuum bonding, and a cross-sectional view of a main part of a reverse blocking IGBT using different bonded wafers. . FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate showing a manufacturing process in order of a manufacturing method for forming a separation layer according to the present invention by bonding by vacuum bonding, and a cross-sectional view of a main part of a reverse blocking IGBT using different bonded wafers. . FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate showing a manufacturing process in order of a manufacturing method for forming a separation layer according to the present invention by bonding by vacuum bonding, and a cross-sectional view of a main part of a reverse blocking IGBT using different bonded wafers. . It is principal part sectional drawing of the semiconductor substrate which shows in order the manufacturing process in the case of forming the said separation layer of the conventional reverse blocking IGBT by the application | coating diffusion method. It is principal part sectional drawing of reverse blocking IGBT formed with the conventional application | coating diffusion method. It is principal part sectional drawing of the semiconductor substrate which shows in order the manufacturing process at the time of forming the said isolation layer of the conventional reverse blocking IGBT by the trench method. It is principal part sectional drawing of the reverse blocking IGBT formed with the conventional trench method. It is sectional drawing of the trench part for demonstrating the problem at the time of forming the said isolation layer of the conventional reverse blocking IGBT by the trench method.

  Embodiments of a reverse blocking insulated gate bipolar transistor and a manufacturing method thereof according to the present invention will be described below in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.

Example 1 of the present invention will be described below. As shown in FIG. 1A, an opening 3 is provided in an oxide film 2 formed on the surface of a silicon wafer 1 (hereinafter simply referred to as a wafer) having a thickness of 100 μm. As shown by arrows in FIG. 1B, boron is introduced into the opening 3 by selective ion implantation at an acceleration voltage of 100 keV and a dose of 1 × 10 ¹⁵ cm ^{−2 using} the oxide film 2 as a mask. Boron may be introduced into the opening 3 of the oxide film 2 by applying a boron source 4 as shown in FIG. The wafer 1 into which boron has been introduced is subjected to a thermal diffusion treatment at 1300 ° C. for 100 hours, and boron is thermally diffused until it reaches the back surface of the wafer 1 as shown in FIG. Then, the oxide film 2 used as a mask is removed and both surfaces of the wafer 1 are made mirror surfaces (FIG. 1E). After placing this wafer 1 in a high vacuum chamber of about 10 ⁻⁶ Pa and cleaning the surface by argon sputtering, three wafers 1 having a thickness of 100 μm are stacked so that the separation layer 5 in which boron is diffused overlaps. Then, bonding is performed in a vacuum to obtain a bonded wafer 1a having a thickness of 300 μm in which the separation layer 5 is connected from the front to the back (FIG. 1 (f)). As described above, the bonding between the wafers 1 is performed by causing Ar ions to collide with the wafer 1 in a high vacuum, releasing the adsorbed surface, and bringing the wafer surfaces in which the surface Si atoms are activated into contact with each other. Is called. When the MOS gate structure 10, the emitter electrode 8a, the breakdown voltage structure 9 and the like are formed on one surface surrounded by the separation layer 5 of the bonded wafer 1a, and the collector layer 7 and the collector electrode 8b are formed on the back surface, FIG. The reverse blocking IGBT 300 shown in 2 (a) is completed. FIG. 2B shows a reverse blocking IGBT 400 in which the front and back surfaces of the bonded wafer 1a are reversed and the same surface structure as in FIG. 2A is formed.

A second embodiment of the present invention will be described below. Openings 3 using the oxide film 2 as a mask are formed on both sides of a wafer 1b having a thickness of 200 μm as shown in FIG. 3A, and boron is accelerated in the openings 3 on both sides as shown in FIG. 3B. Introduced by selective ion implantation at a voltage of 100 keV and a dose of 1 × 10 ¹⁵ cm ⁻² . Boron may be introduced into the opening 3 of the oxide film 2 by applying a boron source 4 as shown in FIG. A thermal diffusion treatment is performed at 1300 ° C. for 100 hours to thermally diffuse to a depth where the boron diffusion regions from both sides overlap at the center as shown in FIG. Then, the oxide film 2 is removed and both surfaces of the wafer 1 are made mirror surfaces. As shown in FIG. 3 (e), the surface of the wafer 1b having a high vacuum of about 10 ⁻⁶ Pa and cleaned by argon sputtering is overlapped in vacuum so that the boron diffused regions overlap. As shown in FIG. 3F, a single bonded wafer 1c having a thickness of 600 μm in which the separation layer 5a is connected from the front to the back as shown in FIG. Using the bonded wafer 1c bonded to the three sheets, the MOS gate structure 10, the emitter electrode 8a, the breakdown voltage structure 9 and the like are formed on any one surface, and the collector layer 7 and the collector electrode 8b are formed on the back surface. The reverse blocking IGBT 500 shown in FIG. 4 is completed. Compared with the manufacturing method of the reverse blocking IGBT according to the first embodiment, the second embodiment has an advantage that the risk of cracking during the wafer process is small because the thickness of the wafer before bonding is as thick as 200 μm.

  A third embodiment of the present invention will be described below. First, a wafer 1c in which a separation layer 5a is connected from the front to the back is manufactured by the method described in the first or second embodiment. As shown in FIG. 5A, boron ion implantation and annealing are performed on the entire surface of one surface to form a collector layer 7. The annealing can be performed by laser, but at this stage, since the metal electrode is not yet formed on the surface side, it can be heated to about 1000 ° C. by rapid thermal annealing using an infrared lamp. A collector electrode 8 b (shown in FIG. 5C) is formed on the surface of the collector layer 7. Next, a reverse side blocking IGBT surface side MOS gate structure as shown in FIG. 5B and the emitter electrode 8a and the separation layer 5a are formed on one surface by a conventional thermal diffusion method. A wafer 1d is prepared separately. By bonding the other surface of the thin wafer 1d to the other surface of the bonded wafer 1c by the same vacuum bonding method as described above, the reverse blocking IGBT 600 shown in FIG. 5C is completed. .

  Embodiment 4 of the present invention will be described below. By the method described in the first or second embodiment, two wafers having a thickness of 100 μm in which a boron diffusion layer (separation layer 5a) is connected from the front to the back are prepared, and these two sheets are not diffused by boron at all 1 Three wafers having a thickness of 100 μm are joined to produce a bonded wafer 1e having a thickness of 300 μm as shown in FIG. A MOS gate structure 10, an emitter electrode 8a, a breakdown voltage structure 9 and the like are formed on the surface of a region surrounded by the boron diffusion layer (separation layer 5a) of the bonded wafer 1e. As shown in FIG. 6B, a taper groove 14 is dug by etching on the back surface side of the bonded wafer so that the bottom of the taper groove 14 reaches the boron diffusion layer (separation layer 5a). Then, the reverse blocking IGBT 700 as shown in FIG. 6C is completed by forming the collector layer 7 and the collector electrode 8b connected to the separation layer 5a by boron ion implantation and laser annealing on the back surface.

  Embodiment 5 of the present invention will be described below. By the method described in the first or second embodiment, two wafers having a thickness of 100 μm in which a boron diffusion layer (separation layer 5a) is connected from the front to the back are prepared, and these two sheets are not diffused by boron at all 1 Three sheets of 100 μm wafers are bonded together to produce a wafer 1e having a thickness of 300 μm, similar to FIG. In this wafer 1e, a taper groove 14 is dug as shown in FIG. 7A from the side (back side) where there is no boron diffusion layer, so that the bottom reaches the boron diffusion layer (separation layer 5a). . As shown in FIG. 7B, the collector layer 7 is formed by ion implantation and annealing so as to connect the collector layer 7 and the separation layer 5a. The back side of the thin wafer 1d having the front side structure shown in FIG. 5 (b) is bonded and bonded to the front surface side of the wafer 1e having the boron diffusion layer (separation layer 5a) so that the separation layers overlap. Let it be a wafer 1f. The reverse blocking IGBT 800 as shown in FIG. 7C can be completed by depositing a collector electrode on the back side of the bonded wafer 1f where the tapered groove 14 is present.

  In the description of Examples 1 to 5 described above, the wafer 1 to be used has a thickness of 50 μm to 100 μm. However, there is a demerit that the diffusion time becomes long, but the semiconductor device of the present invention up to a thickness of 200 μm is used. Advantages of using this manufacturing method can be obtained.

  As described above, according to Examples 1 to 5 according to the present invention, in the conventional high-temperature and long-time thermal diffusion, when the adverse effect on the semiconductor characteristics or the diffusion furnace is taken into consideration, the depth of the separation layer that has a limit is limited. However, since it becomes substantially unlimited, it becomes possible to easily manufacture a high breakdown voltage reverse blocking IGBT in which the total wafer thickness becomes thicker.

1a, 1b, 1c, 1d wafer 2 oxide film 3 opening 4 boron source 5, 5a separation layer 6 scribe line 7 p collector layer 8a emitter electrode 8b collector electrode 9 breakdown voltage structure 10 MOS gate structure 11 trench 12 separation layer 13a chemical solution residue 13b Resist residue 14 Tapered groove 100, 200, 300, 400, 500, 600, 700, 800 Reverse blocking IGBT

Claims (6)

Forming a second conductive type penetrating region penetrating the first conductive type semiconductor substrate from any one or both main surfaces at a position surrounding the semiconductor device region of the first conductive type semiconductor substrate; A method of manufacturing a semiconductor device, comprising: mirror-finishing the first conductive type semiconductor substrate, and aligning the positions of the second conductive type through regions and bonding them in a vacuum. Forming a second conductive type first through region penetrating through the first conductive type semiconductor substrate at a position surrounding the semiconductor device region of the first conductive type semiconductor substrate from one or both main surfaces; , a plurality of the first conductivity type semiconductor substrate mirror finished, before Symbol align the second conductivity type first through region bonded in a vacuum, the separation of the first through region second conductivity type are stacked Forming a second conductive type semiconductor layer connected to the separation layer on one main surface of the bonded semiconductor substrate, and a first different from the bonded semiconductor substrate. Forming a second conductive type second through region, an active portion, and a breakdown voltage structure on one main surface of the conductive type semiconductor substrate; and the other main type of each of the bonded semiconductor substrate and the different first conductive type semiconductor substrate. The surface is the second conductivity type The method of manufacturing a semiconductor device characterized by a step of bonding the combined 1 through region and the position of the second through regions in vacuo. Forming a second conductive type first through region penetrating through the first conductive type semiconductor substrate at a position surrounding the semiconductor device region of the first conductive type semiconductor substrate from one or both main surfaces; Mirror-treating a plurality of first conductive type semiconductor substrates in which the second conductive type first through region is formed and a first conductive type semiconductor substrate in which the second conductive type first through region is not formed. The first conductive type semiconductor substrate in which the second conductive type first through region is formed and the first conductive type semiconductor substrate in which the second conductive type first through region is not formed are the second conductive type first. A step of aligning the positions of the through regions and bonding them in a vacuum to form a bonded semiconductor substrate, and an active portion on one main surface surrounded by the second conductive type first through region formed on the bonded semiconductor substrate Opposite to the process of forming a pressure-resistant structure And forming a second conductive type semiconductor layer on the other main surface after forming a tapered groove whose bottom reaches the second conductive type first through region on the other main surface. A method for manufacturing a semiconductor device. Forming a second conductive type first through region penetrating through the first conductive type semiconductor substrate at a position surrounding the semiconductor device region of the first conductive type semiconductor substrate from one or both main surfaces; Mirror-treating a plurality of first conductive type semiconductor substrates in which the second conductive type first through region is formed and a first conductive type semiconductor substrate in which the second conductive type first through region is not formed. The first conductive type semiconductor substrate in which the second conductive type first through region is formed and the first conductive type semiconductor substrate in which the second conductive type first through region is not formed are the second conductive type first. a step of the semiconductor substrate bonded by bonding in vacuum to align the transmembrane region, on the one main surface of the second conductive type first through region is not formed side of the semiconductor substrate mating Ri該貼, A taper where the bottom reaches the first through region of the second conductivity type After forming the groove, forming a second conductive type semiconductor layer, the other main surface of the semiconductor substrate mating Ri該貼, separately formed second conductivity type second transmembrane region comprising the active portion and the breakdown voltage structure the other main surface of the first conductivity type semiconductor substrate having one main surface, characterized by comprising a step of bonding in a vacuum by aligning the second conductivity type first through region and the second through region A method for manufacturing a semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the first conductivity type semiconductor substrate is 50 μm to 200 μm. 6. The semiconductor device, wherein the second conductivity type semiconductor layer is a p-type collector layer, and the active part is composed of a MOS gate structure and an emitter electrode, is a reverse blocking insulated gate bipolar transistor. The manufacturing method of the semiconductor device as described in 2 ..

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