JPH1051010A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the semiconductor device with a high breakdown voltage and a low resistance by breaking the resistance/breakdown voltage trade-off in a conventional design method. SOLUTION: After thermal oxidation is applied to an entire surface of an N-type silicon substrate low concentration layer 1, holes are made to part of the surface by a conventional photolithography method to form an N<+> diffusion layer 4 which is an N-type layer where an impurity element is diffused with higher concentration. Then a substrate resulting from growing an epitaxial grown layer 5 with the same concentration as that of the N channel layer 1 on the entire surface of the N<+> diffusion layer 4 is used for a start wafer, and an element is formed on the major surface opposite to the deep diffusion layer imbeded in the inside of the wafer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having high withstand voltage, low resistance, and high power.

[0002]

2. Description of the Related Art As a conventional method, a beveling structure, a guard ring structure or the like has been used as a method for increasing the breakdown voltage, and a method such as a large area or miniaturization has been used as a method for reducing the resistance.

[0003] Static induction type transistors (Static
Induction Transistor (SIT)
Is shown in FIG. That is, in the conventional SIT, the withstand voltage and the resistance are mainly determined by the thickness of the N ⁻ layer (N-type low-concentration impurity layer) 1. As the thickness of the N ⁻ layer 1 increases, the withstand voltage increases, but the resistance also increases. As the thickness decreases, the resistance decreases, but the breakdown voltage also decreases.

[0004]

In these methods, the breakdown voltage and the resistance have a reciprocal relationship. In other words, there is a reciprocal relationship that the resistance increases as the breakdown voltage increases, and the breakdown voltage decreases as the resistance decreases.

An object of the present invention is to provide a semiconductor device having a high withstand voltage and a low resistance by breaking the trade-off relationship between the resistance and the withstand voltage in the conventional design method.

[0006]

According to the present invention, a first conductivity type silicon substrate is thermally oxidized over the entire surface, and then a part of the surface is opened by a usual photolithography technique to form the same portion as the first conductivity type. A substrate of a conductivity type with a higher impurity concentration diffusion is prepared, and an epitaxial layer of the same concentration as the first conductivity type is grown on the entire surface of the substrate with a high concentration of deep diffusion. The buried substrate is used as a starting wafer, and elements are formed on the main surface opposing the deep diffusion region buried inside the substrate. An element is formed on a main surface opposed to a deep diffusion region buried therein, using a substrate in which an impurity layer is buried as a starting wafer.

[0007]

The peripheral portion of the element which determines the breakdown voltage is designed by the impurity concentration and thickness of the substrate in accordance with the conventional design, and the inside of the element (the active region) which determines the internal resistance has a structure in which the current path length is shortened. The object of the present invention is achieved by overcoming the trade-off relationship between withstand voltage and resistance.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a high withstand voltage static induction transistor (SIT) will be described.

First, a first embodiment will be described with reference to FIGS.

As shown in FIG. 1A, an N-type silicon substrate 3 is prepared. As the substrate, the silicon substrate low-concentration layer 1 has a specific resistance ρ = 70 Ωcm and a thickness t _N− = 50 μm, and the silicon substrate high-concentration layer 2 has a specific resistance ρ = 0.002 Ωcm and a thickness t.
_{N +} = 150 μm. Next, as shown in FIG.
The silicon substrate low-concentration layer 1 is thermally oxidized to form an opening in the silicon substrate low-concentration layer 1 by photolithography, and an N ⁺ diffusion layer 4 of the same conductivity type and the same concentration as the silicon substrate high-concentration layer 2 is formed. Form. Next, as shown in FIG. 1C, an epitaxial growth layer (N ⁻ layer) 5 is formed on the silicon substrate low concentration layer 1 and the N ⁺ diffusion layer 4 by vapor phase growth. The concentration is 5 × 10 ¹³ cm ⁻³ and the thickness t is 50 μm. Here, the N ⁺ diffusion layer 4 becomes a buried layer. next,
As shown in FIG. 1D, a P-type impurity (boron: B) is diffused in a stripe shape on the substrate surface and on an N ⁺ diffusion layer (N ⁺ buried layer) 4 by photolithography to form a P ⁺ diffusion layer. 6 and 7 are formed. The concentration is 5 × 10 ¹⁹ cm ⁻³ and the thickness t =
2 μm.

As shown in FIG. 2A, an epitaxial growth layer 8 is formed on the silicon substrate low concentration layer 1 and the P ⁺ diffusion layers 6 and 7 by epitaxial growth. The concentration is 2 × 10 ¹⁵ cm ⁻³ and the thickness t is 13 μm. Here, the P ⁺ diffusion layers 6 and 7 become buried layers, and the diffusion proceeds to the silicon substrate low-concentration layer 1 and the epitaxial growth layer 8 to increase the thickness. Next, as shown in FIG. 2B, a hole is formed in the epitaxial growth layer 8 by photolithography, an opening for forming a gate electrode is formed, and P ⁺
A part of the diffusion layer 7 is exposed. Next, as shown in FIG. 2C, a P-type impurity (boron: B) is diffused by photolithography to form a P ⁺ diffusion layer 10 to form a gate ohmic layer. The concentration is 5 × 10 ¹⁹ cm ^-3 and the thickness t
= 2 μm. Here, gate electrode layer 11 is formed from P ⁺ diffusion layers 7 and 10. Next, as shown in FIG. 2D, an N ⁺ ohmic layer (N ⁺ diffusion layer) 12 is formed on a part of the epitaxial growth layer 9 by photolithography.
Is formed by diffusion. The concentration is 1 × 10 ²⁰ cm ⁻³ and the thickness t is 2 μm.

Next, as shown in FIG. 3A, the entire surface of the silicon substrate is thermally oxidized, and surface protective oxide films 13 and 14 are formed by photolithography. Next, FIG.
As shown in FIG.
To form As a method of forming the mesa groove, a dicing method,
Laser processing, wet etching, dry etching, and the like can be applied. Thereafter, the surface of the mesa groove is etched to remove distortion when the mesa groove is formed. Next, as shown in FIG. 3C, a lead-based or zinc-based glass is electrodeposited and fired in the mesa groove 16 to form a high-breakdown-voltage glass passivation film 17.
To form Next, as shown in FIG. 3D, aluminum is metallized on the source electrode 18, the gate electrode 19, and the drain electrode 20 to form each electrode.

The first embodiment is characterized in that a diffusion substrate is used and an epitaxial growth layer is used in combination.

Hereinafter, a second embodiment will be described with reference to FIGS. As shown in FIG. 4A, an N-type low concentration silicon substrate 21 is prepared. The substrate has a low concentration layer, a specific resistance ρ = 70 Ωcm, and a thickness t _N− = 150 μm. Next, Yo shown in FIG. 4 (b), by photolithography and a low density silicon substrate 21 is thermally oxidized at a low concentration silicon substrate 21 to form an opening, N ⁺ diffusion layer (high concentration diffusion layer 4) is formed. Next, as shown in FIG. 4C, a high-concentration silicon substrate 22 is prepared. next,
As shown in FIG. 4D, the high-concentration silicon substrate 22 is attached to the side on which the N ⁺ diffusion layer 4 is formed by a wafer attaching technique to form a single wafer. N ⁺ diffusion layer 4 becomes a buried layer. Next, as shown in FIG.
P-type impurities (boron: B) are diffused in a stripe form on the substrate surface and on the N ⁺ diffusion layer (N ⁺ buried layer) 4 by photolithography to form P ⁺ diffusion layers 6 and 7. The concentration is 5 × 10 ¹⁹ cm ⁻³ and the thickness t is 2 μm.

Next, as shown in FIG. 5A, an epitaxial growth layer 8 is formed on the low-concentration silicon substrate 21 and the P ⁺ diffusion layers 6 and 7 by epitaxial growth. The concentration is 2 × 10 ¹⁵ cm ⁻³ and the thickness t is 13 μm. Here, the P ⁺ diffusion layers 6 and 7 become buried layers, and the diffusion proceeds to the low-concentration silicon substrate 21 and the epitaxial growth layer 8 to increase the thickness. Next, as shown in FIG. 5B, the epitaxial growth layer 8 is opened by photolithography, an opening for forming a gate electrode is formed, and a part of the P ⁺ diffusion layer 7 is exposed. Next, FIG.
As shown in (c), by photolithography, P
A P ⁺ diffusion layer 10 is formed by diffusing a type impurity (boron: B) to form a gate ohmic layer. The concentration is 5 × 10 ¹⁹ c
m ⁻³ and thickness t = 2 μm. Here, the P ⁺ diffusion layer 7,
From 10, a gate electrode layer 11 is formed. Next, FIG.
As shown in (d), an N ⁺ diffusion layer (N ⁺ ohmic layer) 12 is formed in a part of the epitaxial growth layer 9 by diffusion using photolithography. The concentration is 1 × 10 ²⁰
cm ⁻³ and thickness t = 2 μm.

Next, as shown in FIG. 6A, the entire surface of the low-concentration silicon substrate 21 is thermally oxidized and surface protection oxide films 13 and 14 are formed by photolithography. next,
As shown in FIG. 6B, in order to obtain a high withstand voltage structure,
A mesa groove 16 is formed. As a method for forming the mesa groove, a dicing method, a laser processing method, a wet etching method, a dry etching method, or the like can be applied. Thereafter, the surface of the mesa groove 16 is etched to remove distortion when the mesa groove is formed. next,
As shown in FIG. 6C, a lead-based or zinc-based glass is electrodeposited and fired in the mesa groove 16 to form a high-breakdown-voltage glass passivation film 17. Next, as shown in FIG. 6D, aluminum is metallized on the source electrode 18, the gate electrode 19, and the drain electrode 20 to form respective electrodes.

The second embodiment is characterized in that a low-concentration silicon substrate is used, and wafer bonding and epitaxial growth layers are used together.

Hereinafter, a third embodiment will be described with reference to FIGS. An N-type silicon substrate 3 is prepared as shown in FIG. As the substrate, the silicon substrate low-concentration layer 1 has a specific resistance ρ = 70Ωcm and a thickness t _N− = 50 μm.
m, the silicon substrate high concentration layer 2 has a specific resistance ρ = 0.002Ω.
cm and thickness t _{N +} = 150 μm. Next, FIG.
As shown in (b), the silicon substrate low-concentration layer 1 is thermally oxidized to form an opening in the silicon substrate low-concentration layer 1 by photolithography, and the same conductivity type and the same as those of the silicon substrate high-concentration layer 2. An N ⁺ diffusion layer 4 having a concentration is formed. next,
As shown in FIG. 7C, a low-concentration silicon substrate 23 having the same conductivity type and the same concentration as the silicon substrate 1 is prepared. Next, as shown in FIG.
High-concentration N ⁺ diffusion layer 4
Is attached to the side on which is formed a single wafer. This N ⁺ diffusion layer 4 becomes a buried layer. Next, FIG.
As shown in (e), a P-type impurity (boron: B) is diffused in a stripe shape on the substrate surface and on the N ⁺ diffusion layer (N ⁺ buried layer) 4 by photolithography, and the P ⁺ diffusion layer 6 is formed.
7 is formed. The concentration is 5 × 10 ¹⁹ cm ⁻³ and the thickness t = 2 μ
m.

Next, as shown in FIG. 8A, an epitaxial growth layer 8 is formed on the low concentration silicon substrate 23 and the P ⁺ diffusion layers 6 and 7 by epitaxial growth. The concentration is 2 × 10 ¹⁵ cm ⁻³ and the thickness t is 13 μm. Here, the P ⁺ diffusion layers 6 and 7 become buried layers, and the diffusion proceeds to the low-concentration silicon substrate 23 and the epitaxial growth layer 8 to increase the thickness. Next, as shown in FIG. 8B, a hole is formed in the epitaxial growth layer 8 by photolithography, an opening for forming a gate electrode is formed, and a part of the P ⁺ diffusion layer 7 is exposed. Next, FIG.
As shown in (c), by photolithography, P
A P ⁺ diffusion layer 10 is formed by diffusing a type impurity (boron: B) to form a gate ohmic layer. The concentration is 5 × 10 ¹⁹ c
m ⁻³ and thickness t = 2 μm. Here, the P ⁺ diffusion layer 7,
From 10, a gate electrode layer 11 is formed. Next, FIG.
As shown in (d), an N ⁺ diffusion layer (N ⁺ ohmic layer) 12 is formed in a part of the epitaxial growth layer 9 by diffusion using photolithography. The concentration is 1 × 10 ²⁰
cm ⁻³ and thickness t = 2 μm.

Next, as shown in FIG. 9A, the entire surface of the silicon substrate is thermally oxidized, and surface protection oxide films 13 and 14 are formed by photolithography. Next, FIG.
As shown in FIG.
To form As a method of forming the mesa groove, a dicing method,
Laser processing, wet etching, dry etching, and the like can be applied. Thereafter, the surface of the mesa groove 16 is etched to remove distortion when the mesa groove is formed. Next, FIG.
As shown in FIG. 6, a lead-based or zinc-based glass is electrodeposited and fired in the mesa groove 16 to form a high-breakdown-voltage glass passivation film 17. Next, as shown in FIG. 9D, the source electrode 18, the gate electrode 19, and the drain electrode 20 are metallized with aluminum to form respective electrodes.

The third embodiment is characterized in that a diffusion silicon substrate is used, and a wafer bonding and an epitaxial growth layer are used together.

Hereinafter, a fourth embodiment will be described with reference to FIGS.
This will be described with reference to FIG. An N-type silicon substrate 3 is prepared as shown in FIG. The substrate is a low concentration layer, specific resistance ρ = 70 Ωcm, and thickness t _N− = 100 μm. Next, as shown in FIG. 10B, the low-concentration silicon substrate 21 is thermally oxidized and
An opening is formed in the low-concentration silicon substrate 21 and a high-concentration N
^{+ A} diffusion layer 4 is formed. Next, as shown in FIG. 10C, a high-concentration silicon substrate 22 is prepared. Next, FIG.
As shown in (d), the high-concentration silicon substrate 22 is bonded to the side where the N ⁺ diffusion layer 4 is formed by a wafer bonding technique to form a single wafer. N ⁺ diffusion layer 4
Becomes a buried layer. Next, as shown in FIG. 10E, an N ⁺ diffusion layer (N
⁺ P type impurity (boron:
B) is diffused to form P ⁺ diffusion layers 6 and 7. The concentration is 5
× 10 ¹⁹ cm ⁻³ and thickness t = 2 μm.

Next, as shown in FIG. 11, a high concentration silicon substrate 24 is prepared. The concentration is 2 × 10 ¹⁵ cm ⁻³ and the thickness t is 50 μm.

Next, as shown in FIG. 12A, a high-concentration silicon substrate 24 is bonded on the low-concentration silicon substrate 21 and the P ⁺ diffusion layers 6 and 7 by a wafer bonding technique. One wafer. Here, the P ⁺ diffusion layers 6 and 7 are buried layers. Next, as shown in FIG. 12B, the high-concentration silicon substrate 24 is opened by photolithography, and an opening for forming a gate electrode is formed.
A part of the P ⁺ diffusion layer 7 is exposed. Next, FIG.
As shown in FIG. 2, a P-type impurity (boron: B) is diffused by photolithography to form a P ⁺ diffusion layer 10.
The gate ohmic layer is used. The concentration is 5 × 10 ¹⁹ cm ⁻³ ,
The thickness t is set to 2 μm. Here, gate electrode layer 11 is formed from P ⁺ diffusion layers 7 and 10. Next, FIG.
As shown in (d), an N ⁺ diffusion layer (N ⁺ ohmic layer) 12 is formed in a part of the epitaxial growth layer 25 by photolithography. The concentration is 1 × 10
²⁰ cm ⁻³ and thickness t = 2 μm.

Next, as shown in FIG. 13A, the entire surface of the silicon substrate is thermally oxidized and photolithography is performed.
The surface protection oxide films 13 and 14 are formed. Next, FIG.
As shown in FIG. 2B, a mesa groove 16 is formed in order to obtain a high breakdown voltage structure. As a method for forming the mesa groove, a dicing method, a laser processing method, a wet etching method, a dry etching method, or the like can be applied. Thereafter, the surface of the mesa groove is etched to remove distortion when the mesa groove is formed. Next, FIG.
As shown in (c), a lead-based or zinc-based glass is electrodeposited and fired in the mesa groove 16 to form a high-breakdown-voltage glass passivation film 17. Next, as shown in FIG. 13D, aluminum is metallized on the source electrode 18, the gate electrode 19, and the drain electrode 20 to form each electrode.

The above-described fourth embodiment is characterized in that a low-concentration silicon substrate is used and two wafer bonding steps are used. Here, the thickness of each diffusion layer is larger than the thickness due to the heat treatment during the process.

The SIT obtained according to the present invention has the characteristics that the chip size is S = 10 mm ² , the withstand voltage V _GDO = 1800 V, and the resistance R _on = 0.75Ω. The resistance is reduced by about 20% at the same withstand voltage value as compared with the conventional SIT. This is because the thickness of the N ⁻ layer of the silicon substrate in the active region portion 77 is reduced by about 50 μm (the thickness is reduced by about 25%) due to the diffusion of N ⁺ .

[0028] The practice of the present invention, according to conventional design element peripheral portions 27 and 28, as shown in FIG. 14, the impurity concentration of the substrate and the N ^- breakdown voltage due to the substrate thickness A is determined, the internal resistance primarily current path It is determined by the thickness B of the N ^- substrate of the active region 26, and the current path length B is shortened, so that a low resistance is obtained at the same breakdown voltage as the conventional one.

Here, the expansion of the depletion layer that determines the breakdown voltage expands in the direction from the broken line D to E in FIG. 14, and in the active region, the depletion layer reaches the N ⁺ diffusion layer 4 at a low voltage. , Spread to the peripheral portion of the element (to the broken line F), and the breakdown voltage is determined in the peripheral portion. Since the thickness of the N ^- layer at the peripheral portion is the same as that of the related art, the same breakdown voltage value can be obtained.

Although this embodiment has been described with reference to the SIT, it is needless to say that the present invention can be applied to other high withstand voltage devices such as a diode, a bipolar transistor, an FET, a thyristor, and an IGBT.

[0031]

According to the present invention, the element peripheral portions 27, 2
8. By arbitrarily designing the active region 26 and the thicknesses A and B of the N ⁻ substrate, it is possible to provide an SIT having characteristics that break the conventional trade-off between the breakdown voltage and the resistance. Further, by performing wafer bonding instead of epitaxial growth, there are the following features and advantages in the process.

In order to form a thick epitaxial growth layer, a heat treatment at a high temperature for a long time is required, which causes the problem of autodoping of the diffusion layer, and it is difficult to grow a low concentration layer thickly on a high impurity concentration substrate. However, according to the present invention, the introduction of the wafer bonding technique requires only a short heat treatment, and has a process feature that auto-doping hardly occurs due to the short heat treatment time. In addition, it is easy to join a high-concentration substrate and a low-concentration substrate, and the concentration distribution can be controlled by heat treatment conditions.

Further, according to the present invention, unlike the epitaxial growth, in the case of wafer bonding, an existing wafer is bonded so that there is no crystal defect which is a problem in the epitaxial growth layer.

According to the present invention, when deep diffusion is to be obtained, the diffusion time is enormous. However, in the case of wafer bonding, the processing time is significantly reduced by bonding an existing substrate having a desired concentration. Therefore, deep diffusion can be substituted. Further, the thickness can be freely set by polishing, and it is easy to manufacture a dielectric isolation type substrate (SOI) by bonding an oxidized wafer.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of an electrostatic induction transistor (SIT) according to an embodiment of the present invention.

FIG. 2 is a view showing a manufacturing process of an electrostatic induction transistor (SIT) according to an embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing process of an electrostatic induction transistor (SIT) according to an embodiment of the present invention.

FIG. 4 is a diagram showing a manufacturing process of an electrostatic induction transistor (SIT) according to an embodiment of the present invention.

FIG. 5 is a diagram showing a manufacturing process of an electrostatic induction transistor (SIT) according to an embodiment of the present invention.

FIG. 6 is a diagram showing a manufacturing process of an electrostatic induction transistor (SIT) according to an embodiment of the present invention.

FIG. 7 is a diagram showing a manufacturing process of an electrostatic induction transistor (SIT) according to an embodiment of the present invention.

FIG. 8 is a diagram showing a manufacturing process of the electrostatic induction transistor (SIT) according to the embodiment of the present invention.

FIG. 9 is a diagram showing a manufacturing process of an electrostatic induction transistor (SIT) according to an embodiment of the present invention.

FIG. 10 is a diagram illustrating a manufacturing process of the static induction transistor (SIT) according to the embodiment of the present invention.

FIG. 11 is a diagram showing a manufacturing process of an electrostatic induction transistor (SIT) according to an embodiment of the present invention.

FIG. 12 is a diagram showing a manufacturing process of the static induction transistor (SIT) according to the embodiment of the present invention.

FIG. 13 is a diagram showing a manufacturing process of the static induction transistor (SIT) according to the embodiment of the present invention.

FIG. 14 shows an electrostatic induction transistor (SI) according to the present invention.
It is a figure which shows the structure of T).

FIG. 15 is a diagram showing a structure of a conventional static induction transistor (SIT).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon substrate low concentration layer 2 Silicon substrate high concentration layer 3 N type silicon substrate 4 N ⁺ diffusion layer (N ⁺ buried layer) 5 Epitaxial growth layer 6 P ⁺ diffusion layer 7 P ⁺ diffusion layer 8 Epitaxial growth layer 9 Epitaxial growth layer 10 P ⁺ Diffusion layer 11 Gate electrode layer 12 N ⁺ Diffusion layer 13 Surface protection oxide film 14 Surface protection oxide film 15 Opening 16 Mesa groove 17 Glass passivation film 18 Source electrode 19 Gate electrode 20 Drain electrode 21 Low concentration silicon substrate 22 High concentration Silicon substrate 23 Low-concentration silicon substrate 24 High-concentration silicon substrate 25 Low-concentration region 26 Active region 27 Element peripheral part 28 Element peripheral part

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 21/329 H01L 29/91 B 29/861 D

Claims (5)

[Claims] After a first-conductivity-type silicon substrate is entirely thermally oxidized, a part of the surface is opened by a usual photolithography method, and a higher impurity of the same conductivity type as the first-conductivity type is used. A substrate having a high-concentration diffusion is prepared, and an epitaxial layer having the same concentration as that of the first conductivity type is grown on the entire surface of the substrate having a high-concentration deep diffusion. A method of manufacturing a semiconductor device, wherein an element is formed on a main surface of a wafer opposing a deep diffusion region embedded therein. 2. After the entire surface of a silicon substrate of the first conductivity type is thermally oxidized, a part of the back surface is opened by a normal photolithography technique, and a higher impurity of the same conductivity type as the first conductivity type is used. A substrate having a high concentration of deep diffusion is prepared, and a substrate having a high concentration of deep diffusion and a substrate of the same conductivity type as the first conductivity type are prepared. These are bonded to a wafer to form a single substrate in which the high-concentration layer is buried, and the substrate in which the high-concentration impurity layer is buried is used as a starting wafer, and on the main surface opposed to the deep diffusion region buried therein. A method for manufacturing a semiconductor device, wherein an element is formed. 3. After the whole surface of the silicon substrate of the first conductivity type is thermally oxidized, a part of the surface is opened by a normal photolithography technique, and a higher impurity of the same conductivity type as the first conductivity type is used. A substrate having a concentration diffusion is prepared, and the first surface is formed on a main surface opposed to a deep diffusion region embedded therein.
Prepare a high-concentration substrate with the same conductivity type as that of the above, bond the wafer to create a single substrate, and form an element on the main surface opposing the deep diffusion region embedded inside A method of manufacturing a semiconductor device, comprising: 4. After the whole surface of the silicon substrate of the first conductivity type is thermally oxidized, a part of the back surface is opened by a normal photolithography technique, and a higher impurity of the same conductivity type as the first conductivity type is used. A substrate having the same concentration as the first conductive type is prepared on the surface of the substrate on which the high-concentration diffusion is performed, and these are bonded to a wafer. To form a single substrate in which a high-concentration layer is buried, and further prepare a high-concentration substrate of the same conductivity type as the first conductivity type on the main surface opposed to the deep diffusion region buried therein. A method of manufacturing a semiconductor device, wherein wafers are bonded to form a single substrate, and an element is formed on a main surface opposed to a deep diffusion region embedded therein. 5. The method according to claim 1, wherein the thickness of the first conductive type low-concentration layer corresponding to immediately below the active region of the semiconductor device is substantially reduced, and the thickness of the first conductive type low-concentration layer at the outer peripheral portion is deep and high-concentration diffusion. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness before the implementation is maintained.