WO2007004528A1

WO2007004528A1 - Method for designing structure of silicon carbide electrostatic induction transistor

Info

Publication number: WO2007004528A1
Application number: PCT/JP2006/313046
Authority: WO
Inventors: Koji Yano; Masanobu Kasuga; Tsutomu Yatsuo; Yasunori Tanaka; Mitsuo Okamoto
Original assignee: Yamanashi University; National Institute Of Advanced Industrial Science And Technology
Priority date: 2005-06-30
Filing date: 2006-06-30
Publication date: 2007-01-11
Also published as: JPWO2007004528A1; JP5076146B2

Abstract

When the parameters of the channel structure of a normally-on silicon carbide electrostatic induction transistor, i.e. channel length xj, half channel width a, and channel donor impurity concentration Nch, are determined, a combination of a and Nch satisfying an expression 2.1×107/√Nch<a<1.72×108/√Nch concerning the limits of characteristic on resistance and breakdown voltage is determined, and xj of 4 μm or less satisfying an expression a<-0.1+0.9 xj-0.1 xj2 is also determined (a and xj have a unit of μm, Nch has a unit of cm-3).

Description

Specification

Method for designing silicon carbide static induction transistor structure

Technical field

TECHNICAL FIELD [0001] The present invention relates to a design method for a normally-on type epitaxial channel buried gate silicon carbide electrostatic induction transistor structure, and more particularly to a design method for a channel structure that ensures conduction and current interruption operation of an element.

Background art

[0002] Silicon carbide (hereinafter, SiC) is promising as a material for power transistors because of its high breakdown electric field strength, high mobility, high thermal conductivity, and wide band gap. On the other hand, an electrostatic induction transistor (SIT) is a transistor that exhibits unsaturated current-voltage characteristics and has low loss and high-speed switching performance.

[0003] A silicon carbide static induction transistor (hereinafter referred to as SiC-SIT) is an element that has both the advantages of SiC and the high performance of SIT, and achieves about 1/100 of the conduction loss of a silicon power transistor. This is theoretically possible and is promising as a low-loss power transistor.

[0004] The basic operation of SIT is to efficiently control the potential barrier formed in the channel region with the drain voltage and the gate voltage. In particular, as a result of reducing the parasitic resistance of the channel region, Achieves low on-resistance. Therefore, the design of the channel structure is important to obtain the above SIT performance.

[0005] Until now, a clear SIT channel structure design technique has not been established, but the channel structure is often determined based on the width of the depletion layer based on the full depletion approximation of the semiconductor pn junction. (Non-Patent Document l, Fig. 13, 14, 15 and Equation 14).

[0006] The full depletion approximation means that the concentration of electrons and holes in the depletion layer is zero when the electric field potential distribution inside the depletion layer formed at the junction such as a pn junction is derived. This means that the calculation proceeds with the assumption of a fully depleted situation.

FIG. 1 shows a conventional design method for channel impurity concentration N and half channel width a. Non-patent

ch

In Document 1, if the channel is designed with a set of N and a to satisfy Equation 14 in the same document,

ch

The figure of merit considering the performance of both breakdown voltage and on-resistance is said to be the best. This

In equation (1), ε is the relative permittivity of the semiconductor, ε is the permittivity of the vacuum, and V is the diffusion of the ρη junction.

s 0 bi

Potential, q is unit charge. The meaning of this formula is to set the pair of a and N so that the value of a is between the depletion layer width at zero voltage and the depletion layer width when V reverse bias is applied according to the full depletion approximation.

bi ch

It means to do. Design region 1 in Fig. 1 is the range of N and a pairs that satisfy the condition of equation (1) when the material is assumed to be SiC.

ch

[0008] Here, the straight line 1 satisfies the value power ¾ on the left side of the equation (1), and is one design limit relating to the characteristic on-resistance. On the other hand, line 2 satisfies the value power ¾ on the right-hand side of equation (1) and gives a design limit for the breakdown voltage. The a = wd mark (0V), a = wd mark (2.5V), a = wdep (-Vbi), and a = wdep (-15V) described in Fig. 1 are 0 [ ¥], 2.5 ^],-¾- Depletion layer width when a voltage of 15 [V] is applied. This means that the wd mark is equal to a.

[0009] If the above conventional design method is applied, the value of a is assumed to be between the depletion layer widths obtained by the full depletion approximation when the gate-source voltage VGS is 2.5 V and -15 V. N and

If a set of ch a is set, the non-depletion region always remains in the channel region when the on signal VGS = 2.5V is applied, so that the element can be made conductive, and at the same time when the off signal VGS = _15V is applied. Since the depletion layer from the adjacent gate region is always in contact with the center of the channel and a potential barrier is formed, the current can be interrupted. That is, formula (2)

[Equation 2]

If the combination of a and N is determined so as to satisfy the requirements, 2.5V and -15V can be marked as VGS. Thus, it is theoretically possible to design an element capable of conduction and current interruption.

[0010] The range that satisfies Equation (2) when the material is assumed to be SiC is design region 2 in FIG. As in the case of equation (1), line 3 satisfies the value power ¾ on the left side of equation (2), and is one design limit for characteristic on-resistance. On the other hand, line 4 satisfies the value power on the right side of Eq. (2) and gives a design limit for the breakdown voltage.

[0011] As another channel region design, as shown in Fig. 1 of Patent Document 1, a high-concentration P region (hereinafter referred to as a P ⁺ region) with an acceptor concentration of 10 ¹⁸ cm- ³ or more on the source side. There is a contrivance to reduce the voltage drop during drain-source conduction by adjusting the impurity concentration of the channel region sandwiched between the drain side channel region and adjusting the depletion layer width of the source side channel region. .

[0012] Non-Patent Document 1: IEEE Trans. Electron Devices, ED_24, No.8 pp.1061-1069, 1977.

Fig.13, 14,15

Patent Document 1: JP-A-8-316492

Disclosure of the invention

Problems to be solved by the invention

[0013] However, the first problem of the conventional design method is that the electrostatic barrier effect from the drain electrode and the gate electrode, which are important in the operation of the SIT, is affected by the potential barrier in the channel region. It is not built in consideration of interaction.

[0014] The operation principle of the SIT will be described using the vertical buried gate structure SIT shown in FIG. The operation principle of SIT is that the height of the potential barrier formed in the channel region by the depletion layer extending from the gate P ⁺ region 4 to the channel region 3 is determined by both the electrostatic induction effect due to the gate voltage and the electrostatic induction effect due to the drain voltage. Basically, the current flowing between the drain region 1 and the high concentration source region 6 is controlled.

[0015] In particular, by reducing the potential barrier height by the electrostatic induction effect due to the drain voltage, the channel from the high-concentration source region 6 that is a high-concentration region (hereinafter referred to as N ⁺ region) with donor concentration force Sl0 ¹⁸ cm- ³ or higher By injecting electrons into the drift region 2 through the potential barrier in the region 3, an unsaturated current-voltage characteristic in which the drain current is not saturated due to an increase in the drain voltage is realized. [0016] In order to realize the unsaturated current-voltage characteristics, the channel length Xj is reduced to reduce the parasitic resistance in the channel region, thereby increasing the electrostatic induction effect of the drain voltage and increasing the efficiency by the drain voltage. A design that often lowers the potential barrier in the channel region is necessary.

That is, in the design of the SIT channel structure, it is necessary to reflect the interaction of the electrostatic induction effect from the drain electrode and the gate electrode to the potential barrier of the channel region.

[0018] In particular, the electrostatic induction effect due to the drain voltage has the effect of lowering the potential barrier as described above, and may reduce the breakdown voltage. The design upper limit of half channel width a independent of N is

ch

Although it should exist, there is a problem with the conventional design method that there is no design policy regarding the upper limit.

[0019] The second issue of the conventional design method is the design method determined by the simulation and the support of the experimental facts, with the conventional design method using silicon (hereinafter referred to as Si) as the semiconductor material for SIT. There is a problem that it has not been demonstrated whether the design method can be applied to the device.

[0020] SiC and Si differ in material physical parameters such as carrier mobility, band gap, and ionization coefficient. If these physical property parameters are different, the effect of the electrostatic induction effect on the potential barrier is also different, and as a result, the design method may need to be modified.

[0021] Further, as described above, the conventional design method is derived based on the complete depletion approximation that no carrier exists in the depletion layer. However, the carrier flows in from the neutral region in contact with the depletion layer at the end in the actual depletion layer, and this approximation does not hold.

[0022] The potential barrier in the channel region of the SIT is formed by overlapping electric fields in the depletion layer extending from the P ⁺ gate regions 4 on both sides of the channel region 3 at the center of the channel. That is, the electric field distribution at the end of the depletion layer is greatly related to the height of the potential barrier. Therefore, the design method based on the conventional formula (1) and formula (2) based on the perfect depletion approximation lacks accuracy.

[0023] The third problem of the conventional design method is that the conventional design method assumes that the shape of the p ⁺ gate region is cylindrical. This is a design method in the case where it is determined. On the other hand, in the epitaxial channel buried gate structure, the cross-sectional shape of the p ⁺ gate structure is square. Therefore, the conventional design method cannot be applied as it is to an epitaxial channel loading gate structure.

[0024] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a channel structure design method for ensuring both the conduction operation and the current interruption operation of SiC_SIT.

Means for solving the problem

[0025] In order to solve the above problem, the present invention provides a normally-on type epitaxial channel loading gate silicon carbide electrostatic induction transistor (normally on • EC 'SiC-SIT) having a breakdown voltage of 800 to 1200V. In determining the channel length x, half channel width a, and channel donor impurity concentration N, which are parameters of the channel structure, the following equation (3) ch regarding the characteristic on-resistance

[Equation 3]

And the following equation for the breakdown voltage (4)

[Equation 4]

Determines the combination of a and N that satisfies the conditions of the two equations, and X is 4 m or less and

ch j

The following formula (5)

[Equation 5]

«<-£) .1+ 0, 广 O.lxJ '*' * * 53 It is characterized in that x satisfying the condition of is determined. Where N is the channel region 3 (see Fig. 5) j ch

The donor impurity concentration, a is the half channel width value, and X is the channel length. N is cm— ³ , ao j ch

And x have units of z m. The channel region mentioned here is preferably a rectangular parallelepiped having a width force ¾a, a length force, a depth sufficiently large compared to 2a and X, and a donor impurity concentration N. Equations (3) are preferably applied under the condition of VGS = 2.5V. Equations (4) and (5) are preferably applied under the condition of VGS = -15V.

Equation (3) according to the present invention corresponds to the lower limit value of a in Equations (1) and (2), which are conventional design methods, and is derived by strict semiconductor device simulation described later. Therefore, equation (3) can provide a more accurate design area for characteristic on-resistance than the conventional design method.

Similarly, equation (4) according to the present invention is a force corresponding to the upper limit value of a in equations (1) and (2), which are conventional design methods. As a result, the design area for the breakdown voltage can be provided by Equation (4), which is more accurate than the conventional design method.

Furthermore, the expression (5) according to the present invention is a conditional expression concerning a new limit which is not shown in the conventional design method. This is a result of accurate simulation of the interaction of the electrostatic induction effect from both the drain electrode and the gate electrode to the potential barrier in the channel region by strict semiconductor device simulation described later.

[0029] Equation (5) means that the upper limit value of a regarding the breakdown voltage does not depend on N because the electrostatic induction effect due to the drain voltage is sufficiently larger than the electrostatic induction effect due to the gate voltage.

is doing. In other words, this can provide an accurate upper limit value of a that can reliably turn off SiC-SIT.

[0030] Therefore, a combination of a and N satisfying the two expressions (3) and (4) according to the present invention is represented by ch.

And determine X that satisfies the condition of equation (5) below X force S4 z m, and these a, N,

If you design the channel region using J J ch χ, you will surely have a breakdown voltage of 800-1200V and conduct

J

And SiC-SIT that can cut off current can be fabricated.

[0031] The present invention relates to the design technique of the channel structure according to claim 1 in SiC-SIT normally. It is characterized by applying to one-on-EC-SiC-SIT structure. The normally-on · EC · SiC-SIT structure, P ⁺ gate region 4 as shown in FIG. 5 is written Tanme below the source low concentration region 5, the source electrode 8 is disposed on the surface of the device, The gate electrode 9 is a structure that is installed around the source electrode 8. Here, when forming the gate electrode, a trench reaching the buried P ⁺ gate region 4 is formed in a part around the source electrode, and the gate electrode 9 is provided at the bottom of the trench. The channel region 3 is disposed so as to be surrounded by the P ⁺ gate region 4 and is not connected to the gate electrode 9. The channel region 3 is formed by embedding a trench portion by anisotropic trench etching technology and epitaxial growth, and the cross-sectional shape of the p ⁺ gate region is basically square.

In addition, the present invention takes into account variations in the half-channel width a and the impurity concentration N in the channel region that occur during the production of normally-on 'EC' SiC-SIT.

ch

Since there is no variation in characteristic on-resistance,

圆

••• (6)

To determine the half-channel width a and the impurity concentration Ν of the channel region to satisfy

ch

Similarly, since the breakdown voltage does not vary, the following formula

[Equation 7]

••• (7)

The half channel width a and the channel region impurity concentration N should be determined to satisfy

ch

Features.

Further, the present invention is created by the channel structure design method according to claims 1 to 4. Normally-ON EC · SiC-SIT is characterized in that an N-type region with a concentration lower than the impurity concentration of the N-type channel region is provided on the source region side in contact with the gate p ⁺ region. . With this structure, the width of the depletion layer extending from the gate p ⁺ region 4 to the source region 6 side in FIG. 9 is increased, and the negative voltage applied to the gate electrode 9 is increased with respect to the source electrode 8 when the element is shut off. As it comes, switching time can be shortened.

[0034] Further, the present invention provides a normally-on-EC-SiC-SIT produced by the channel structure design method according to claims 1 to 4, and on the drain region side in contact with the gate p ⁺ region. An N − type region having a lower concentration than the impurity concentration of the N type channel region is provided. With this structure, the breakdown voltage between the drain 'source and drain' gate can be increased.

[0035] Further, the present invention provides a normally-on-EC-SiC-SIT produced by the channel structure design method according to claims 1 to 4, and the source region side in contact with the gate p ⁺ region and A feature is that an N-type region having a lower concentration than the impurity concentration of the N-type channel region is provided on the drain region side. With this structure, the negative voltage applied to the gate electrode 9 can be increased with respect to the source electrode 8 when the element is shut off in FIG. 11, and at the same time, the switching time can be shortened. The voltage can be increased.

[0036] Further, according to the present invention, the channel region width is set to a distance from the gate electrode in a normally-on EC · SiC-SIT produced by the channel structure design method according to claims 1 to 4. It is characterized by a linear function decrease. In a conventional buried gate SIT structure, when data N'ofu p ⁺ voltage drop or immediately it occurs in the gate region Yotsute spreads the depletion layer portion of the channel region from about p ⁺ gate region away gate electrode force It becomes difficult. Therefore, if a structure in which the channel region width 2a decreases linearly according to the distance from the gate electrode 9 as shown in FIG. 12, the portion of the channel region 3 away from the gate electrode 9 at the time of turn-off of the element is used. Since the current can be sufficiently cut off and the uniform turn-off operation can be realized in the entire channel region 3, the turn-off time can be shortened and the safe operation region of the turn-off operation and the load short-circuit operation can be increased.

The invention's effect

[0037] If the design method of the present invention is applied to SiC-SIT, the channel is more accurate than the conventional design considering the electrostatic induction effect from both the gate electrode and the drain electrode, which is the basic operation of SIT. Can be designed.

[0038] As will be described later, the semiconductor device simulation used in deriving the design method of the normally-on 'EC' SiC-SIT channel structure in the present invention strictly solves the basic equations of the semiconductor, and It contains accurate model equations for the physical properties of SiC materials such as SiC carrier mobility, forbidden bandwidth, and ionization coefficient, and has been shown to be in good agreement with experimental results. 'It is possible to provide an accurate channel structure design method to ensure both SiC-SIT conduction and current cut-off operations.

Furthermore, the input / output breakdown voltage and the switching time can be improved while maintaining the above effects.

Brief Description of Drawings

[0040] FIG. 1 is a diagram showing a design range of N and a of SiC-SIT in the prior art.

ch

[Fig. 2] A diagram showing the range of (a) the combination of a and N and (b) the design range of the set of a and x in the present invention.

ch j

is there.

[Fig. 3] (a) Relationship between characteristic on-resistance and N, and (b) Relationship between breakdown voltage and N in the present invention.

ch ch graph (when χ = 1 μm).

[Fig.4] Normally-on 'EC' SiC-SIT N and a set for x = l x m in the present invention

It is a figure of the Example which determines jch.

FIG. 5 is a cross-sectional view of normally-on “EC” SiC-SIT according to an example of the present invention.

[Fig. 6] Normally on 'EC' SiC-SIT in the case of x = l x m in the present invention.

j

It is a figure of the Example which determines the set of N and a, suppressing the variation in resistance.

ch

[Fig. 7] In the case of χ = 1 μ τη according to the present invention, the normally-on 'EO SiC-SIT

j

It is a figure of the Example which determines the group of N and a, suppressing the variation of a breakdown voltage.

ch

[Fig. 8] ON in normally-on 'EO SiC-SIT in the case of χ = 1 μ τη in the present invention.

j

In the diagram of the embodiment, the set of N and a is determined while suppressing variations in resistance and breakdown voltage.

ch

is there.

FIG. 9 is a cross-sectional view of a normal EC · SiC-SIT that further improves the input capacitance and the input withstand voltage according to an embodiment of the present invention. 10] A sectional view of normally-on 'EC' SiC-SIT that further improves the output withstand voltage according to an embodiment of the present invention.

FIG. 11 is a cross-sectional view of normally-on “EC” SiC-SIT that further improves input capacitance, input withstand voltage, and output withstand voltage according to an embodiment of the present invention.

12] This is a structure that shortens the turn-off time and increases the safe operation region of the turn-off operation and the load short-circuit operation according to the embodiment of the present invention.

Explanation of symbols

1 Drain region

2 Drift region

3 channel region

4 Gate area

5 Low concentration source region

6 High concentration source region

7 Drain electrode

8 Source electrode

9 Gate electrode

10 Insulation area

11 Low concentration N-type region on the source side

12 Low concentration N-type region on the drain side

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Determine the half width a, length x, and donor impurity concentration N of the channel region necessary to realize normally-on 'EC' SiC-SIT with a breakdown voltage of 800-1200V and reliable on-function. You

j ch. For this purpose, if a combination of a and N satisfying the two equations (3) and (4) is determined,

ch

In both cases, it is necessary to determine X that satisfies Eq. (5) when X is less than 4 μπι.

[0043] Here, in Figs. 2 (a) and (b), a straight line 5 that coincides with the condition that the right side of equation (3) indicating the limit on the characteristic on-resistance is equal to a, the limit on the breakdown voltage is shown. If the right side of equation (4) is equal to a, straight line 6 that matches the conditions, right of equation (5) indicating the upper limit of a with respect to breakdown voltage Curve 1 that matches the condition of equal side force ¾ is shown.

[0044] Each limit line shown in Fig. 2 (a) and (b) was obtained by analyzing the conduction and breakdown characteristics of normally-on 'EC' SiC-SIT by semiconductor device simulation. In semiconductor device simulation, the basic equations of semiconductors, the Poisson equation, the electron continuity equation, and the hole continuity equation, are discretized using the finite difference method and solved using the Newton method.

[0045] Especially in the area where electric field concentration occurs and in the channel region that is important for SIT operation, the mesh interval is set finely and devised so that the electrostatic induction effect can be simulated accurately if avalanche breakdown occurs. The The semiconductor material is assumed to have a crystalline structural force of periodic hexagonal SiC (4H-SiC), and in order to obtain accurate simulation results, the physical properties of the material such as carrier mobility, forbidden band width, and ionization coefficient are 4H_SiC experimental data. A fitted model equation is used.

[0046] In order to obtain the limit lines shown in Figs. 2 (a) and (b), first, as shown in Figs. 3 (a) and (b), the channel donor impurity concentration N Characteristic on-resistance and breakdown voltage

ch

Is derived by simulation for various half-channel width a and channel length X conditions.

[0047] In the calculation of Fig. 3 (a), the gate-source voltage VGS is set to 2.5V, which is the input signal for turning on the device, and the drain current density is 200A m ^2. -The characteristic on-resistance RonS is calculated from the source-to-source voltage V DS. The present invention relates to normally-on operation, and is a force that assumes that the element conducts when VGS = 0V. Here, VGS is set to 2.5V. The width of the depletion layer extending in the channel region 3 shown in Fig. 5 is reduced to reduce RonS as much as possible. If VGS is set to 3.0 V or more, holes are injected from the P ⁺ gate region 4 into the channel region 3 and the drift region 2, which may significantly increase the turn-off time. Therefore, VGS is set to 2.5V, which is the upper limit where holes are not injected from the P ⁺ gate region. In the figure (b), V GS = _15V is set to turn off the element. This VGS value is the standard off-voltage of the power device. Here, let χ = 1 μ πι.

[0048] In the relationship diagram of characteristic on-resistance vs. N in Fig. 3 (a), the characteristic is gradually turned on at the beginning as N decreases. It can be seen that the resistance increases. The reason for this is that as N decreases, the P ⁺ gate region

ch

This is because the effective width of the conduction channel, which is a non-depleted region in the channel, gradually decreases because the width of the depletion layer extending to the channel increases.

[0049] Then, it can be confirmed from Fig. 3 (a) that the characteristic on-resistance increases sharply for a certain N.

ch

The This is because the depletion layer from the P ⁺ gate region 4 on both sides of the channel is in contact with the center of the channel region 3 and a potential barrier is formed there, so that the current is significantly reduced. From Fig. 3 (a), the characteristic on-resistance increases sharply at a certain N, especially in the case of a curve below a = 0.65 xm.

ch

You can see that

[0050] In this way, N-force S with a sudden increase in characteristic on-resistance and normally-on 'EC' SiC-SIT are introduced.

ch

It is a lower limit value for passing the element, and it is necessary to design N with a value larger than this lower limit value in order for this element to have a conduction function. The lower limit value depends on a

ch

This can be seen in Fig. 3 (a). Therefore, as a curve of a vs. N lower limit value, a is the vertical axis and N is the horizontal axis.

ch Can be plotted on the log-log plane (hereinafter referred to as a-N log-log plane).

ch

[0051] In Fig. 3 (a), when a is 0.65 μ πι or more, N decreases compared to other curves.

ch

It can be seen that the characteristic on-resistance increases slowly. For this reason, in a is 0.65 μ πι above conditions, the static induction effect from the channel width is relatively large instrument gate P ⁺ region is small compared to the static induction effect from the drain region, N To make the depletion layer width small enough

ch

This is because even when the potential is increased, the potential barrier in the channel region does not become sufficiently high.

[0052] For this reason, the channel current does not decrease so much, and as a result, the characteristic on-resistance with respect to N

ch

The rate of increase slows down. This power is one of the features of SSIT operation.

[0053] As a result, when the above a vs. N lower limit curve is plotted on the a vs. N logarithmic plane, a ch ch

A relatively small value of less than .65 μm results in a straight line with a negative slope, and when a exceeds 0.65 μm, the curve tends to fall gradually, and finally the value of a depends on N. Disappear. in front

ch

Equation (3) expresses the person's straight line area.

[0054] In the relationship diagram of breakdown voltage vs. N in Fig. 3 (b), the breakdown voltage in the case of a of 0.65 μm or less increases rapidly when N ch c is increased. I understand that. This is because the width of the depletion layer extending from the P ⁺ gate region 4 to the channel region 3 decreases due to the increase in N h ch ch, and the potential barrier for blocking current decreases. [0055] The channel impurity concentration when the breakdown voltage rapidly decreases is the upper limit value of the channel impurity concentration for ensuring that the device has an off function. It can be seen from Fig. 3 (b) that the upper limit value decreases as a increases. Therefore, there is one relationship between a and N upper limit values.

ch

It can be plotted as a curve in the logarithmic plane a vs. N.

ch

[0056] In Fig. 3 (b), when a = 0.7 z m, the increase in breakdown voltage is sufficiently observed even if N is decreased.

ch

You can see that it ’s not. This is because, when a = 0.7 xm, the channel width is relatively large, so that the electrostatic induction effect from the P ⁺ gate region is less than that from the drain electrode.

This is because a potential barrier for reliably blocking the current cannot be formed in the channel region even if it is lowered to ch.

[0057] As a result, when the above a vs. N upper limit curve is plotted on the a vs. N logarithmic plane, a ch cn

ch

Equation (4) expresses the person's straight line area.

[0058] Furthermore, as described above, the curve of a vs. N lower limit obtained from Fig. 3 (a) and the curve obtained from Fig. 3 (b).

ch

The electrostatic induction effect due to the drain voltage strongly acts on the curve of the upper limit of a vs. N.

ch

Since there is a limit of 0.7 / i m that does not depend on N

ch

It is necessary to add an upper limit to the design of the channel structure. When the same characteristics as in Fig. 3 (a) and (b) were simulated for values other than X = 1 μm, it was found that the upper limit of this a depends on X. Equation (5) expresses this under the condition of X force / im or less.

[0059] As a result obtained in Figs. 3 (a) and (b), the straight line 5, the straight line 6 and the curved line 1 shown in Figs. 2 (a) and (b) are obtained. Therefore, the combination of a and N that satisfies the conditions of the expressions (3) and (4) of the present invention is determined.

ch

In addition, if X is determined under the condition that the X force is less than μm and satisfies Equation (5), the design method for the channel structure is the range enclosed by lines 5 and 6 in Fig. 2 (a) (however, The point of is not included, and) decides the pair of N and a, and at the same time decides X for the area below curve 1 for this a ch j

Etc.

Example

[0060] Design region 3 in Fig. 4 is a normally-on 'EC' SiC- with a breakdown voltage of 800 to 1200V and capable of conducting and interrupting current when the channel region length X is 1 μm. Create SIT To show the range of a and N pairs. The numerical value that satisfies this condition is, for example,

ch

, Χ = 1 μm, a = 0.5 μm, N = 10 cm.

j ch

[0061] Design region 4 in FIG. 6 has a breakdown voltage of 800 to 1200 V when the length x of the channel region is 1 μm, and can conduct and cut off current. N

The range of a and N pairs for producing normally-on 'EO SiC -SIT to avoid the increase in on-resistance caused by ch variation is shown. The straight line 5 in Fig. 6 represents the equation (3) ch

Is a line showing the design limits of a and N with respect to the characteristic on-resistance corresponding to

Due to variations in a and N that may occur in manufacturing,

ch

It can be seen from Fig. 3 (a) that if it is not satisfied, the characteristic on-resistance will increase suddenly outside the range of design region 3 in Fig. 4. Therefore, in order to avoid this, the range of a and N variations that can occur during manufacturing is considered, and this variation does not affect the characteristic on-resistance.

The new design condition is Equation (6), which corresponds to the straight line 8 in FIG. The region set by this equation and equations (4) and (5) is the design region 4 in FIG. In other words, if a and N are determined in the design area 4 and the device is designed, even if variations in a and N that may occur during manufacturing occur, ch

Still, low on-resistance is guaranteed.

[0062] Design region 5 in FIG. 7 has a breakdown voltage of 800 to 1200 V when the length X of the channel region is 1 μm, and can conduct and cut off current. N

The range of a and N pairs to produce normally-on 'EC' SiC-SIT to avoid the breakdown voltage drop caused by ch variation is shown. The straight line 6 in Fig. 7 is the equation (4) ch

Is a line showing the design limits of a and N for the breakdown voltage corresponding to

ch

The condition of Eq. (4) is satisfied due to variations in a and N that may occur in

ch

It can be seen from Fig. 3 (b) that if this is not the case, it will be outside the range of design region 3 in Fig. 4 and the breakdown voltage will drop rapidly. So to avoid this a and N

ch Considering the range of variation, the design condition in which this variation does not affect the breakdown voltage is Equation (7), which corresponds to line 9. The region set by this equation and equations (3) and (5) is the design region 5 in Fig. 7. In other words, element design can be performed by determining a and N in design area 5.

ch

Even if the a and N variations that may occur during production occur,

The breakdown voltage is guaranteed. [0063] Design region 6 in FIG. 8 has a breakdown voltage of 800 to 1200 V when the length x of the channel region is 1 μm, and can conduct and cut off current. Shows the range of a and N pairs for fabricating normally-on 'EC' SiC-SIT to avoid increased on-resistance and lower breakdown voltage caused by N ch variation

ch

FIGS. 9 to 12 are structural diagrams according to the embodiments of the present invention, and the channel structure design method of the present invention can be applied to these structures.

[0065] FIG. 5 shows a normally-on 'EC' SiC-SIT, in which the P ⁺ gate region 4 is buried under the source low-concentration region 5, the source electrode 8 is placed on the surface of the device, and the gate electrode 9 Is a structure installed around the source electrode 8. Here, when the gate electrode 9 is formed, a groove reaching the buried P ⁺ gate region 4 is formed in a part around the source electrode, and the gate electrode 9 is provided at the bottom of the groove. The channel region 3 is disposed so as to be surrounded by the P ⁺ gate region 4 and is not connected to the gate electrode 9. The channel region 3 is formed by anisotropic trench etching technology and embedding the trench portion by epitaxial growth, and the cross-sectional shape of the p ⁺ gate region is basically a square.

[0066] FIG. 9 shows the N-type impurity concentration lower than the impurity concentration of the N-type channel region 3 on the source region 6 side in contact with the gate p ⁺ region 4 in the normally-on “EC” SiC-SIT shown in FIG. The mold area 11 is provided.

[0067] FIG. 10 shows a lower concentration than the impurity concentration of the N-type channel region 3 on the drain region 1 side in contact with the gate p ⁺ region 4 in the normally-on “EC” SiC-SIT shown in FIG. In this structure, an N-type region 12 is provided.

[0068] FIG. 11 shows the impurity concentration of the N-type channel region 3 on the source region 6 side and the drain region 1 side in contact with the gate p ⁺ region 4 in the normally-on 'EC' SiC-SIT shown in FIG. In this structure, N-type regions 11 and 12 having a lower concentration are provided.

[0069] FIG. 12 shows a linear function of the vertical channel vertical buried gate structure SiC-SIT shown in FIGS. 5, 9, 10, and 11 with the channel region width 2a depending on the distance from the gate electrode 9. It is a structure that has been reduced. The channel structure design method of the present invention described above may be applied to the design of the channel width 2a in these structures. [0070] This book is based on Japanese Patent Application 2005- 191763 filed on June 30, 2005. All this content is included here.

Industrial applicability

[0071] The present invention may be used in a design technique for reducing the loss of a high-power transistor using silicon carbide.

Claims

The scope of the claims

[1] NORLY-ON EPITAXIAL CHANNEL GATE GATE SILICON CARBIDE STATIC INDUCTION TRANSISTOR

(Hereinafter, in the design method of the channel structure of NORION “EC” SiC-SIT), the half channel width a and the channel donor impurity concentration N are set to a N satisfying the conditions of Equation (1) and Equation (2).

ch A channel structure design method characterized by determining a combination of ch and a channel length xj force μm or less and satisfying the condition of Equation (3).

a> 2.10 X 10 ⁷ / ^ N (1)

ch

N is cm— ³ a has units of μ πι.

ch

a <1.72 X 10 ⁸ / ^ N (2)

ch

N is cm— ³ a has units of μ πι.

ch

a <-0.1 + 0.9x-0.1x ² (3)

a and xj have units of μm.

[2] The channel according to claim 1, wherein the equation (1) satisfies a> 3.3 × 10 ⁷ / N.

ch

How to design the structure.

[3] The channel structure according to claim 1, wherein the equation (2) is a 9 × 10 ⁷ / N.

ch

Building design method.

[4] The above formula (1) is a> 3.3 X 10 ⁷ Z ^ TN, and the above formula (2) is a 9 × 10 ⁷ / N.

ch ch

The method for designing a channel structure according to claim 1.

[5] In the non-on 'EC' SiC-SIT created by the channel structure design method according to any one of claims 1 to 4, the impurity concentration of the N-type channel region on the source region side in contact with the gate p ⁺ region SiC_SIT characterized by having a lower concentration N-type region

[6] In the non-on 'EC' SiC-SIT created by the channel structure design method according to any one of claims 1 to 4, the impurity concentration of the N-type channel region on the drain region side in contact with the gate p ⁺ region SiC_SIT characterized by having a lower concentration N-type region

[7] In the non-on 'EC' SiC-SIT created by the channel structure design method according to any one of claims 1 to 4, N-type is formed on the source region side and the drain region side in contact with the gate p ⁺ region. SiC-SIT characterized by providing an N-type region with a lower concentration than the impurity concentration of the channel region In normally-on 'EC' SiC-SIT created by the channel structure design method according to any one of claims 1 to 4, the channel region width decreases linearly according to the distance from the gate electrode. SiC-SIT characterized by

A power conversion device including a normally-on · EC · SiC-SIT according to any one of claims 5 to 8.