JP5196513B2 - Silicon carbide transistor device - Google Patents
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims description 63
- 229910010271 silicon carbide Inorganic materials 0.000 title claims description 63
- 239000012535 impurity Substances 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 35
- 238000005468 ion implantation Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 11
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 34
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 34
- 230000015556 catabolic process Effects 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 7
- 230000006698 induction Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000001459 lithography Methods 0.000 description 5
- 238000005036 potential barrier Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 108091006146 Channels Proteins 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000011261 inert gas Substances 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
- H01L29/8083—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1058—Channel region of field-effect devices of field-effect transistors with PN junction gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Description
本発明は、炭化珪素を用いたトランジスタ装置に関する。
The present invention relates to a transistor device using silicon carbide.
炭化珪素はシリコンと比較してバンドギャップが広く絶縁破壊電界強度が１０倍以上大きい事から、特にパワー半導体素子の分野でシリコンに置き換わるべき新しい半導体材料として注目されている。特に、その応用範囲の広さから実現が期待されている炭化珪素ユニポーラ型スイッチング素子としては金属-酸化膜-半導体型トランジスタ（ＭＯＳＦＥＴ）、及び静電誘導型トランジスタ（ＳＩＴ又はＪＦＥＴ）が挙げられるが、ＭＯＳＦＥＴは酸化膜/半導体界面の高い界面準位密度の影響でチャネル部分の抵抗が非常に高い事が大きな問題となっている。一方、ＳＩＴは固体中にチャネルが形成されることから、炭化珪素中の高い電子移動度（〜９００ｃｍ２／Ｖｓ）をそのまま生かすことが出来るため、炭化珪素の物性限界に近い低オン抵抗化が可能であると期待されている。 Silicon carbide has attracted attention as a new semiconductor material that should replace silicon, particularly in the field of power semiconductor devices, because it has a wider band gap and a dielectric breakdown electric field strength that is 10 times greater than silicon. In particular, examples of silicon carbide unipolar switching elements expected to be realized due to their wide range of applications include metal-oxide-semiconductor transistors (MOSFETs) and electrostatic induction transistors (SIT or JFET). The MOSFET has a big problem that the resistance of the channel portion is very high due to the influence of the high interface state density at the oxide film / semiconductor interface. On the other hand, since SIT forms a channel in a solid, the high electron mobility (˜900 cm 2 / Vs) in silicon carbide can be utilized as it is, so that the low on-resistance close to the physical property limit of silicon carbide is achieved. It is expected to be possible.
図３は従来試みられてきた静電誘導型炭化珪素トランジスタ装置の基本構造である。高濃度ｎ型炭化珪素基板（２２）上に、エピタキシャル成長により低濃度ｎ型層（２３）を形成する。その後、アルミニウム（Ａｌ）又はホウ素（Ｂ）等のｐ型不純物を、マスク材を使用して選択的にイオン注入することにより互いに離間した高濃度ｐ型ゲート領域（２４）を形成する。この際、前記低濃度ｎ型層（２３）の内、前記ｐ型ゲート領域（２４）の深さｄを除いた領域（深さｅの領域）を低濃度ｎ型ドリフト層（３０）とすると、該領域（３０）の不純物濃度、及び厚さｅによりデバイスの耐圧特性が決定される。 FIG. 3 shows a basic structure of an electrostatic induction type silicon carbide transistor device which has been conventionally tried. A low concentration n-type layer (23) is formed by epitaxial growth on the high concentration n-type silicon carbide substrate (22). Thereafter, a p-type impurity such as aluminum (Al) or boron (B) is selectively ion-implanted using a mask material to form a high-concentration p-type gate region (24) separated from each other. At this time, if a region (region of depth e) excluding the depth d of the p-type gate region (24) in the low-concentration n-type layer (23) is a low-concentration n-type drift layer (30). The breakdown voltage characteristics of the device are determined by the impurity concentration of the region (30) and the thickness e.
次に、リン（Ｐ）又は窒素（Ｎ）等のｎ型不純物を選択的にイオン注入することにより高濃度ｎ型ソース領域（２５）を形成する。イオン注入により形成された前記高濃度ｐ型ゲート領域（２４）、及び前記高濃度ｎ型ソース領域（２５）は１６００℃以上の高温処理により電気的に活性化される。この際、前記低濃度ｎ型層（３０）の内、互いに離間した前記高濃度ｐ型ゲート領域（２４）に挟まれ、且つ前記高濃度ｎ型ソース領域（２５）の直下のｎ型領域を低濃度ｎ型チャネル領域（２７）とすると、該領域（２７）において互いに離間した前記高濃度ｐ型ゲート領域（２４）から伸びる空乏層によりドレイン電極（２１）からソース電極（２６）に流れる電流量を調整することが出来る。 Next, an n-type impurity such as phosphorus (P) or nitrogen (N) is selectively ion-implanted to form a high concentration n-type source region (25). The high-concentration p-type gate region (24) and the high-concentration n-type source region (25) formed by ion implantation are electrically activated by high-temperature treatment at 1600 ° C. or higher. At this time, the n-type region sandwiched between the high-concentration p-type gate regions (24) that are spaced apart from each other in the low-concentration n-type layer (30) and immediately below the high-concentration n-type source region (25) is formed. If the low-concentration n-type channel region (27) is used, the current flowing from the drain electrode (21) to the source electrode (26) due to the depletion layer extending from the high-concentration p-type gate region (24) spaced apart from each other in the region (27). The amount can be adjusted.
その後、前記高濃度ｐ型ゲート領域（２４）、及び前記高濃度ｎ型ソース領域（２５）を電気的に分離するためＳｉＯ２等の絶縁膜（２９）を堆積し、リソグラフィーにより前記高濃度ｎ型ソース領域（２５）の直上、及び高濃度ｐ型ゲート領域（２４）の直上に開口部を開け、それぞれ前記ソース電極（２６）、及びゲート電極（２８）を形成し、更に高濃度ｎ型基板（２２）の裏面側に前記ドレイン電極（２１）を形成させることにより、従来型の静電誘導型炭化珪素トランジスタが完成する。 Thereafter, an insulating film (29) such as SiO 2 is deposited to electrically isolate the high-concentration p-type gate region (24) and the high-concentration n-type source region (25), and the high-concentration n is formed by lithography. An opening is formed immediately above the p-type source region (25) and directly above the high-concentration p-type gate region (24) to form the source electrode (26) and the gate electrode (28), respectively, and a high-concentration n-type By forming the drain electrode (21) on the back side of the substrate (22), a conventional static induction silicon carbide transistor is completed.
図３にあるような従来型の静電誘導型炭化珪素トランジスタ装置では、その電気的特性、及び製造プロセスにおいて多くの問題点を有している。 The conventional static induction silicon carbide transistor device as shown in FIG. 3 has many problems in its electrical characteristics and manufacturing process.
（第１の問題点）基本的に静電誘導型炭化珪素トランジスタ装置では、ゲート電極（２８）に負バイアス（ノーマリオフ型の場合は零電位）を印可することにより、高濃度ｐ型ゲート領域（２４）から低濃度ｎ型チャネル領域（２７）中に空乏層を伸ばし、電位障壁を形成することによりドレイン電極（２１）からソース電極（２６）への電流を遮断する。この際、前記低濃度ｎ型チャネル領域（２７）に十分な電位障壁が形成されない状況では、十分なブロッキング特性（逆漏れ電流や耐圧特性）を得ることが出来ない。 (First Problem) Basically, in an electrostatic induction silicon carbide transistor device, a high-concentration p-type gate region (by applying a negative bias to the gate electrode (28) (zero potential in the case of a normally-off type)) ( 24) extends the depletion layer into the low-concentration n-type channel region (27) and forms a potential barrier to cut off the current from the drain electrode (21) to the source electrode (26). At this time, in a situation where a sufficient potential barrier is not formed in the low-concentration n-type channel region (27), sufficient blocking characteristics (reverse leakage current and breakdown voltage characteristics) cannot be obtained.
図３の様な従来型の静電誘導型炭化珪素トランジスタ装置では、十分なブロッキング特性を得るためには前記高濃度ｐ型ゲート領域（２４）の深さｄを1mm以上確保し、高い電位障壁を形成する必要がある。しかし、このような深いゲート層を形成するためには、現状ではほとんど市販されておらず、且つ非常に高価なメガボルト級のイオン注入装置を導入する必要があり、結果的にデバイス作製コストを大幅に押し上げる要因となる。 In the conventional static induction type silicon carbide transistor device as shown in FIG. 3, in order to obtain sufficient blocking characteristics, the depth d of the high-concentration p-type gate region (24) is secured to 1 mm or more and a high potential barrier is provided. Need to form. However, in order to form such a deep gate layer, it is necessary to introduce a very expensive megavolt-class ion implantation apparatus that is hardly commercially available at present, resulting in a significant increase in device fabrication cost. It becomes a factor to push up to.
また、イオン注入する際のマスク材も高エネルギーに耐え得る材料を、その加工性を考慮した上で選定する必要があり大きな問題となる。更には、該構造のように高エネルギーで深い領域にイオン注入された不純物の分布は横方向にも大きく広がるため不純物分布の的確な制御が非常に困難であり、特にデバイスのオン特性を向上させるためにデバイスサイズを微細化した際に大きな障害となる。 Moreover, it is necessary to select a material that can withstand high energy in consideration of its workability as a mask material for ion implantation, which is a serious problem. Furthermore, since the distribution of impurities implanted into a deep region with high energy as in the structure is wide in the lateral direction, it is very difficult to accurately control the impurity distribution, and in particular, the on-characteristics of the device are improved. Therefore, it becomes a big obstacle when the device size is miniaturized.
（第２の問題点）該構造ではソース電極（２６）とゲート電極（２８）をそれぞれ高濃度ｎ型ソース領域（２５）、及び高濃度ｐ型ゲート領域（２４）の直上に形成するため、パターニングの露光合わせ精度、及び確実なオーミック電極の形成等を考慮すると、前記高濃度ｎ型ソース領域（２５）と前記高濃度ｐ型ゲート領域（２４）の間隔aや、前記高濃度ｎ型ソース領域（２５）の幅b、前記高濃度ｐ型ゲート領域（２４）の幅cに余裕を持たせてデバイス設計を行う必要があり、自ずとデバイスの微細化に制限が加えられる。デバイスの微細化は、デバイスのオン特性の改善に直接繋がるため、該構造では炭化珪素の持つ優れた物理限界に迫るような電気特性を実現することは困難である。 (Second Problem) In this structure, the source electrode (26) and the gate electrode (28) are formed immediately above the high-concentration n-type source region (25) and the high-concentration p-type gate region (24), respectively. Considering the exposure alignment accuracy of patterning and the formation of a reliable ohmic electrode, the distance a between the high-concentration n-type source region (25) and the high-concentration p-type gate region (24) and the high-concentration n-type source It is necessary to design the device with a margin for the width b of the region (25) and the width c of the high-concentration p-type gate region (24), which naturally limits the miniaturization of the device. Since device miniaturization directly leads to improvement of the on-characteristics of the device, it is difficult to realize electrical characteristics that approach the excellent physical limits of silicon carbide in this structure.
（第３の問題点）該構造において低濃度ｎ型ドリフト層（３０）と低濃度ｎ型チャネル領域（２７）は、同一のエピタキシャル成長工程で形成されるため同一の不純物濃度を有している。一般的にデバイスの耐圧特性は、前記低濃度ｎ型ドリフト層（３０）の厚みｅと不純物濃度により決定される。一方、デバイスのブロッキングゲイン（耐圧／デバイスを完全にオフにするために必要なゲート電圧）やオン特性は、前記低濃度ｎ型チャネル領域（２７）の厚みと不純物濃度に依存する。つまり、該構造のように、前記低濃度ｎ型ドリフト層（３０）と前記低濃度ｎ型チャネル領域（２７）が同一不純物濃度を有している場合は、耐圧とブロッキングゲイン、及びオン特性のデバイス設計を独立に行うことが出来ない。例えば、前記低濃度ｎ型チャネル領域（２７）の不純物濃度を前記低濃度ｎ型ドリフト層（３０）の不純物濃度よりも低濃度にしてブロッキング特性を向上させ、ノーマリオフ特性を実現するような工夫を行うことは不可能であり、デバイス設計の自由度が限定されてしまう。 (Third Problem) In this structure, the low-concentration n-type drift layer (30) and the low-concentration n-type channel region (27) have the same impurity concentration because they are formed in the same epitaxial growth step. Generally, the breakdown voltage characteristics of the device are determined by the thickness e and the impurity concentration of the low-concentration n-type drift layer (30). On the other hand, the device blocking gain (breakdown voltage / gate voltage required to completely turn off the device) and on-state characteristics depend on the thickness and impurity concentration of the low-concentration n-type channel region (27). That is, when the low-concentration n-type drift layer (30) and the low-concentration n-type channel region (27) have the same impurity concentration as in this structure, the breakdown voltage, the blocking gain, and the on-characteristics Device design cannot be done independently. For example, the low concentration n-type channel region (27) has an impurity concentration lower than the impurity concentration of the low concentration n-type drift layer (30) to improve the blocking characteristics and realize a normally-off characteristic. This is impossible and limits the degree of freedom in device design.
特許文献１に記載された炭化珪素半導体装置の断面構造図を図８に示す。該半導体装置は、高濃度ｐ型ゲート領域（４３及び４４）、低濃度ｎ型チャネル領域（４６）、及び高濃度ｎ型ソース領域（４７）をすべてエピタキシャル成長で形成することを特徴としており、この事によりイオン注入により発生する結晶欠陥起因のビルトインポテンシャル低下を防ぐことを目的として提案されているが、付加的な長所として前述した３つの問題点を解決できる可能性がある。 FIG. 8 shows a cross-sectional structure diagram of the silicon carbide semiconductor device described in Patent Document 1. In FIG. The semiconductor device is characterized in that the high-concentration p-type gate region (43 and 44), the low-concentration n-type channel region (46), and the high-concentration n-type source region (47) are all formed by epitaxial growth. Although it has been proposed for the purpose of preventing the built-in potential from being lowered due to crystal defects caused by ion implantation, the above three problems may be solved as an additional advantage.
しかし、該半導体装置はデバイス特性を改善する上で大きな問題点を有している。まず第１に、前記高濃度ｎ型ソース領域（４６）をエピタキシャル成長で形成するために、該領域（４６）の抵抗値を十分下げることが出来ず、結果的にデバイスのオン特性を大幅に劣化させてしまうと言う問題点がある。エピタキシャル成長ではｎ型不純物濃度はせいぜい1019/cm3程度しか導入できないため、前記高濃度ｎ型ソース領域（４６）のシート抵抗を十分に低下させることは不可能である。また、エピタキシャル成長により高濃度ｎ型層の不純物濃度を精密に制御することは非常に困難であると言う問題点も有している。 However, the semiconductor device has a big problem in improving device characteristics. First, since the high-concentration n-type source region (46) is formed by epitaxial growth, the resistance value of the region (46) cannot be lowered sufficiently, resulting in a significant deterioration in the on-characteristics of the device. There is a problem of letting it go. In epitaxial growth, since the n-type impurity concentration can be introduced only about 10 19 / cm 3 at most, it is impossible to sufficiently reduce the sheet resistance of the high-concentration n-type source region (46). Further, there is a problem that it is very difficult to precisely control the impurity concentration of the high-concentration n-type layer by epitaxial growth.
第２に、該半導体装置ではゲート・ソース間の耐圧特性を上げるために、低濃度ｎ型チャネル領域（４６）から高濃度ｎ型ソース領域（４７）に向かって、連続的に不純物濃度が高くなる様に構成されているが、この様な不純物濃度の精密な制御は非常に困難であり、再現性良くエピタキシャル成長を行うことは極めて困難である。 Second, in the semiconductor device, in order to increase the gate-source breakdown voltage characteristics, the impurity concentration increases continuously from the low-concentration n-type channel region (46) toward the high-concentration n-type source region (47). However, precise control of such impurity concentration is very difficult, and it is extremely difficult to perform epitaxial growth with good reproducibility.
以上のように、従来の構造（図３）や特許文献１に記載の半導体装置（図８）では、炭化珪素の持つ優れた物理限界に迫るような電気特性をもつ炭化珪素トランジスタ装置を実現するのは極めて困難である。
本発明では、以上挙げたような問題点を克服し、容易にデバイスサイズを微細化し、デバイスのオン特性を改善することが出来る炭化珪素トランジスタ装置及びその製造方法を提供することを目的とする。 An object of the present invention is to provide a silicon carbide transistor device and a method for manufacturing the same that can overcome the above-described problems, easily reduce the device size, and improve the on-characteristics of the device.
上記のような目的を達成するために、請求項１に記載の炭化珪素トランジスタ装置では、高濃度ｎ型炭化珪素基板と、該高濃度ｎ型炭化珪素基板表面上にエピタキシャル成長により形成された低濃度ｎ型ドリフト層と、該低濃度ｎ型ドリフト層上にエピタキシャル成長により形成され、互いに離間した複数の高濃度ｐ型ゲート領域と、同一のエピタキシャル成長工程により同一不純物濃度を有し、且つ前記低濃度ｎ型ドリフト層よりも不純物濃度が低くなる様に形成され、互いに隣り合った前記高濃度ｐ型ゲート領域の間に位置するチャネル領域及び、ゲート電極が形成される領域を除いた前記高濃度ｐ型ゲート領域の全面を覆うように形成された低濃度ｎ型領域と、該低濃度ｎ型領域上にあってｎ型不純物イオン注入により形成された高濃度ｎ型ソース領域と、該高濃度ｎ型ソース領域上に形成されたソース電極、前記高濃度ｎ型炭化珪素基板の裏面に形成されたドレイン電極、及び前記高濃度ｐ型ゲート領域に電気的に接続されたゲート電極から構成されていることを特徴としている。 In order to achieve the above object, in the silicon carbide transistor device according to claim 1, a high concentration n-type silicon carbide substrate and a low concentration formed by epitaxial growth on the surface of the high concentration n-type silicon carbide substrate. An n-type drift layer, a plurality of high-concentration p-type gate regions formed by epitaxial growth on the low-concentration n-type drift layer , spaced apart from each other, and having the same impurity concentration by the same epitaxial growth process, and the low-concentration n The high-concentration p-type except for the channel region formed between the adjacent high-concentration p-type gate regions and the region where the gate electrode is formed. A low-concentration n-type region formed so as to cover the entire surface of the gate region, and a high-concentration region formed on the low-concentration n-type region by n-type impurity ion implantation An n-type source region, a source electrode formed on the high-concentration n-type source region, a drain electrode formed on the back surface of the high-concentration n-type silicon carbide substrate, and the high-concentration p-type gate region are electrically connected It is characterized by being composed of connected gate electrodes.
この様に、高濃度ｐ型ゲート領域（４）を完全に埋め込んでしまう構造を実現することにより、図３に示す従来型のＳＩＴに必要な露光合わせ精度や余分な設計マージンを取る必要が無く、デバイスの極限までの微細化が初めて可能となる。また、高濃度ｎ型ソース領域（５）をイオン注入により形成することにより、制御性良く該領域（５）の不純物導入を行うことが出来る上に、エピタキシャル成長で該領域（５）を形成するよりも一桁以上シート抵抗値を下げることが可能となり、結果的にデバイスのオン特性の大幅な改善が可能となる。また、低濃度ｎ型チャネル領域（７）と低濃度ｎ型領域１（９）を同一のエピタキシャル成長工程で、同一不純物濃度を有する様に形成することにより、エピタキシャル成長中に精密な不純物制御を行う必要が無く、デバイスプロセスの大幅な簡素化が可能となる。
さらに、この様に、低濃度ｎ型チャネル領域（７）の不純物濃度を、低濃度ｎ型ドリフト層（３）の不純物濃度よりも低くすることによって、デバイスの耐圧設計とは独立してブロッキングゲインを向上させることが可能となり、究極的にノーマリオフ特性を実現することが可能となる。
In this way, by realizing a structure in which the high-concentration p-type gate region (4) is completely buried, it is not necessary to provide exposure alignment accuracy and an extra design margin necessary for the conventional SIT shown in FIG. For the first time, miniaturization to the limit of the device becomes possible. Further, by forming the high-concentration n-type source region (5) by ion implantation, impurities can be introduced into the region (5) with good controllability, and the region (5) is formed by epitaxial growth. In addition, the sheet resistance value can be lowered by one digit or more, and as a result, the on-characteristics of the device can be greatly improved. In addition, it is necessary to perform precise impurity control during epitaxial growth by forming the low-concentration n-type channel region (7) and the low-concentration n-type region 1 (9) in the same epitaxial growth step so as to have the same impurity concentration. This makes it possible to greatly simplify the device process.
Further, by making the impurity concentration of the low-concentration n-type channel region (7) lower than the impurity concentration of the low-concentration n-type drift layer (3) in this way, the blocking gain is independent of the device withstand voltage design. Thus, it is possible to ultimately realize normally-off characteristics.
請求項２に記載の炭化珪素トランジスタ装置では、請求項１に記載の炭化珪素トランジスタ装置において、高濃度ｎ型炭化珪素基板として（０００１）面、又は（０００−１）面から傾斜した表面を有する六方晶系炭化珪素基板を使用し、互いに離間した複数の高濃度ｐ型ゲート領域の長手方向が、前記高濃度ｎ型炭化珪素基板の傾き方向に対して平行になるように配置されたことを特徴としている。
In the silicon carbide transistor device according to claim 2 , in the silicon carbide transistor device according to claim 1, the high-concentration n-type silicon carbide substrate has a (0001) plane or a surface inclined from the (000-1) plane. A hexagonal silicon carbide substrate is used, and the plurality of high-concentration p-type gate regions spaced apart from each other are arranged so that the longitudinal directions thereof are parallel to the tilt direction of the high-concentration n-type silicon carbide substrate. It is a feature.
これにより、前記低濃度ｎ型チャネル領域（７）と、前記高濃度ｐ型ゲート領域（４）及び前記低濃度ｎ型チャネル領域（７）上部の低濃度ｎ型領域１（９）をエピタキシャル成長により形成する際に、オフ基板成長特有のファセット成長を抑制したエピタキシャル成長が可能となり、デバイス通電時の電流集中等の問題点を解決することが出来る。 Thus, the low-concentration n-type channel region (7), the high-concentration p-type gate region (4), and the low-concentration n-type region 1 (9) above the low-concentration n-type channel region (7) are epitaxially grown. At the time of formation, epitaxial growth can be performed while suppressing facet growth peculiar to off-substrate growth, and problems such as current concentration during device energization can be solved.
本発明では、高濃度ｐ型ゲート領域を完全に埋め込んでしまう構造を実現することにより、従来型の炭化珪素トランジスタに必要な露光合わせ精度や余分な設計マージンを取る必要が無くなるため、デバイスの極限までの微細化が可能となり、デバイスのオン特性が大幅に改善される。また、高濃度ｎ型ソース領域をイオン注入により形成することにより、更なるオン特性の改善が可能となる。また、低濃度ｎ型ドリフト層と低濃度ｎ型チャネル領域の不純物濃度を操作することによりノーマリオンからノーマリオフへの幅広いデバイス設計が可能となる。 In the present invention, by realizing a structure in which the high-concentration p-type gate region is completely buried, it is not necessary to take exposure alignment accuracy and an extra design margin necessary for a conventional silicon carbide transistor. The on-characteristics of the device are greatly improved. Further, by forming the high-concentration n-type source region by ion implantation, the on-characteristics can be further improved. In addition, it is possible to design a wide range of devices from normally-on to normally-off by manipulating the impurity concentration of the low-concentration n-type drift layer and the low-concentration n-type channel region.
以下、本発明に係わる炭化珪素トランジスタ装置、及びその製造方法の実施例を説明する。 Embodiments of a silicon carbide transistor device and a manufacturing method thereof according to the present invention will be described below.
第１実施例として、図１に炭化珪素トランジスタ装置の断面構造を示す。以下、図１に従って炭化珪素トランジスタ装置の構成について説明する。 As a first embodiment, FIG. 1 shows a cross-sectional structure of a silicon carbide transistor device. Hereinafter, the structure of the silicon carbide transistor device will be described with reference to FIG.
該炭化珪素トランジスタ装置には、例えば1.0x1018〜1.0x1020/cm3の不純物濃度を有するｎ型炭化珪素基板（２）上に、例えば1.0x1014/cm3〜1.0x1017/cm3の不純物濃度を有するｎ型ドリフト層（３）が備えられている。前記ｎ型ドリフト層（３）の直上には互いに離間した、例えば1.0x1017/cm3〜1.0x1020/cm3の不純物濃度を有するｐ型ゲート領域（４）、及び互いに隣り合った前記ｐ型ゲート領域（４）の間にエピタキシャル成長により形成された、例えば1.0x1014/cm3〜1.0x1017/cm3の不純物濃度を有するｎ型チャネル領域（７）が備えられ、更に、前記ｐ型ゲート領域（４）及び前記ｎ型チャネル領域（７）の直上に前記ｎ型チャネル領域（７）と同じ不純物濃度を有する低濃度ｎ型領域１（９）が備えられている。 The silicon carbide transistor devices, for example, 1.0x10 18 ~1.0x10 20 / cm 3 on the n-type silicon carbide substrate (2) having an impurity concentration of, for example, of 1.0x10 14 / cm 3 ~1.0x10 17 / cm 3 An n-type drift layer (3) having an impurity concentration is provided. A p-type gate region (4) having an impurity concentration of, for example, 1.0 × 10 17 / cm 3 to 1.0 × 10 20 / cm 3 separated from each other immediately above the n-type drift layer (3), and the p adjacent to each other. An n-type channel region (7) having an impurity concentration of, for example, 1.0 × 10 14 / cm 3 to 1.0 × 10 17 / cm 3 formed by epitaxial growth between the type gate regions (4) is provided. A low concentration n-type region 1 (9) having the same impurity concentration as that of the n-type channel region (7) is provided immediately above the gate region (4) and the n-type channel region (7).
前記ｎ型チャネル領域（７）、及び前記低濃度ｎ型領域１（９）は図４に示す様に、トレンチ構造上へのエピタキシャル成長により同時に形成され、同一の不純物濃度を有している。ここで、前記ｎ型ドリフト層（３）の不純物濃度と、前記ｎ型チャネル領域（７）及び低濃度ｎ型領域１（９）の不純物濃度がほぼ同じであっても良い。この場合は、エピタキシャル成長の成長条件を全く同じに出来るためプロセスが容易になる利点がある。前記低濃度ｎ型領域１（９）の直上にはｎ型不純物のイオン注入により形成された、例えば1.0x1019/cm3〜1.0x1021/cm3の不純物濃度を有するｎ型ソース領域（５）が備えられている。前記ｎ型ソース領域（５）上にはソース電極（６）が、前記ｎ型炭化珪素基板（２）の裏側にはドレイン電極（１）が備えられている。 As shown in FIG. 4, the n-type channel region (7) and the low-concentration n-type region 1 (9) are simultaneously formed by epitaxial growth on the trench structure and have the same impurity concentration. Here, the impurity concentration of the n-type drift layer (3) may be substantially the same as the impurity concentration of the n-type channel region (7) and the low-concentration n-type region 1 (9). In this case, since the growth conditions for epitaxial growth can be made exactly the same, there is an advantage that the process becomes easy. An n-type source region (5) having an impurity concentration of, for example, 1.0 × 10 19 / cm 3 to 1.0 × 10 21 / cm 3 formed by ion implantation of n-type impurities immediately above the low-concentration n-type region 1 (9). ) Is provided. A source electrode (6) is provided on the n-type source region (5), and a drain electrode (1) is provided on the back side of the n-type silicon carbide substrate (2).
また、図１（ｂ）は図１（ａ）に対して紙面に垂直な方向の断面を示した図であるが、図１（ｂ）に示す様にデバイスセルの外部において前記ｎ型ソース領域（５）、及び前記低濃度ｎ型領域１（９）を例えばドライエッチング法により除去し前記ｐ型ゲート領域を最表面に露出させた領域にゲート電極（８）が備えられている。 FIG. 1B is a view showing a cross section in a direction perpendicular to the plane of FIG. 1A, but the n-type source region is outside the device cell as shown in FIG. The gate electrode (8) is provided in the region where the low-concentration n-type region 1 (9) is removed by, for example, dry etching and the p-type gate region is exposed on the outermost surface.
該構造において、前記ゲート電極（８）に負バイアスを印可することにより、前記ｐ型ゲート領域（４）より空乏層が伸び、前記ｎ型チャネル領域（７）に電位障壁が形成され、ドレイン電極（１）からソース電極（６）へ流れる電流が遮断される。一方、前記ゲート電極（８）に正バイアスを印可することにより、空乏層による電位障壁は形成されないため電流が流れる。つまり、ゲートバイアスにより電流量を調整することが出来る。 In this structure, by applying a negative bias to the gate electrode (8), a depletion layer extends from the p-type gate region (4), a potential barrier is formed in the n-type channel region (7), and a drain electrode Current flowing from (1) to the source electrode (6) is interrupted. On the other hand, by applying a positive bias to the gate electrode (8), a potential barrier is not formed by the depletion layer, so that a current flows. That is, the amount of current can be adjusted by the gate bias.
次に、図１に示す炭化珪素トランジスタ装置の製造方法の一例について、図５に示す製造工程に従って説明する。 Next, an example of a method for manufacturing the silicon carbide transistor device shown in FIG. 1 will be described in accordance with the manufacturing process shown in FIG.
図５（ａ）の工程において、高濃度ｎ型炭化珪素基板（２）上に低濃度ｎ型ドリフト層（３）をエピタキシャル成長により形成する。この際、前記低濃度ｎ型ドリフト層（３）の厚みと不純物濃度はデバイスの耐圧設計により決定される。更に、前記低濃度ｎ型ドリフト層（３）上にエピタキシャル成長により高濃度ｐ型層（１０）を形成する。 5A, a low-concentration n-type drift layer (3) is formed by epitaxial growth on a high-concentration n-type silicon carbide substrate (2). At this time, the thickness and impurity concentration of the low-concentration n-type drift layer (3) are determined by the breakdown voltage design of the device. Further, a high concentration p-type layer (10) is formed on the low concentration n-type drift layer (3) by epitaxial growth.
図５（ｂ）の工程において、前記高濃度ｐ型層（１０）上に金属又はＳｉＯ２等のエッチングマスク材を積層し、次工程である図５（ｃ）のエピタキシャル成長工程において低濃度ｎ型チャネル領域（７）が形成される部分のみをリソグラフィーにより開口し、該開口部を前記低濃度ｎ型ドリフト層（３）の最表面が露出するまでドライエッチングを行う。これにより、互いに離間した高濃度ｐ型ゲート領域（４）が形成される。この際、前記高濃度ｎ型炭化珪素基板（２）として、（０００１）面、又は（０００−１）面から傾斜した表面を有する六方晶型炭化珪素基板を使用する場合、前記高濃度ｐ型ゲート領域（４）の長手方向が、前記高濃度ｎ型炭化珪素基板（２）のオフ方向に対して平行になる様にエッチングを行っても良い。 In the step of FIG. 5B, an etching mask material such as metal or SiO 2 is laminated on the high-concentration p-type layer (10), and in the epitaxial growth step of FIG. Only a portion where the channel region (7) is formed is opened by lithography, and dry etching is performed on the opening until the outermost surface of the low-concentration n-type drift layer (3) is exposed. As a result, high-concentration p-type gate regions (4) separated from each other are formed. At this time, when a hexagonal silicon carbide substrate having a surface inclined from the (0001) plane or the (000-1) plane is used as the high-concentration n-type silicon carbide substrate (2), the high-concentration p-type is used. Etching may be performed so that the longitudinal direction of the gate region (4) is parallel to the off direction of the high-concentration n-type silicon carbide substrate (2).
もし図７（ａ）の工程の様に、前記高濃度ｐ型ゲート領域（４）の長手方向が、前記高濃度ｎ型炭化珪素基板（２）のオフ方向に対して垂直になる様にエッチングした場合、次工程の低濃度ｎ型チャネル領域（７）及び低濃度ｎ型領域２（１１）をエピタキシャル成長させる際に、図７（ｂ）に示す様な、前記高濃度ｎ型炭化珪素基板（２）のオフ角に準じたｃ面ファセット成長が起こり、左右非対称な構造が形成される。この様な構造上にデバイスを作製した場合、デバイスの動作中に電流パスの不均一性から電流集中が発生しやすくなり、良好なデバイス特性が得られない。 If the high-concentration p-type gate region (4) has a longitudinal direction perpendicular to the off-direction of the high-concentration n-type silicon carbide substrate (2) as in the step of FIG. In this case, when the low-concentration n-type channel region (7) and the low-concentration n-type region 2 (11) in the next step are epitaxially grown, the high-concentration n-type silicon carbide substrate (as shown in FIG. The c-plane facet growth according to the off-angle of 2) occurs, and a left-right asymmetric structure is formed. When a device is manufactured on such a structure, current concentration is likely to occur due to current path non-uniformity during device operation, and good device characteristics cannot be obtained.
一方、図７（ｃ）の工程の様に、前記高濃度ｐ型ゲート領域（４）の長手方向が、前記高濃度ｎ型炭化珪素基板（２）のオフ方向に対して平行になる様にエッチングした場合、次工程のエピタキシャル成長工程において、図７（ｄ）に示す様にｃ面ファセット成長は起こらず、左右対称の構造が得られる。この様な構造の場合、デバイスの動作中に電流集中は起こらず、良好なデバイス特性が得られる。 On the other hand, as in the step of FIG. 7C, the longitudinal direction of the high-concentration p-type gate region (4) is parallel to the off direction of the high-concentration n-type silicon carbide substrate (2). When etching is performed, in the next epitaxial growth step, c-plane facet growth does not occur as shown in FIG. 7D, and a symmetrical structure is obtained. In such a structure, current concentration does not occur during device operation, and good device characteristics can be obtained.
図５（ｃ）の工程において、前工程において形成されたトレンチ構造上、及びデバイスセル外のエッチングされずに残った前記高濃度ｐ型層（１０）上に、エピタキシャル成長により低濃度ｎ型チャネル領域（７）及び低濃度ｎ型領域２（１１）を形成する。図４に示す様に前記低濃度ｎ型チャネル領域（７）及び前記低濃度ｎ型領域２（１１）は同一のエピタキシャル成長工程で形成されるため、同一の不純物濃度を有している。前記低濃度ｎ型領域２（１１）は、次々工程である図５（ｅ）のイオン注入工程において、高濃度ｎ型ソース領域（５）と低濃度ｎ型領域１（９）に分割される。 In the step of FIG. 5C, the low-concentration n-type channel region is formed by epitaxial growth on the trench structure formed in the previous step and on the high-concentration p-type layer (10) remaining outside the device cell without being etched. (7) and the low concentration n-type region 2 (11) are formed. As shown in FIG. 4, since the low concentration n-type channel region (7) and the low concentration n-type region 2 (11) are formed in the same epitaxial growth process, they have the same impurity concentration. The low-concentration n-type region 2 (11) is divided into a high-concentration n-type source region (5) and a low-concentration n-type region 1 (9) in the ion implantation step shown in FIG. .
この際、前記低濃度ｎ型チャネル領域（７）及び前記低濃度ｎ型領域１（９）の不純物濃度と、前記低濃度ｎ型ドリフト層（３）の不純物濃度がほぼ同じであっても良い。これにより、低濃度ｎ型ドリフト層（３）と全く同じ条件で、前記低濃度ｎ型チャネル領域（７）と前記低濃度ｎ型領域１（９）を作製することが出来るため、製造工程が簡略化される。 At this time, the impurity concentration of the low-concentration n-type channel region (7) and the low-concentration n-type region 1 (9) may be substantially the same as the impurity concentration of the low-concentration n-type drift layer (3). . Thus, the low concentration n-type channel region (7) and the low concentration n-type region 1 (9) can be manufactured under exactly the same conditions as the low concentration n-type drift layer (3). Simplified.
また、前記低濃度ｎ型チャネル領域（７）及び前記低濃度ｎ型領域１（９）の不純物濃度が、前記低濃度ｎ型ドリフト層（３）の不純物濃度よりも低くても良い。これにより、デバイスの耐圧設計とは独立してブロッキングゲインを向上させることが可能となり、究極的にノーマリオフ特性を実現することが可能となる。 The impurity concentration of the low concentration n-type channel region (7) and the low concentration n-type region 1 (9) may be lower than the impurity concentration of the low concentration n-type drift layer (3). As a result, the blocking gain can be improved independently of the withstand voltage design of the device, and a normally-off characteristic can ultimately be realized.
また、前記低濃度ｎ型チャネル領域（７）及び前記低濃度ｎ型領域１（９）の不純物濃度が、前記低濃度ｎ型ドリフト層（３）の不純物濃度よりも高くても良い。これにより、前記低濃度ｎ型チャネル領域（７）の抵抗が減少し、耐圧設計とは独立してオン特性を大幅に向上させることが可能となる。 The impurity concentration of the low-concentration n-type channel region (7) and the low-concentration n-type region 1 (9) may be higher than the impurity concentration of the low-concentration n-type drift layer (3). As a result, the resistance of the low-concentration n-type channel region (7) is reduced, and the on-characteristic can be greatly improved independently of the withstand voltage design.
図５（ｄ）の工程において、前記低濃度ｎ型領域２（１１）上に金属又はＳｉＯ２等のエッチングマスク材を積層し、次々工程である図５（ｆ）の電極形成工程においてゲート電極（８）が形成されるデバイスセルの外周部のみをリソグラフィーにより開口し、前記開口部を前記高濃度ｐ型層（１０）の最表面が露出するまでドライエッチングを行う。 In the step of FIG. 5D, an etching mask material such as metal or SiO 2 is laminated on the low-concentration n-type region 2 (11), and the gate electrode is formed in the electrode forming step of FIG. Only the outer periphery of the device cell in which (8) is formed is opened by lithography, and dry etching is performed on the opening until the outermost surface of the high-concentration p-type layer (10) is exposed.
図５（ｅ）の工程において、前工程において形成した表面上にレジスト、又はＳｉＯ２のイオン注入マスク材を積層し、高濃度ｎ型ソース領域（５）が形成される部分のみをリソグラフィーにより開口し、前記開口部にリン、又は窒素等のｎ型不純物をイオン注入することにより、前記高濃度ｎ型ソース領域（５）を形成する。この際、前記高濃度ｐ型ゲート領域（４）、及び前記低濃度ｎ型チャネル領域（７）の上部に低濃度ｎ型領域１（９）が残る様に、イオン注入のエネルギーを調整する必要がある。前記低濃度ｎ型領域１（９）が存在することにより、ソース・ゲート間の耐圧を確保することが出来る。またイオン注入を行う際、基板温度は室温であっても良いし、１０００℃以下の温度に昇温しても良い。 In the step of FIG. 5E, a resist or SiO 2 ion implantation mask material is laminated on the surface formed in the previous step, and only the portion where the high-concentration n-type source region (5) is formed is opened by lithography. Then, the high-concentration n-type source region (5) is formed by ion-implanting n-type impurities such as phosphorus or nitrogen into the opening. At this time, it is necessary to adjust the ion implantation energy so that the low-concentration n-type region 1 (9) remains above the high-concentration p-type gate region (4) and the low-concentration n-type channel region (7). There is. Due to the presence of the low-concentration n-type region 1 (9), the breakdown voltage between the source and the gate can be ensured. When performing ion implantation, the substrate temperature may be room temperature or may be raised to a temperature of 1000 ° C. or lower.
イオン注入する際の温度を上げることにより、結晶性を維持した状態で高ドーズ注入が可能となり、前記高濃度ｎ型ソース領域（５）のシート抵抗を大幅に低下させることが出来る。イオン注入終了後、基板をＡｒ等の不活性ガス雰囲気中で１５００℃以上の高温でアニールすることにより、前記高濃度ｎ型ソース領域（５）を電気的に活性化させる。また、このイオン注入工程は、前記図５（ｃ）工程の直後に行われても良い。その際は、イオン注入用のマスク材は必要なく基板全面にイオン注入を行うことが出来るため、デバイスプロセスは大幅に簡略化される。 By raising the temperature at the time of ion implantation, high dose implantation is possible while maintaining crystallinity, and the sheet resistance of the high concentration n-type source region (5) can be greatly reduced. After the ion implantation is completed, the high-concentration n-type source region (5) is electrically activated by annealing the substrate at a high temperature of 1500 ° C. or higher in an inert gas atmosphere such as Ar. In addition, this ion implantation step may be performed immediately after the step of FIG. In that case, since a mask material for ion implantation is not required and ion implantation can be performed on the entire surface of the substrate, the device process is greatly simplified.
図５（ｆ）の工程において、前記図５（ｅ）工程において形成した前記高濃度ｎ型ソース領域（５）の直上にソース電極（６）を、前記図５（ｄ）工程において形成したデバイスセル外の前記高濃度ｐ型層（１０）が露出している領域にゲート電極（８）をリソグラフィーを利用したリフトオフ、又はエッチングにより形成し、更に高濃度ｎ型炭化珪素基板（２）の裏面にドレイン電極を形成する。最終的にＡｒ等の不活性ガス雰囲気中で１０００℃以下のシンタリングアニールを行うことにより、炭化珪素トランジスタ装置が完成する。 In the step of FIG. 5 (f), a device in which the source electrode (6) is formed in the step of FIG. 5 (d) immediately above the high-concentration n-type source region (5) formed in the step of FIG. 5 (e). A gate electrode (8) is formed by lift-off using lithography or etching in a region where the high-concentration p-type layer (10) is exposed outside the cell, and the back surface of the high-concentration n-type silicon carbide substrate (2). A drain electrode is formed on the substrate. Finally, sintering annealing at 1000 ° C. or lower is performed in an inert gas atmosphere such as Ar to complete a silicon carbide transistor device.
本実施例では、高濃度ｐ型ゲート領域（４）を完全に埋め込んでしまう構造を実現することにより、従来型のＳＩＴに必要な露光合わせ精度や余分な設計マージンを取る必要が無く、デバイスの極限までの微細化が初めて可能となり、大幅なデバイスのオン抵抗削減が実現する。また、高濃度ｎ型ソース領域（５）をイオン注入により形成することにより、更なる大幅なデバイスのオン特性の改善が可能となる。また、低濃度ｎ型チャネル領域（７）及び低濃度ｎ領域１（９）の不純物濃度を、低濃度ｎ型ドリフト層（３）の不純物濃度と独立に制御が可能であるため、ノーマリオフ・ノーマリオンのスイッチングデバイスの動作モードを含めた、幅広いデバイス設計が可能となる。 In the present embodiment, by realizing a structure in which the high-concentration p-type gate region (4) is completely embedded, it is not necessary to provide exposure alignment accuracy and an extra design margin necessary for the conventional SIT. For the first time, miniaturization to the limit is possible, and the on-resistance of the device is greatly reduced. Further, by forming the high-concentration n-type source region (5) by ion implantation, it becomes possible to further improve the on-characteristics of the device. Further, since the impurity concentration of the low-concentration n-type channel region (7) and the low-concentration n-region 1 (9) can be controlled independently of the impurity concentration of the low-concentration n-type drift layer (3), it is normally off-no- A wide range of device designs are possible, including the operational modes of Mullion switching devices.
参考例として、図２に炭化珪素トランジスタ装置の断面構造を示す。本参考例は、第１実施例の製造工程の一部を変更したものである。ここでは、第１実施例と変更した部分のみを説明する。
As a reference example, FIG. 2 shows a cross-sectional structure of a silicon carbide transistor device. In this reference example, a part of the manufacturing process of the first embodiment is changed. Here, only the part which changed with 1st Example is demonstrated.
本参考例では、第１実施例における図５（ｅ）のイオン注入により高濃度ｎ型ソース領域（５）を形成する工程において、イオン注入のエネルギーを調整することにより、図２に示す様に前記高濃度ｎ型ソース領域（５）と、高濃度ｐ型ゲート領域（４）及び低濃度ｎ型チャネル領域（７）が直接接する様な構造が備えられている。この様な構造では、ソース・ゲート間の耐圧は低くなるが、第１実施例に備えられている低濃度ｎ型領域１（９）が存在しないため、第１実施例と比較して更なるオン特性の向上が可能となる。この様な構造は、電流をオフさせるためのゲート電圧が低いデバイス、例えばノーマリオフ特性を持つデバイスのように、特に高いソース・ゲート間耐圧が必要でない場合に非常に有効である。
In this reference example, as shown in FIG. 2, by adjusting the ion implantation energy in the step of forming the high concentration n-type source region (5) by the ion implantation of FIG. 5E in the first embodiment. The high-concentration n-type source region (5) is directly in contact with the high-concentration p-type gate region (4) and the low-concentration n-type channel region (7). In such a structure, the breakdown voltage between the source and the gate is lowered, but since the low concentration n-type region 1 (9) provided in the first embodiment does not exist, it is further compared with the first embodiment. The on-characteristic can be improved. Such a structure is very effective when a high source-gate breakdown voltage is not required, such as a device having a low gate voltage for turning off the current, for example, a device having normally-off characteristics.
本第２実施例は、第１実施例、及び参考例の製造工程の一部を変更したものである。ここでは、第１実施例、及び参考例と変更した部分のみを説明する。
In the second embodiment, a part of the manufacturing process of the first embodiment and the reference example is changed. Here, only the part which changed with 1st Example and a reference example is demonstrated.
第１実施例における図５（ａ）の工程と同様に、図６（ａ）に示す様に、高濃度ｎ型炭化珪素基板（２）上に低濃度ｎ型ドリフト層（３）をエピタキシャル成長により形成する。続いて、図６（ｂ）に示す様に、前記低濃度ｎ型ドリフト層（３）へ、アルミニウム又はホウ素等のｐ型不純物をイオン注入することにより高濃度ｐ型層（１０）を形成する。その後、基板をＡｒ等の不活性ガス雰囲気中で１６００℃以上の高温でアニールすることにより、前記高濃度ｐ型層（１０）を電気的に活性化させる。その後の工程は第１実施例と同様であるので省略する。 Similar to the process of FIG. 5A in the first embodiment, as shown in FIG. 6A, the low concentration n-type drift layer (3) is epitaxially grown on the high concentration n-type silicon carbide substrate (2). Form. Subsequently, as shown in FIG. 6B, a high-concentration p-type layer (10) is formed by ion-implanting p-type impurities such as aluminum or boron into the low-concentration n-type drift layer (3). . Thereafter, the high-concentration p-type layer (10) is electrically activated by annealing the substrate at a high temperature of 1600 ° C. or higher in an inert gas atmosphere such as Ar. Subsequent steps are the same as those in the first embodiment, and will be omitted.
第１実施例、及び参考例のようにエピタキシャル成長ではなく、本実施例ではイオン注入により前記高濃度ｐ型層（１０）を形成することにより、製造工程が簡略化される。ただしこの場合、予めエピタキシャル成長させた前記低濃度ｎ型ドリフト層（３）の一部が、イオン注入により高濃度ｐ型層（１０）に転換されるため、イオン注入により消滅する前記低濃度ｎ型ドリフト層（３）の厚みを予め考慮に入れた上で、デバイスの耐圧設計を行う必要がある。
The manufacturing process is simplified by forming the high-concentration p-type layer (10) by ion implantation in this embodiment instead of epitaxial growth as in the first and reference examples. However, in this case, since a part of the low-concentration n-type drift layer (3) epitaxially grown in advance is converted into a high-concentration p-type layer (10) by ion implantation, the low-concentration n-type disappears by ion implantation. It is necessary to design the device withstand voltage in consideration of the thickness of the drift layer (3) in advance.
１・・・ドレイン電極
２・・・高濃度ｎ型炭化珪素基板
３・・・低濃度ｎ型ドリフト層
４・・・互いに離間した高濃度ｐ型ゲート領域
５・・・高濃度ｎ型ソース領域
６・・・ソース電極
７・・・低濃度ｎ型チャネル領域
８・・・ゲート電極
９・・・低濃度ｎ型領域１
１０・・・高濃度ｐ型層
１１・・・低濃度ｎ型領域２
２１・・・ドレイン電極
２２・・・高濃度ｎ型炭化珪素基板
２３・・・低濃度ｎ型層
２４・・・互いに離間した高濃度ｐ型ゲート領域
２５・・・高濃度ｎ型ソース領域
２６・・・ソース電極
２７・・・低濃度ｎ型チャネル領域
２８・・・ゲート電極
２９・・・絶縁膜
３０・・・低濃度ｎ型ドリフト層
４１・・・高濃度ｎ型炭化珪素基板
４２・・・低濃度ｎ型ドリフト層
４３・・・互いに離間した高濃度ｐ型ゲート領域１
４４・・・互いに離間した高濃度ｐ型ゲート領域２
４６・・・低濃度ｎ型チャネル領域
４７・・・高濃度ｎ型ソース領域
４８・・・ソース電極
４９・・・ドレイン電極
DESCRIPTION OF SYMBOLS 1 ... Drain electrode 2 ... High concentration n type silicon carbide substrate 3 ... Low concentration n type drift layer 4 ... High concentration p type gate region spaced apart from each other 5 ... High concentration n type source region 6 ... Source electrode 7 ... Low concentration n-type channel region 8 ... Gate electrode 9 ... Low concentration n-type region 1
10 ... High-concentration p-type layer 11 ... Low-concentration n-type region 2
21 ... Drain electrode 22 ... High concentration n-type silicon carbide substrate 23 ... Low concentration n-type layer 24 ... High concentration p-type gate region 25 spaced apart from each other ... High concentration n-type source region 26 ... Source electrode 27 ... Low-concentration n-type channel region 28 ... Gate electrode 29 ... Insulating film 30 ... Low-concentration n-type drift layer 41 ... High-concentration n-type silicon carbide substrate 42 ..Low concentration n-type drift layer 43... High concentration p-type gate region 1 separated from each other
44... High-concentration p-type gate region 2 separated from each other
46 ... Low-concentration n-type channel region 47 ... High-concentration n-type source region 48 ... Source electrode 49 ... Drain electrode
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| WO2007004528A1 (en) * | 2005-06-30 | 2007-01-11 | Yamanashi University | Method for designing structure of silicon carbide electrostatic induction transistor |
| US20070029573A1 (en) * | 2005-08-08 | 2007-02-08 | Lin Cheng | Vertical-channel junction field-effect transistors having buried gates and methods of making |
| JP4853928B2 (en) * | 2007-08-24 | 2012-01-11 | 独立行政法人産業技術総合研究所 | Control device and control method for silicon carbide static induction transistor |
| JP2009088223A (en) * | 2007-09-28 | 2009-04-23 | Hitachi Cable Ltd | Silicon carbide semiconductor substrate and silicon carbide semiconductor device using the same |
| WO2011108768A1 (en) * | 2010-03-04 | 2011-09-09 | 独立行政法人産業技術総合研究所 | Embedded gate type silicon carbide static induction transistor and method for manufacturing same |
| US8698164B2 (en) | 2011-12-09 | 2014-04-15 | Avogy, Inc. | Vertical GaN JFET with gate source electrodes on regrown gate |
| JP6160216B2 (en) * | 2013-05-09 | 2017-07-12 | 富士電機株式会社 | Semiconductor device |
| WO2015145641A1 (en) * | 2014-03-26 | 2015-10-01 | 日本碍子株式会社 | Semiconductor device |
| JP2016032014A (en) * | 2014-07-29 | 2016-03-07 | 日本電信電話株式会社 | Method of manufacturing nitride semiconductor device |
| CN116936610B (en) * | 2023-09-18 | 2023-12-01 | 成都功成半导体有限公司 | Deep-doped silicon carbide withstand voltage JFET structure and preparation method thereof |
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| JPH1051010A (en) * | 1996-07-29 | 1998-02-20 | Tokin Corp | Manufacture of semiconductor device |
| JPH10341025A (en) * | 1997-06-06 | 1998-12-22 | Toyota Central Res & Dev Lab Inc | Vertical junction type field effect transistor |
| JP3338683B2 (en) * | 2000-01-12 | 2002-10-28 | 株式会社日立製作所 | Silicon carbide semiconductor device and power converter using the same |
| JP4085604B2 (en) * | 2001-08-29 | 2008-05-14 | 株式会社デンソー | Method for manufacturing silicon carbide semiconductor device |
| JP3765268B2 (en) * | 2001-12-21 | 2006-04-12 | 株式会社デンソー | Silicon carbide semiconductor device and manufacturing method thereof |
| JP4110875B2 (en) * | 2002-08-09 | 2008-07-02 | 株式会社デンソー | Silicon carbide semiconductor device |
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