JP3338683B2 - Silicon carbide semiconductor device and power converter using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device using silicon carbide as a semiconductor material.

[0002]

2. Description of the Related Art Silicon carbide has a dielectric breakdown electric field which is one order of magnitude larger than silicon. Therefore, when applied to a power device, it is possible to reduce the size of a large-capacity device which cannot be achieved with a silicon semiconductor device.

A conventional apparatus is disclosed in Japanese Patent Application Laid-Open No. H10-294471.
As described in Japanese Patent Application Laid-Open Publication No. H10-260, a high-resistance first
A first substrate having a two-layer structure including a first substrate of a conductivity type and a second substrate of a first conductivity type having a second main surface having a lower resistance than the first substrate of the high resistance first conductivity type has a first main surface. A second conductivity type gate region is arranged at a constant interval in a direction parallel to the first main surface from the first conductivity type source region, and is in contact with the second conductivity type gate region. This is a silicon carbide semiconductor device that limits a current between a source / drain electrode by a voltage applied to a gate electrode.

However, as described below, the conventional apparatus can be roughly divided into two problems.

In the conventional device described in Japanese Patent Application Laid-Open No. H10-294471, a portion of the first conductivity type source region where the first conductivity type impurity concentration is high, and a portion of the second conductivity type gate region where the first conductivity type impurity concentration is high. A pn junction is formed between the regions where the value is high.

Generally, the distribution of defects due to ion implantation is large in a region having a high impurity concentration, and it is difficult to recover defects after ion implantation in a silicon carbide semiconductor. Therefore, the pn junction region has many defects. Including. Further, the breakdown voltage of the pn junction between the high impurity concentration portions is low even without considering the influence of the defect.

Therefore, in order to improve the breakdown voltage between the second conductivity type gate region and the high resistance first conductivity type first substrate in the conventional device, the device in which the impurity concentration of the second conductivity type gate region is high is as follows. The breakdown voltage between the first conductivity type source region and the second conductivity type gate region is low.

On the other hand, Terasawa et al. Announced S at IEDM '79.
In the conventional i-semiconductor device, the first conductive type source region and the second conductive type gate region are not in contact with each other in a cross section of the first conductive type first base perpendicular to the first main surface. The above problem has been solved by improving the breakdown voltage of the second conductive type gate region because the second conductive type gate region is located closer to the second main surface side than the first conductive type source region. Ion implantation during formation requires a high accelerating voltage.

Due to the high-energy ion implantation, a number of defects due to the ion implantation are generated in a portion of the first conductive type first base body closer to the first main surface than the second conductive type gate region, and carbonization occurs. It is difficult to recover defects after ion implantation in a silicon semiconductor, which causes an increase in leakage current.

In addition, ion implantation requires a new mask material capable of withstanding high energy ion implantation and capable of fine processing.

[0011]

In manufacturing a silicon carbide semiconductor device, the breakdown voltage between the second conductivity type gate region / the high resistance first conductivity type first base and the first conductivity type source region / the first There is a need to improve the breakdown voltage between the two-conductivity-type gate regions at the same time, to withstand high-energy ion implantation, to enable fine processing, and to adopt a structure that does not require a new mask material.

An object of the present invention is to provide a withstand voltage between the second conductivity type gate region / the high resistance first conductivity type first base and a withstand voltage between the first conductivity type source region / the second conductivity type gate region. It is another object of the present invention to provide a silicon carbide semiconductor device which achieves the simultaneous improvement of the above.

Another object of the present invention is to provide a power converter in which the gate drive circuit is simplified by applying the above-mentioned silicon carbide semiconductor device.

[0014]

According to the present invention, in a silicon carbide semiconductor device, the first conductivity type source region / the second conductivity type source region is provided.
In order to simultaneously improve the withstand voltage between the conductive-type gate regions and the withstand voltage between the second conductive-type gate region and the high-resistance first-conductivity-type first base, the following configuration is adopted.

[1] A projection point on the first main surface of a portion in the second conductivity type gate region where the distance between the second conductivity type gate region and the first conductivity type source region is minimum,
A point in the first conductive type source region where the width of the first conductive type source region is maximum is closer to the source electrode than a projection point on the first main surface.

The projection point is, as described with reference to FIG. 1, an example of the projection point in the second conductivity type gate region 2 where the distance between the second conductivity type gate region 2 and the first conductivity type source region 1 is minimum. It indicates the projection point B of the part A on the first main surface.

[2] The boundary between the first conductivity type source region / the high resistance first conductivity type first base and the boundary between the second conductivity type gate region / the high resistance first conductivity type first base are Touch or overlap. The above-mentioned boundary is, for example, p
Refers to the contour of the n-junction.

[3] The second conductivity type impurity concentration at the boundary between the first conductivity type source region / the second conductivity type gate region is the second conductivity type impurity concentration contained in the second conductivity type gate region. Or less than the maximum value of.

[4] Further, the second conductivity type impurity concentration at the boundary between the first conductivity type source region / the second conductivity type gate region is included in the second conductivity type gate region. The concentration was limited to the maximum value or less.

According to the present invention, the junction region between the source region of the first conductivity type and the gate region of the second conductivity type is the first conductive type.
The conductive type source region and the second conductive type gate region are formed so as to avoid the high impurity concentration regions.

Thus, the high impurity concentration portions of the first conductivity type source region and the second conductivity type gate region, which include a large number of defects generated by the ion implantation, are formed by the first conductivity type gate region.
Pn between a conductive type source region and the second conductive type gate region
Since it is not included in the junction region, a decrease in breakdown voltage between the first conductivity type source region and the second conductivity type gate region due to a defect is suppressed. Further, even when the existence of a defect is not taken into consideration, an improvement in the breakdown voltage of the pn junction can be achieved.

The second conductivity type gate region is closer to the first main surface side than the conventional Si semiconductor device disclosed by Terasawa et al. In IEDM '79. Accordingly, the acceleration voltage required for ion implantation for forming the second conductivity type gate region can be reduced.

Therefore, defects due to high-energy ion implantation can be reduced, and the leakage current can be reduced. Further, it is not necessary to change the mask material required for high energy ion implantation.

Further, when the silicon carbide semiconductor device is applied to a power converter, simplification of a gate drive circuit can be achieved.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view of a silicon carbide static induction transistor according to one embodiment of the present invention. FIG. 2 shows an example in which the silicon carbide electrostatic induction transistor according to one embodiment of the present invention is applied to a product.

Reference numeral 1 denotes n which is an example of a source region of the first conductivity type.
Type source region, 2 is a p-type gate region which is an example of a second conductivity type gate region, 3 is a low impurity concentration n-type drift region which is an example of a first conductivity type first substrate, and 4 is a first conductivity type second drift region. An n-type drain region, which is an example of a base, 5 is an insulator, 11 is a high n-type impurity concentration region of an n-type source region, 12 is a high p-type impurity concentration region of a p-type gate region, 21 is a source electrode,
22 is a gate electrode, 23 is a drain electrode, 31 is a source terminal, 32 is a gate terminal, and 33 is a drain terminal.

In the silicon carbide semiconductor device of the present invention,
As in the conventional device, the low impurity concentration n-type drift region 3
Has a structure in which the n-type source region 1 is arranged between the p-type gate region 2 and the adjacent p-type gate region 2 on the first main surface side. The projection point on the first main surface of the portion of the p-type gate region 2 where the distance between the n-type source region 1 adjacent to the region 2 is the minimum, the width of the n-type source region 1 is the maximum The n
A point on the source region 1 is projected closer to the source electrode 11 than the projection point on the first main surface, and a boundary between the n-type source region 1 / the low impurity concentration n-type drift region 3 and p In this structure, the boundary between the gate region 2 and the low impurity concentration n-type drift region 3 is in contact with or overlaps.

Further, the impurity concentration at the boundary between the n-type source region 1 and the p-type gate region 2 is limited to a maximum value of the concentration of the p-type impurity contained in the p-type gate region 2. It is.

For example, when the present invention is applied to a device which achieves a gate / drain withstand voltage of 1 kV or more and a source / gate withstand voltage of 80 V or more, the p-type gate region 2 contains p-type gate region 2.
The maximum value of the concentration of the type impurity is 2 × 10 ¹⁷ cm to ³ or more, and the p-type impurity concentration at the boundary between the n-type source region 1 and the p-type gate region 2 is 2 × 10 ¹⁵ cm to ³ or less. Has become.

In the silicon carbide semiconductor device, the gate / drain breakdown voltage depends on the p-type impurity concentration of the p-type gate region 2. Is required to have a maximum value of the hole concentration of 2 × 10 ¹⁷ cm to ³ or more.
Since the higher the impurity concentration, the higher the defect distribution due to ion implantation, the higher the hole concentration at the pn junction, the lower the breakdown voltage between the source and drain due to the defects at the pn junction.

Even when the influence of defects is not taken into account, the lower the hole concentration of the p-type gate region 2 is, the higher the source / gate breakdown voltage is. Therefore, in the structure of the conventional device, the gate / drain breakdown voltage and the source-drain Simultaneous improvement with the withstand voltage is impossible.

In the silicon carbide semiconductor device of the present invention, the n
Since the high n-type impurity region 11 of the p-type source region 1 and the high p-type impurity region 12 of the p-type gate region 2 do not overlap, the maximum value of the concentration of the p-type impurity necessary for improving the gate / drain breakdown voltage is high. The pn junction impurity concentration between the n-type source region 1 and the p-type gate region 2 which is necessary for improving the withstand voltage between the source and the gate while maintaining the high p-type impurity region 12 which is a hole concentration region. it can.

In general, it is desirable that the withstand voltage between the source and the gate is higher.
Since the inter-gate breakdown voltage is improved, the gate drive power for switching is reduced by applying the semiconductor device of the present invention to a system as a switching element.

For example, in the above-described device, the hole concentration at the boundary between the n-type source region 1 and the p-type gate region 2 is 1/5 or less of the maximum value of the hole concentration contained in the p-type gate region. If it is limited to 4 × 10 ¹⁶ cm to ³ or less, a source / gate breakdown voltage of 50 V or more can be achieved.

In the structure, the boundary between the n-type source region 1 / the low impurity concentration n-type drift region 3 does not contact the boundary between the p-type gate region 2 / the low impurity concentration n-type drift region 3 Since it is necessary to form the p-type gate region 2 closer to the n-type drain region 4 according to the present invention, it is necessary to perform ion implantation at a higher acceleration voltage when the p-type gate region 2 is formed. .

As a result, due to the high-energy ion implantation, a number of defects caused by the ion implantation occur in a portion of the low impurity concentration n-type drift region 3 closer to the n-type source region 1 than the p-type gate region 2. Leakage current increases. Further, it is necessary to change to a mask material that withstands a higher accelerating voltage and is suitable for fine processing accompanying pattern formation.

As described above, the distance between the boundary between the n-type source region 1 / the low impurity concentration n-type drift region 3 and the boundary between the p-type gate region 2 / the low impurity concentration n-type drift region 3 is as follows. The p-type impurity concentration at the boundary between the n-type source region 1 and the p-type gate region 2 is selected so as to be equal to or less than the maximum value of the concentration of the p-type impurity contained in the p-type gate region 2.

FIG. 3 is a schematic sectional view of a silicon carbide static induction transistor in which boron and aluminum are applied to the formation of the p-type gate region 2 in another embodiment of FIG.

This structure can be realized by forming the p-type gate region 2 using boron and then forming the high aluminum concentration p-type region 6 using aluminum.

Boron differs from other p-type impurities in that a thermal diffusion phenomenon in silicon carbide crystal has been confirmed.
In the device described above, when boron is ion-implanted as an impurity of the p-type gate region 2 and then annealed at about 1600 ° C., the p-type gate region 2 expands outside the ion-implanted region due to a thermal diffusion phenomenon of boron. It is possible to reduce the probability of the existence of defects caused by ion implantation at the pn junction surface formed by the n-type source region 1 or the low impurity concentration n-type drift region 3 and the p-type gate region 2. it can.

However, when the p-type gate region 2 is formed using boron as a p-type impurity, the resistance inside the p-type gate region 2 increases, and when applied to a power element, heat loss increases.

When boron diffuses toward the low impurity concentration n-type drift region 3 due to the thermal diffusion phenomenon of boron, the boron concentration in the p-type gate region 2 decreases, and the resistance in the p-type gate region 2 decreases. Will be even higher. Therefore, after the p-type gate region 2 is formed using boron as a p-type impurity, aluminum is implanted into the p-type gate region 2 to form a high aluminum concentration p-type region 6, whereby boron is used as a p-type impurity. An increase in resistance inside the p-type gate region 2 due to the use can be suppressed.

FIG. 4 shows a silicon carbide electrostatic induction transistor according to one embodiment of the present invention, in which a p-type transistor for reducing the electric resistance between the p-type gate region 2 and the gate electrode 22 is formed.
FIG. 4 is a schematic cross-sectional view of a device having a mold region (p-type gate contact region 7).

The p-type gate region 2 and the gate electrode 2
2 so that the p-type gate region 2 and the n-type source region 1 do not form a pn junction for the purpose of reducing the electric resistance between the two.
By forming the p-type gate contact region 7 using a p-type impurity such as aluminum at a distance from the n-type source region 1, an electrical connection between the p-type gate region 2 and the gate electrode 22 is formed. The resistance is reduced.

For forming the p-type gate contact region 7, an impurity such as aluminum is suitable. This is because the use of boron as a p-type impurity in the formation of the p-type gate contact region 7 increases the resistance of the p-type gate contact region 7 and further increases the boron in the silicon carbide crystal in the substrate heating step after ion implantation. The boron concentration in the p-type gate contact region 7 decreases due to the thermal diffusion phenomenon of
This is because the resistance of the mold gate contact region 7 further increases.

In the structure in which the p-type gate contact region 7 forms a pn junction with the n-type source region 1,
Since the p-type impurity concentration of the p-type gate contact region 7 is higher than that of the p-type gate region 2, the breakdown voltage between the source and the gate is smaller than that of the pn junction between the n-type source region 1 and the p-type gate contact region 7. The breakdown voltage is limited by the breakdown voltage, and the breakdown voltage between the source and the gate is reduced as compared with the structure in which the p-type gate contact region 7 does not contact the n-type source region 1.

Therefore, the p-type gate contact region 7
Need to be formed at a distance from the n-type source region 1 so as not to form a pn junction with the n-type source region 1.

FIG. 5 shows a silicon carbide static induction transistor according to one embodiment of the present invention.
At least a part of the low impurity concentration n-type drift region 3 was processed using physical means such as polishing or chemical means such as etching, and then the gate electrode 22 was formed in a processed portion. It is a schematic cross section of an apparatus.

In the structure of the present invention, since the p-type gate region 2 exists inside the low impurity concentration n-type drift region 3, the p-type gate region 2 and the low impurity concentration n-type drift region 3 At least one part is processed to expose a part of the high p-type impurity part 12 to the first main surface, and then the first main surface exposed part is formed of the aluminum / titanium two-layer structure or the like. By forming the gate electrode 22, the electric resistance between the p-type gate region 2 and the gate electrode 22 is reduced.

FIG. 6 shows, in one embodiment of the silicon carbide static induction transistor of FIG. 5, a portion processed for the purpose of forming an electrode on a surface oblique or perpendicular to the first main surface. FIG. 2 is a schematic cross-sectional view of a device in which a part of the n-type source region 1 is exposed.

With the structure shown in FIG. 5, in the formation process using ion implantation of the n-type source region 1,
An error in the direction parallel to the first main plane with respect to the position of the implantation mask in the n-type source region 1 can be greatly tolerated. Further, when the semiconductor device formed on the base has the same structure, the implantation mask is The ion implantation of the n-type source region 1 becomes possible without using it.

FIG. 7 shows a silicon carbide static induction transistor according to one embodiment of the present invention, wherein the p-type gate region 2 and the gate electrode 22 have circular shapes on the first main surface, and FIG. 2 is a perspective view of a device in which the n-type source region 1 and the source region 21 are disposed inside a device 2;

FIG. 8 shows a silicon carbide electrostatic induction transistor according to one embodiment of the present invention, wherein the p-type gate region 2 and the gate electrode 22 on the first main surface are formed in a lattice shape, FIG. 2 is a perspective view of a device in which the n-type source region 1 and the source region 21 are disposed inside a mold gate region 2.

By using the structure shown in FIGS. 7 and 8, the present invention can be used, space can be saved, and the invention can be applied to a larger-scale power semiconductor device.

FIG. 9 is a configuration diagram showing an example of a configuration of an inverter for driving a motor using a silicon carbide static induction transistor to which the present invention is applied.

Six switching elements SW according to the present invention
11, SW21, SW31, SW12, SW22, SW
32 and six diodes D11, D21, D31, D
This is an example in which the three-phase induction motor M is controlled by using 12, D22, D32, and the gate drive circuit GD.

In the silicon carbide static induction transistor according to the present invention, the withstand voltage between the n-type source region 1 and the p-type gate region 2 is higher than that of the conventional structure, so that the gate drive circuit GD can be simplified.

FIG. 9 shows an example of application to an inverter device for a motor, but application to other power converters using a switching device is also possible.

[0059]

According to the present invention, the structure change of the silicon carbide semiconductor device withstands high-energy ion implantation, enables fine processing, does not require a new mask material, and reduces the second conductivity type gate region / The withstand voltage between the high-resistance first-conductivity-type first base and the withstand-voltage between the first-conductivity-type source region / the second-conductivity-type gate region can be simultaneously improved.

Further, when applied to a power converter, the gate drive circuit can be simplified.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a silicon carbide electrostatic induction transistor showing one embodiment of the present invention.

FIG. 2 is a schematic sectional view of a product to which a silicon carbide static induction transistor according to an embodiment of the present invention is applied.

FIG. 3 is a schematic cross-sectional view of a silicon carbide static induction transistor in which a p-type gate region is formed using boron and aluminum as impurities according to one embodiment of the present invention.

FIG. 4 is a schematic sectional view of a silicon carbide static induction transistor having a p-type gate contact region according to one embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a silicon carbide static induction transistor in which a gate electrode is formed in a processed portion after exposing a part of a p-type gate region to a first main surface according to one embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a silicon carbide static induction transistor in which a part of an n-type source region is exposed at a processing portion oblique or perpendicular to the first main surface in FIG.

FIG. 7 is a schematic perspective view of a silicon carbide static induction transistor having a circular shape on a first main surface of a p-type gate region and a gate electrode according to one embodiment of the present invention.

FIG. 8 is a schematic perspective view of a p-type gate region and a silicon carbide static induction transistor in which a shape on a first main surface of a gate electrode is formed in a lattice shape according to an embodiment of the present invention.

FIG. 9 is a circuit configuration diagram in which the silicon carbide static induction transistor of the present invention is used in an inverter for driving a motor.

[Explanation of symbols]

1 ... n-type source region, 2 ... p-type gate region, 3 ... low impurity concentration n-type drift region, 4 ... n-type drain region, 5 ...
Insulator, 6 ... High aluminum concentration p-type region, 7 ... P-type gate contact region, 11 ... High n-type impurity concentration region of n-type source region, 12 ... High p-type impurity concentration region of p-type gate region, 21 ... Source electrode, 22 ... Gate electrode, 23 ...
Drain electrode, 31 ... source terminal, 32 ... gate terminal,
33: drain terminal, SW11: switching element, S
W21: switching element, SW31: switching element, SW12: switching element, SW22: switching element, SW32: switching element, D11: diode, D21: diode, D31: diode, D
12: diode, D22: diode, D32: diode, M: three-phase induction motor, GD: gate drive circuit.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-10-294471 (JP, A) JP-A-57-172765 (JP, A) JP-A 2001-94120 (JP, A) Power Semiconductor or Devices and IC 's, 1997. ISPSD '97. , 1997 IEEE Symposium on, May 26, 1997, p. 149-152 (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/778-29/812 H01L 21/338

Claims (5)

(57) [Claims] 1. A high-resistance first conductivity type first base having a first main surface and a first conductivity type second base having a second main surface having a lower resistance than the high resistance first conductivity type first base. A silicon carbide semiconductor device in which a first conductivity type source region and a second conductivity type gate region are selectively provided on a first main surface side of a base having a two-layer structure, the second conductivity type gate region and the first conductivity type gate region. A projection point on the first main surface of a portion in the second conductivity type gate region where the distance of the conductivity type source region is minimum is the first conductivity type where the width of the first conductivity type source region is maximum. A first conductive type source region / the high resistance first conductive type first, which is closer to the source electrode than a projection point of a portion in the source region onto the first main surface;
A boundary between the bases and a boundary between the second conductive type gate region / the high resistance first conductive type first base contact or overlap, and a boundary between the first conductive type source region / the second conductive type gate region is formed. The second conductivity type impurity concentration is equal to or less than the maximum value of the second conductivity type impurity concentration included in the second conductivity type gate region, and is in a direction parallel to the first main surface of the first conductivity type source region.
A first conductivity type impurity concentration region and a second conductivity type gate region;
A second conductivity type impurity concentration in a direction parallel to the first main surface of the region.
The high resistance first conductivity type first base is not n-type and the second conductivity type gate region is formed by boron in silicon carbide crystal.
A silicon carbide semiconductor device characterized by using silicon and aluminum as impurities . Wherein said part first least processed by the second conductivity type gate region a part of the hand also of the high resistance first conductivity type first base and said second conductivity type gate region after exposing the main surface side, the serial <br/> placing the silicon carbide semiconductor device in claim 1 having a gate electrode formed on the exposed portion of the first main surface side of the second conductivity type gate region. 3. A part of the first conductivity type source region is exposed on a surface of the high resistance first conductivity type first base machined obliquely or perpendicular to the first main surface. 2
3. The silicon carbide semiconductor device according to item 1. 4. A physical means to the processing of the second conductivity type gate region, claim 1 using at least one of the chemical methods
3. The silicon carbide semiconductor device according to item 1. 5. A switching element using a silicon carbide semiconductor device according to any one of claims 1-4, the switch
A power converter, wherein the switching element has a gate drive circuit .