SG11201906017UA - Support for a semiconductor structure - Google Patents

Support for a semiconductor structure

Info

Publication number
SG11201906017UA
SG11201906017UA SG11201906017UA SG11201906017UA SG11201906017UA SG 11201906017U A SG11201906017U A SG 11201906017UA SG 11201906017U A SG11201906017U A SG 11201906017UA SG 11201906017U A SG11201906017U A SG 11201906017UA SG 11201906017U A SG11201906017U A SG 11201906017UA
Authority
SG
Singapore
Prior art keywords
international
bernin
chemin
des
pct
Prior art date
Application number
SG11201906017UA
Inventor
Patrick Reynaud
Marcel Broekaart
Frédéric Allibert
Christelle Veytizou
Luciana Capello
Isabelle Bertrand
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11201906017UA publication Critical patent/SG11201906017UA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 02 August 2018 (02.08.2018) WIP0 I PCT omit IIl °nolo milli mil IIIII lII 1111111 ow (10) International Publication Number WO 2018/137937 Al (51) International Patent Classification: H01L 21/02 (2006.01) HOJL 21/762 (2006.01) H01L 29/06 (2006.01) (21) International Application Number: PCT/EP2018/050677 (22) International Filing Date: 11 January 2018 (11.01.2018) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 1750646 26 January 2017 (26.01.2017) FR (71) Applicant: SOITEC [FR/FR]; Parc Technologique des Fontaines, Chemin des Franques, 38190 Bernin (FR). (72) Inventors: REYNAUD, Parick; Chemin de la Briot, 38420 Murianette (FR). BROEKAART, Marcel; Clos des Gen- tons, 38570 Theys (FR). ALLIBERT, Frederic; 30, rue Gay Lussac, 38100 Grenoble (FR). VEYTIZOU, Chris- telle; 295, chemin du Craponoz, 38190 Bernin (FR). CAPELLO, Luciana; 2, rue Madeleine, 38000 Grenoble (FR). BERTRAND, Isabelle; 756, RD 1090, Cedex 38, 38190 Bernin (FR). (74) Agent: BREESE, Pierre; IP TRUST, 2, me de Clichy, 75009 Paris (FR). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3)) (54) Title: SUPPORT FOR A SEMICONDUCTOR STRUCTURE 11 N N 11 FIG.1 (57) : The invention relates to a support (1) for a semiconductor structure, comprising a base substrate (3), a first silicon N dioxide insulating layer (2a) positioned on the base substrate (3) and having a thickness greater than 20 nm, and a charge trapping layer (2) having a resistivity higher than 1000 ohm.cm and a thickness greater than 5 microns positioned on the first insulating layer (2a). C
SG11201906017UA 2017-01-26 2018-01-11 Support for a semiconductor structure SG11201906017UA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1750646A FR3062238A1 (en) 2017-01-26 2017-01-26 SUPPORT FOR A SEMICONDUCTOR STRUCTURE
PCT/EP2018/050677 WO2018137937A1 (en) 2017-01-26 2018-01-11 Support for a semiconductor structure

Publications (1)

Publication Number Publication Date
SG11201906017UA true SG11201906017UA (en) 2019-08-27

Family

ID=59253590

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201906017UA SG11201906017UA (en) 2017-01-26 2018-01-11 Support for a semiconductor structure

Country Status (9)

Country Link
US (2) US11373856B2 (en)
EP (1) EP3574519B1 (en)
JP (1) JP2020505769A (en)
KR (1) KR20190108138A (en)
CN (1) CN110199375A (en)
FR (1) FR3062238A1 (en)
SG (1) SG11201906017UA (en)
TW (1) TW201841341A (en)
WO (1) WO2018137937A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3062517B1 (en) * 2017-02-02 2019-03-15 Soitec STRUCTURE FOR RADIO FREQUENCY APPLICATION
FR3098342B1 (en) * 2019-07-02 2021-06-04 Soitec Silicon On Insulator semiconductor structure comprising a buried porous layer, for RF applications
CN110687138B (en) * 2019-09-05 2022-08-05 长江存储科技有限责任公司 Method and device for measuring semiconductor structure and extracting boundary characteristic
FR3104322B1 (en) * 2019-12-05 2023-02-24 Soitec Silicon On Insulator METHOD FOR FORMING A HANDLING SUBSTRATE FOR A COMPOSITE STRUCTURE TARGETING RF APPLICATIONS
EP4189734B1 (en) * 2020-07-28 2024-06-26 Soitec Method for transferring a thin layer onto a support substrate provided with a charge trapping layer
FR3113184B1 (en) * 2020-07-28 2022-09-16 Soitec Silicon On Insulator METHOD FOR PREPARING A SUPPORT SUBSTRATE, AND METHOD FOR TRANSFERRING A THIN LAYER ONTO THIS SUPPORT SUBSTRATE
US11522516B2 (en) 2020-08-27 2022-12-06 RF360 Europe GmbH Thin-film surface-acoustic-wave filter using lithium niobate
CN116783719A (en) * 2020-12-31 2023-09-19 华为技术有限公司 Integrated circuit, power amplifier and electronic equipment
FR3127588A1 (en) 2021-09-28 2023-03-31 Lynred METHOD FOR MAKING AT LEAST ONE OPTICAL WINDOW, OPTICAL WINDOW AND ASSOCIATED INFRARED DETECTOR
FR3138239B1 (en) * 2022-07-19 2024-06-21 Soitec Silicon On Insulator Process for manufacturing a support substrate for radio frequency application

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Also Published As

Publication number Publication date
US11373856B2 (en) 2022-06-28
CN110199375A (en) 2019-09-03
WO2018137937A1 (en) 2018-08-02
KR20190108138A (en) 2019-09-23
TW201841341A (en) 2018-11-16
JP2020505769A (en) 2020-02-20
US20200020520A1 (en) 2020-01-16
EP3574519B1 (en) 2020-08-19
FR3062238A1 (en) 2018-07-27
EP3574519A1 (en) 2019-12-04
US20220301847A1 (en) 2022-09-22

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