SG11201907481PA - Rf device integrated on an engineered substrate - Google Patents

Rf device integrated on an engineered substrate

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Publication number
SG11201907481PA
SG11201907481PA SG11201907481PA SG11201907481PA SG11201907481PA SG 11201907481P A SG11201907481P A SG 11201907481PA SG 11201907481P A SG11201907481P A SG 11201907481PA SG 11201907481P A SG11201907481P A SG 11201907481PA SG 11201907481P A SG11201907481P A SG 11201907481PA
Authority
SG
Singapore
Prior art keywords
silicon oxide
international
oxide layer
layer coupled
qromis
Prior art date
Application number
SG11201907481PA
Inventor
Vladimir Odnoblyudov
Cem Basceri
Ozgur Aktas
Original Assignee
Qromis Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qromis Inc filed Critical Qromis Inc
Publication of SG11201907481PA publication Critical patent/SG11201907481PA/en

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
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    • H01L21/0245—Silicon, silicon germanium, germanium
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/2003—Nitride compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Nitrogen And Oxygen Or Sulfur-Condensed Heterocyclic Ring Systems (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Medicinal Preparation (AREA)

Abstract

SourceDrain 370 Gate-Diel 380 300 Multiple FP Gate 360 Interlayer-Diel 390 FIG. 3A ••.• .. • ... • . ••••••• . ••• . • . • .. .;. .. ... .. . .. ... :: : 2DEG inducing stack 340 Epitaxial Layers 330 Interlayer with embedded metal 320 Core 310 Via 352 RF Substrate 315 (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 30 August 2018 (30.08.2018) WIP0 I PCT oimiolo VIII °nolo OH 0111 VIII ioo Imo oimIE (10) International Publication Number WO 2018/156357 Al (51) International Patent Classification: HOlL 21/02 (2006.01) C3OB 29/06 (2006.01) C23C 16/24 (2006.01) C3OB 2 9 / 4 0 (2006.01) C23C 16/34 (2006.01) C3OB 29/68 (2006.01) (21) International Application Number: PCT/US2018/017405 (22) International Filing Date: 08 February 2018 (08.02.2018) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 62/461,722 21 February 2017 (21.02.2017) US 15/891,205 07 February 2018 (07.02.2018) US (71) Applicant: QROMIS, INC. [US/US]; 2306 Walsh Av- enue, Santa Clara, California 95051 (US). (72) Inventors: ODNOBLYUDOV, Vladimir; c/o Qromis, Inc., 2306 Walsh Avenue, Santa Clara, California 95032 (US). BASCERI, Cem; c/o Qromis, Inc., 2306 Walsh Av- enue, Santa Clara, California 95051 (US). AKTAS, Ozgur; c/o Qromis, Inc., 2306 Walsh Avenue, Santa Clara, Califor- nia 95051 (US). (74) Agent: LIU, Rong et al.; Kilpatrick Townsend & Stock- ton LLP, Mailstop: IP Docketing-22, 1100 Peachtree Street, Suite 2800, Atlanta, Georgia 30309 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, W O 20 18/ 15 6357 Al (54) Title: RF DEVICE INTEGRATED ON AN ENGINEERED SUBSTRATE (57) : A substrate for RF devices includes a polycrystalline ceramic core and an interlayer structure. The interlayer structure includes a first silicon oxide layer coupled to the polycrystalline ceramic core, a polysilicon layer coupled to the first silicon oxide layer, a second silicon oxide layer coupled to the polysilicon layer, a barrier layer coupled to the second silicon oxide layer, a third silicon oxide layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the third silicon oxide layer. [Continued on next page] WO 2018/156357 Al MIDEDIMOMOIDEIREEMOMMEHMEMEnin UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3))
SG11201907481PA 2017-02-21 2018-02-08 Rf device integrated on an engineered substrate SG11201907481PA (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201762461722P 2017-02-21 2017-02-21
US15/891,205 US10622468B2 (en) 2017-02-21 2018-02-07 RF device integrated on an engineered substrate
PCT/US2018/017405 WO2018156357A1 (en) 2017-02-21 2018-02-08 Rf device integrated on an engineered substrate

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SG11201907481PA true SG11201907481PA (en) 2019-09-27

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US (3) US10622468B2 (en)
EP (1) EP3586355A4 (en)
JP (2) JP7190244B2 (en)
KR (2) KR102559594B1 (en)
CN (2) CN110383420B (en)
SG (1) SG11201907481PA (en)
TW (2) TWI803054B (en)
WO (1) WO2018156357A1 (en)

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US10622468B2 (en) 2017-02-21 2020-04-14 QROMIS, Inc. RF device integrated on an engineered substrate
TWI789420B (en) * 2017-08-31 2023-01-11 美商康寧公司 Housings for portable electronic devices and methods for manufacturing the same
US10734303B2 (en) * 2017-11-06 2020-08-04 QROMIS, Inc. Power and RF devices implemented using an engineered substrate structure
US10686037B2 (en) * 2018-07-19 2020-06-16 Vanguard International Semiconductor Corporation Semiconductor structure with insulating substrate and fabricating method thereof
JP7070848B2 (en) * 2018-07-26 2022-05-18 住友電工デバイス・イノベーション株式会社 Manufacturing method of semiconductor device
US11430873B2 (en) * 2018-09-29 2022-08-30 Intel Corporation Self aligned gate connected plates for group III-Nitride devices and methods of fabrication
CN111009530A (en) * 2018-10-08 2020-04-14 世界先进积体电路股份有限公司 Semiconductor structure and manufacturing method
US10971612B2 (en) 2019-06-13 2021-04-06 Cree, Inc. High electron mobility transistors and power amplifiers including said transistors having improved performance and reliability
US10923585B2 (en) 2019-06-13 2021-02-16 Cree, Inc. High electron mobility transistors having improved contact spacing and/or improved contact vias
JP7429522B2 (en) * 2019-11-22 2024-02-08 住友化学株式会社 Group III nitride multilayer substrate and semiconductor device
EP4163424A4 (en) * 2020-06-09 2024-06-12 Shin-Etsu Chemical Co., Ltd. Substrate for group-iii nitride epitaxial growth and method for producing the same
WO2023119916A1 (en) * 2021-12-21 2023-06-29 信越半導体株式会社 Nitride semiconductor substrate and method for manufacturing nitride semiconductor substrate

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