CN106033724A - III-family nitride reinforced HEMT and preparation method thereof - Google Patents
III-family nitride reinforced HEMT and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 30
- 150000004767 nitrides Chemical class 0.000 title abstract 3
- 238000005530 etching Methods 0.000 claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 238000002161 passivation Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 34
- 229910002704 AlGaN Inorganic materials 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 19
- 229910002601 GaN Inorganic materials 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 229910017083 AlN Inorganic materials 0.000 claims description 11
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- UBMXAAKAFOKSPA-UHFFFAOYSA-N [N].[O].[Si] Chemical compound [N].[O].[Si] UBMXAAKAFOKSPA-UHFFFAOYSA-N 0.000 claims description 2
- 238000000605 extraction Methods 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 16
- 230000000694 effects Effects 0.000 abstract description 7
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 70
- 230000008569 process Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000007547 defect Effects 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 238000005036 potential barrier Methods 0.000 description 5
- 230000005533 two-dimensional electron gas Effects 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 238000004549 pulsed laser deposition Methods 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000011031 large-scale manufacturing process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- CVOFKRWYWCSDMA-UHFFFAOYSA-N 2-chloro-n-(2,6-diethylphenyl)-n-(methoxymethyl)acetamide;2,6-dinitro-n,n-dipropyl-4-(trifluoromethyl)aniline Chemical compound CCC1=CC=CC(CC)=C1N(COC)C(=O)CCl.CCCN(CCC)C1=C([N+]([O-])=O)C=C(C(F)(F)F)C=C1[N+]([O-])=O CVOFKRWYWCSDMA-UHFFFAOYSA-N 0.000 description 1
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 206010020843 Hyperthermia Diseases 0.000 description 1
- 208000037656 Respiratory Sounds Diseases 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 230000036031 hyperthermia Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
Abstract
The invention discloses a III-family nitride reinforced HEMT and a preparation method thereof. The preparation method comprises the steps of growing a heterostructure on a substrate, wherein the heterostructure is mainly composed of a first semiconductor layer as a barrier layer and a second semiconductor layer as a channel layer, and the first semiconductor layer is laminated on the second semiconductor layer; forming a mask layer which is simultaneously used as a passivation layer on the first semiconductor layer; etching the gate area of the mask layer until the first semiconductor layer is exposed; growing a p-type layer on the gate area of the mask layer, wherein the p-type layer and the first semiconductor layer form a PN junction; arranging a p-type gate on the p-type layer, and forming ohmic contact between the p-type gate and the p-type layer. The III-family nitride reinforced HEMT and the preparation method have advantages of greatly reducing application difficulty of p-type gate technology, effectively settling a reliability problem of the reinforced HEMT device, effectively inhibiting a current avalanche effect, greatly improving operation performance of the HEMT device and realizing the reinforced HEMT in the true sense.
Description
Technical field
The present invention relates to a kind of HEMT (High Electron Mobility Transistor, HEMT)
Preparation method, particularly to the preparation method of a kind of group III-nitride enhancement mode HEMT, belongs to technical field of semiconductors.
Background technology
Compared to traditional silica-based MOSFET, HEMT based on AGaN/GaN hetero-junctions
(HEMT) there is the unique advantages such as low on-resistance, high-breakdown-voltage, high switching frequency such that it is able at all kinds of electric power
Converting system uses as core devices, in terms of energy-saving consumption-reducing, has important application prospect, therefore suffer from academia,
The very big attention of industrial quarters.But, due to the polarity effect of III-nitride material system, it is however generally that, based on
The HEMT of AlGaN/GaN hetero-junctions is all depletion type (normally opened), when the device of the type is applied in circuit-level system,
Needing to design special negative polarity power-supply circuit, to realize the on-off control to device, this has been significantly greatly increased circuit
Complexity and cost.Additionally, depletion device existing defects in terms of fail safe ability, therefore, it is impossible to really realize
Commercial applications.For solving this problem, several technical schemes are suggested to prepare enhancement mode (the normally off) device.At present,
Routine techniques mainly includes fluorion injection technique, groove gate technique (Recessed Gate Technology), and wherein the former is sharp
With fluorine-containing plasma (such as CF4) device grids region is processed, electronegative fluorion is injected into
AlGaN potential barrier, thus exhaust the two-dimensional electron gas below grid, fluorion stability in barrier layer is had the highest by it
Requirement, and owing to HEMT device requires big electric current, high voltage when conducting state, the localized hyperthermia at raceway groove will lead
The heat causing fluorion is mobile, affects the spatial distribution of fluorion, thus causes threshold voltage shift, and fluorion injects in addition
During, inevitably barrier layer is caused damage, so must complete grid preparation after carry out process annealing with
Damage is recovered.The latter mainly passes through dry etching technology (mainly ICP, RIE) by grid region
AlGaN potential barrier is unkind, thus exhausts the two-dimensional electron gas below grid, refering to Fig. 1, because of over etching or deficient etching all
Enhancement mode HEMT cannot be realized prepare, therefore need to realize etching depth accurately controlling (typically at about 15nm), this
Damage is inevitably caused on barrier layer surface by outer etching process thus affects Schottky barrier, and etching process
In, the impurity, the defect that introduce in barrier layer can aggravate the electric leakage of the grid of device (it is true that thin barrier layer inherently can
Cause bigger electric leakage of the grid).Therefore, the shortcoming of above two technology is to ensure the reliable of enhancement mode HEMT
Property, it is impossible to realize commercial applications.
For the consideration of reliability, major part commercially available prod uses Cascode structure based on depletion type HEMT at present, i.e.
Depletion type HEMT is packaged integrated with enhanced type silicon MOSFET, by controlling the conducting of silicon MOSET, indirectly controls
Electric potential difference between HEMT gate pole (ground connection) processed and source electrode, thus realize " counterfeit normally-off " HEMT, but itself and non-real
Enhancement mode HEMT in meaning, and owing to Cascode structural requirement carries out integrated with silicon MOSFET, the most additionally increase
Complexity and the cost of packaging technology are added.
Have recently emerged enhancement mode HEMT technology of preparing based on p-type grid, it is expected to the enhancement mode realized truly
HEMT.This technology is on the basis of tradition HEMT epitaxial structure, outside AlGaN potential barrier (involuntary doping N-shaped) is upper
Epitaxial growth p-type layer, and carry out constituency etching and realize p-type grid and prepare, thus forming pn-junction, space-charge region (is primarily present
In barrier layer with in channel layer) two-dimensional electron gas at raceway groove is effectively exhausted, as shown in Figure 2.Due to enhancement mode
The electronics that HEMT requires nothing more than below grid is depleted, and constituency etching preparation p-type grid are required.But carrying out constituency etching
During, over etching or deficient etching all can cause the two-dimensional electron gas in region between device gate source, grid leak to reduce,
Thus have a strong impact on device conducting resistance operationally.Therefore, this p-type gate technique requires the p-type layer to non-area of grid
Etching depth controllable precise, this has also been significantly greatly increased the difficulty of p-type gate technique, and make this technology repeatability (sheet with
Between sheet), uniformity (in sheet between zones of different), stability (different wheel techniques between) be difficult to ensure that, uncomfortable
For large-scale production.Additionally, constituency etching p-type layer can non-area of grid inevitably introduce extra surface state,
Defect state so that the current collapse phenomenon of device is even more serious, thus has a strong impact on the reliability of device.
Summary of the invention
A kind of group III-nitride enhancement mode HEMT of offer and preparation method thereof is provided, thus overcomes existing
There is the deficiency in technology.
For realizing aforementioned invention purpose, the technical solution used in the present invention includes:
A kind of preparation method of group III-nitride enhancement mode HEMT, including:
(1) formed mainly by the first semiconductor layer as barrier layer and the second half leading as channel layer at Grown
The heterojunction structure of body layer composition, wherein said first semiconductor multilayer is located on the second semiconductor layer；
(2) formation doubles as the mask layer of passivation layer on the first semiconductor layer；
(3) gate regions of mask layer is performed etching, to exposing the first semiconductor layer；
(4) in the gate regions of described mask layer, p-type layer is grown, described p-type layer and the first semiconductor layer composition PN junction；
(5) p-type grid are set in described p-type layer, and make to be formed between described p-type grid and p-type layer Ohmic contact.
Among an embodiment, resistive formation between described heterojunction structure and substrate, is also distributed.
Wherein, described resistive formation effect is to make to be formed between active area raceway groove and substrate good being dielectrically separated from, and improves device
Part breakdown voltage.The material of described resistive formation can be selected from GaN, AlGaN or a combination of both etc., but is not limited to this.
Among an embodiment, step (1) may also include that and forms nucleating layer, Stress Control at Grown successively
Layer, resistive formation and described heterojunction structure.
Wherein, the effect of described nucleating layer is to make epitaxial material be grown in high quality on substrate.The material of described nucleating layer
Matter can be selected from AlN, GaN or a combination of both etc., but is not limited to this.
Wherein, the effect of described stress control layer is to offset in material epitaxy growth course because of lattice mismatch, thermal expansion system
Count the reasons such as mismatch and accumulate the stress of generation, thus effectively suppress the phenomenons such as epitaxial wafer warpage, crackle.Described stress control
The material of preparative layer can be selected from monolayer AlGaN, bilayer or double-deck above change al composition AlGaN etc., but is not limited to this.
Among an embodiment, described heterojunction structure may also include the insertion being distributed between first, second semiconductor layer
Layer.Wherein, the effect of described interposed layer be to make two-dimensional electron gas at raceway groove obtain more preferable space quantum confinement characteristic with
And reduction alloy scattering, improve electron mobility.The material of described interposed layer can form higher band rank selected from channel layer
The material of difference, such as AlN, AlInN or AlInGaN etc., but it is not limited to this.
Among an embodiment, step (3) may include that and first forms photoresist layer on mask layer, and to photoresist
The p-type grid region photoetching treatment of layer, to exposing the first semiconductor layer, then using photoresist layer as mask, leads the first half
The gate regions of body layer performs etching.Wherein, etching mode is preferably dry etching mode, such as RIE, ICP etching
Deng.And wet corrosion technique can also be used under given conditions the mask layer that (such as low temperature etc.) grows.
Among an embodiment, this preparation method may also include that
(6) step (5) obtained device is performed etching, it is achieved active area isolation.
Among an embodiment, this preparation method may also include that
(7) source, the drain region of step (6) obtained device is performed etching, to exposing the second semiconductor layer, and
In described source, drain region, it is respectively provided with source electrode and drain electrode, and makes described source electrode and drain electrode form Europe with the second semiconductor layer
Nurse contacts.
Among an embodiment, this preparation method may also include that
(8) extraction electrode being electrically connected with source electrode and drain electrode respectively is set on step (7) obtained device.
Further, described substrate includes silicon, sapphire, carborundum, aluminium nitride or gallium nitride substrate, but is not limited to
This.
Further, the material of described first semiconductor layer includes AlGaN, AInN or AlInGaN, described second quasiconductor
The material of layer includes GaN, but is not limited to this.
Further, the material of described mask layer include amorphous silicon nitride, amorphous silicon oxide, amorphous nitrogen-oxygen-silicon,
The combination of any one or more in amorphous aluminium nitride, but it is not limited to this.
Further, among this preparation method, material epitaxy growth technique can be selected from MBE (Molecular Beam
Epitaxy, molecular beam epitaxy), MOCVD (Metal Organic Chemical Vapor Deposition, metallorganic
Chemical gaseous phase deposits) etc., and it is not limited to this.
Further, among this preparation method, the depositing operation of mask layer/passivation layer can be selected from PECVD (Plasma
Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition), MOCVD, LPCVD
(Low Pressure Chemical Vapor Deposition, low-pressure chemical vapor deposition), ALD (Atom Layer
Deposition, ald), PLD (Pulsed Laser Deposition, pulsed laser deposition) etc., and do not limit
In this.
Further, the material of described p-type layer include p-AlGaN, p-GaN, p-AlGaN, p-AlInN, p-InGaN,
The combination of any one or more in p-AlInGaN, but it is not limited to this.
Use group III-nitride enhancement mode HEMT device prepared by any one technique aforementioned.
Further, in the present invention, can be not limited solely to AlGaN/AlN/GaN heterogeneous for the active area structure of HEMT
Knot, it is also possible to be applicable to the HEMT with other active area structures, as AlInN/AlN/GaN based on nearly Lattice Matching,
AlInGaN/AlN/GaN hetero-junctions HEMT, HEMT etc. based on double channel hetero-junctions.
Compared with prior art, the invention have the advantages that
(1) than the conventional formulation techniques of enhancement mode HEMT, such as fluorion injection technique, groove gate technique, Cascode knot
Structure technology, present invention process can effectively solve the integrity problem of device, it is achieved enhancement mode HEMT truly；
(2) than the p-type gate technique etched based on constituency, present invention process takes selective area epitaxial growth technology, at HEMT
Epitaxial growth aspect directly solve the orientation problem of p-type grid, thus the technique eliminating the p-type layer etching non-area of grid
Step, greatly reduces the enforcement difficulty of p-type gate technique, it is ensured that the repeatability of technique, uniformity, stability, is suitable to
Large-scale production, simultaneously, it is thus also avoided that to the etching in region between grid source, grid leak, reduce and introduce extra surface state
Probability, and use etching mask layer simultaneously as passivation layer, protect device surface admirably, can effectively press down
Current collapse processed.
Accompanying drawing explanation
Fig. 1 is the schematic diagram that groove gate technique prepares enhancement mode HEMT device；
Fig. 2 is the schematic diagram that p-type gate technique prepares enhancement mode HEMT device；
Fig. 3 is the structural representation of a kind of enhancement mode HEMT device in the present invention one exemplary embodiments；
Fig. 4 is the fabrication processing figure of a kind of enhancement mode HEMT device in the present invention one exemplary embodiments.
Detailed description of the invention
As it was previously stated, in view of many defects of prior art, such as conventional p-type gate technique take the scheme requirement that constituency etches
Etching depth controllable precise to the p-type layer of non-area of grid, implements the defects such as difficulty is bigger so existing.Inventor
Through studying for a long period of time and putting into practice in a large number, it is proposed that technical scheme, it is novel p-type grid based on selective area epitaxial growth
Technology, can directly solve the orientation problem of p-type grid in the epitaxial process of HEMT, thus avoid the non-grid of etching
The processing step of the p-type layer in region, greatly reduces the enforcement difficulty of p-type gate technique, it is ensured that the repeatability of technique, all
Even property, stability, can also effectively suppress current collapse simultaneously, thus improve the reliability of device.
Below in conjunction with accompanying drawing and a preferred embodiment, technical scheme is further described.
Below embodiment relates to a kind of based on silicon substrate and the HEMT device of AlGaN/AlN/GaN hetero-junctions, wherein uses p-
AlGaN is as p-type layer.
Refering to Fig. 4, the preparation technology of this HEMT device may include that
S1: the making of HEMT epitaxial structure based on silicon substrate；
S2: by technique grown silicon nitride such as PECVD as mask layer (passivation layer) on HEMT epitaxial structure；
S3: photoetching p-type gate region；
S4:RIE etching grid region silicon nitride mask layer；
S5:MOCVD selective area epitaxial growth p-AlGaN；
S6:p type grid Ohmic contact；
S7: active area isolation；
S8: source, leakage Ohmic contact；
S9: prepared by lead-in wire electrode.
More specifically, the preparation technology of this HEMT device comprises the following specific steps that:
1.MOCVD epitaxial growth HEMT based on AlGaN/GaN hetero-junctions.Wherein, AlGaN potential barrier Al component x
Being 10%～30%, thickness is 10～25nm；AlN interposed layer is about 1nm；GaN channel layer is 50～200nm, complete
Whole HEMT epitaxial structure based on silicon substrate is as shown in S1 in Fig. 4.
2.PECVD grown silicon nitride is as mask layer, and meanwhile, silicon nitride, again as passivation layer, can effectively suppress electric current
Pull-in effect.Growth conditions: underlayer temperature is 100～350 DEG C, reaction chamber pressure is 1700mtorr, SiH4Flow is
13～45sccm, NH3Flow is 10～90sccm, N2Purge flow rate be 1000sccm, RF power be 67W, LF merit
Rate is 53W.Silicon nitride mask layer thickness is 50 300nm, as shown in S2 in Fig. 4.
3. photoetching p-type gate region.Etching condition: photoresist AZ5214 thickness 1.5 μm, exposes 6.5s under hard contact mode,
JZX3038 develops 45s, post bake 5min at 110 DEG C.P-type gate region a size of 3 μ m 104 μm, as shown in S3 in Fig. 4.
In this step process, complete the photoetching of overlay mark simultaneously.
4. utilize photoresist AZ5214 as mask, RIE etching grid region silicon nitride mask layer.Etching condition: substrate temperature
Degree is room temperature, and chamber pressure is 1500mtorr, reacting gas SF6Flow is 8sccm, reacting gas CHF3Flow is 10
Sccm, carrier gas He flow be 150sccm, RF power be 200W.As shown in S4 in Fig. 4.In this step process,
Complete the silicon nitride mask layer etching in overlay mark region simultaneously.
5.MOCVD selective area epitaxial growth p-AlGaN.Growth conditions: growth temperature 500～1100 DEG C, reative cell pressure
55～500mbar, p-AlGaN mg-doped concentration range is 3 × 17～5 × 19cm-3, growth thickness is 50～200
nm.As shown in S5 in Fig. 4.
Prepared by 6.p type grid Ohmic contact.Preparation condition: metal Pd/Pt/Au, thickness is 30nm/30nm/50nm, annealing
Condition is 550 DEG C, 90s, nitrogen atmosphere.As shown in S6 in Fig. 4
7. use RIE, ICP etching, carry out active area isolation, wherein, the silicon nitride mask layer of RIE etching the 2nd one-step growth
(passivation layer), ICP is etched to resistive formation GaN or AlGaN.Etching condition: RIE etching condition is with 4, it is ensured that silicon nitride
All etchings；ICP etches, and underlayer temperature is room temperature, and chamber pressure is 6mtorr, reacting gas Cl2Flow is 30
Sccm, reacting gas BCl3Flow be 30sccm, RF power be 100W, ICP power is 300W.Such as S7 institute in Fig. 4
Show.
8. use RIE etching, carry out source and drain Ohmic contact and window.Etching condition is with 4, it is ensured that silicon nitride all etches,
AlGaN potential barrier can slightly etch (～1nm).
9. prepared by source and drain Ohmic contact.Preparation condition: metal Ti/Al/Ni/Au, thickness is 20nm/130nm/50nm/150
Nm, annealing conditions is 890 DEG C, 30s, nitrogen atmosphere.As shown in S8 in Fig. 4.
10. prepared by lead-in wire electrode.Preparation condition: W metal/Au, thickness is 50nm/400nm.As shown in S9 in Fig. 4.
The structure of this HEMT device finished product refers to Fig. 3, its than use fluorion injection technique, groove gate technique,
Similar device prepared by Cascode structure technology, reliability is substantially improved, and than using existing p-type gate technique to prepare
Similar device, cost of manufacture is greatly reduced, and yields is obviously improved, and the most less current collapse occur
Phenomenon, can long-time stable work.
It should be appreciated that for the person of ordinary skill of the art, can conceive according to the technology of the present invention and make
Other various corresponding changes and deformation, and all these change all should belong to the protection model of the claims in the present invention with deformation
Enclose.
Claims (10)
1. the preparation method of group III-nitride enhancement mode HEMT, it is characterised in that including:
(1) form the heterojunction structure being mainly made up of the first semiconductor layer as barrier layer and the second semiconductor layer as channel layer at Grown, wherein said first semiconductor multilayer is located on the second semiconductor layer；
(2) formation doubles as the mask layer of passivation layer on the first semiconductor layer；
(3) gate regions of mask layer is performed etching, to exposing the first semiconductor layer；
(4) in the gate regions of described mask layer, p-type layer is grown, described p-type layer and the first semiconductor layer composition PN junction；
(5) p-type grid are set in described p-type layer, and make to be formed between described p-type grid and p-type layer Ohmic contact.
The preparation method of group III-nitride enhancement mode HEMT the most according to claim 1, it is characterised in that resistive formation is also distributed between described heterojunction structure and substrate.
The preparation method of group III-nitride enhancement mode HEMT the most according to claim 2, it is characterised in that step (1) including: form nucleating layer, stress control layer, resistive formation and described heterojunction structure at Grown successively.
The preparation method of group III-nitride enhancement mode HEMT the most according to claim 1, it is characterized in that described heterojunction structure also includes the interposed layer being distributed between first, second semiconductor layer, the material of described interposed layer includes can be with the material of channel layer formation higher band jump.
The preparation method of group III-nitride enhancement mode HEMT the most according to claim 1, it is characterized in that step (3) including: on mask layer, first form photoresist layer, and the p-type grid region photoetching treatment to photoresist layer, to exposing the first semiconductor layer, then using photoresist layer as mask, the gate regions of the first semiconductor layer is performed etching.
The preparation method of group III-nitride enhancement mode HEMT the most according to claim 1, it is characterised in that also include:
(6) step (5) obtained device is performed etching, it is achieved active area isolation.
The preparation method of group III-nitride enhancement mode HEMT the most according to claim 6, it is characterised in that also include:
(7) source, the drain region of step (6) obtained device is performed etching, to exposing the second semiconductor layer, and in described source, drain region, be respectively provided with source electrode and drain electrode, and make described source electrode and drain electrode form Ohmic contact with the second semiconductor layer.
The preparation method of group III-nitride enhancement mode HEMT the most according to claim 7, it is characterised in that also include:
(8) extraction electrode being electrically connected with source electrode and drain electrode respectively is set on step (7) obtained device.
9. according to the preparation method of group III-nitride enhancement mode HEMT according to any one of claim 1-8, it is characterized in that described substrate includes silicon, sapphire, carborundum, aluminium nitride or gallium nitride substrate, the material of described first semiconductor layer includes AlGaN, AlInN or AlInGaN, the material of described second semiconductor layer includes GaN, the material of described mask layer includes silicon nitride, silicon oxide, nitrogen-oxygen-silicon, the combination of any one or more in aluminium nitride, the material of described p-type layer includes p-AlGaN, p-GaN, p-AlGaN, p-AlInN, p-InGaN, the combination of any one or more in p-AlInGaN.
10. use group III-nitride enhancement mode HEMT device prepared by method according to any one of claim 1-9.
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