JP2007142144A - Field effect transistor integrated circuit and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transistor integrated circuit that improves heat radiation and has a small chip area, and to provide a manufacturing method of the transistor integrated circuit in a field effect transistor integrated circuit that uses a nitride compound semiconductor. <P>SOLUTION: A through-hole is formed in an epitaxial growth layer for constituting an AlGaN/GaN field effect transistor; a conductive material, such as a metal thick film serving as the ground, and a wiring metal are formed on the upper and lower parts of the epitaxial growth layer; and the conductive material or the wiring metal is connected electrically to the electrode of the field effect transistor via a through-hole formed in the epitaxial growth layer. The wiring metal is laid out so that the wiring metal and the conductive material form a microstrip line, and is used as a passive element to form a high-frequency integrated circuit for submillimeter-wave bands, in combination with one or a plurality of field effect transistors. The epitaxial growth layer is separated from a substrate used for the growth of crystals, such as sapphire. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a field effect transistor integrated circuit using a nitride semiconductor that can be applied to a high-frequency transistor used in, for example, a transmission / reception circuit of a mobile phone, a quasi-millimeter wave band radar system, and the like, and a manufacturing method thereof.

Nitride compound semiconductors typified by GaN are wide-cap semiconductors with a large forbidden band, and have a higher breakdown electric field and higher electron saturation drift speed than compound semiconductors such as GaAs or Si semiconductors. Therefore, it is attracting attention for high-frequency and high-power transistors, and research and development are actively conducted. As a result of reducing the parasitic resistance between the source and drain electrodes by shortening the gate length to 0.18 μm and providing a recess structure around the gate electrode, the maximum oscillation frequency f _max has also been improved to 140 GHz (non-patented) See reference 1.) More recently, there has been a report that a gate length of 60 nm and a field effect transistor f _max of 173 GHz can be realized (see Non-Patent Document 2). If such excellent high-frequency characteristics are used, application as a quasi-millimeter wave band transistor and an integrated circuit of 20 GHz or more is sufficiently possible. In this frequency band, a communication application using UWB (Ultra Wide Band) wireless communication is possible, and for example, development to a short-range radar system is expected.

As described above, in order to apply a nitride semiconductor, which is promising for a high-frequency transistor, to a frequency band higher than a quasi-millimeter wave band, it is indispensable to make an integrated circuit including a passive element portion. In such a high frequency band, it is not as a passive component such as an inductor or a capacitor. For example, a so-called microstrip line in which the entire surface metal as a ground and a wiring metal on the surface side are formed on the back surface of the substrate, or the ground on both sides of the wiring metal. In general, the coplanar lines formed in the above are integrated as passive elements. The microstrip line can reduce the chip area because the ground is formed on the back side, but the establishment of a special process technology that connects the metal wiring on the front side and the back side through holes that penetrate the substrate. Necessary. In general, when using a sapphire substrate that is widely used for crystal growth of nitride semiconductors, the sapphire substrate is difficult to process by dry etching, and it is impossible to form the above-described through hole, so-called via hole. Passive elements are manufactured using a coplanar line, and an integrated circuit for a quasi-millimeter wave band is realized. A two-stage amplifier that integrates the above-mentioned recess-structure field-effect transistor with f _max of 140 GHz and a coplanar line has been fabricated, and a high gain of 13 dB, wideband operation, and excellent distortion characteristics have been confirmed at 21.6 GHz. (See Patent Document 3).
T. Murata et al., IEEE Trans. Electron Devices, 52 (2005) 1042. M. Higashiwaki et al., Jpn. J. Appl. Phys., 44 (2005) L475. M.Nishijima et al., 2005 IEEE MTT-S IMS Digest, Session TU4B.

  However, the conventional GaN-based field effect transistor integrated circuit uses a coplanar line, and since the ground is formed on the chip surface side, there is a problem that there is a limit to reducing the chip area. In addition, in order to make the grounds on both sides of the line have the same potential, it is necessary to provide wiring such as an air bridge structure, which causes a problem that the manufacturing process is rather complicated. In addition, since a sapphire substrate is used, there is a limit to heat dissipation, and it is also a problem that there is a limit to improving characteristics during high output operation.

  In view of the above-mentioned technical problems, the present invention improves heat dissipation by separating a substrate used for crystal growth from a nitride semiconductor layer and further forming a thick metal film or transferring it to a different substrate, and crystal growth. It is an object of the present invention to provide a GaN-based field effect transistor and an integrated circuit having a small chip area and a method of manufacturing the same by forming a microstrip line without forming a through hole in the substrate used in the above.

  In order to solve the above-described problems, the field effect transistor integrated circuit and the manufacturing method thereof according to the present invention have the following configurations.

  That is, a through hole is formed in the epitaxial growth layer constituting the field effect transistor, and a conductive material and a wiring metal serving as a ground are formed above and below the epitaxial growth layer, respectively. The conductive material or the wiring metal is formed through the through hole. And is electrically connected to the electrode of the field effect transistor. The wiring metal is laid out so that the wiring metal and the conductive material form a microstrip line, and this is used as a passive element to form an integrated circuit combined with one or a plurality of field effect transistors. The epitaxial growth layer is separated from the substrate used for crystal growth. Therefore, a microstrip line can be realized only by the process of forming a through hole in the epitaxial growth layer without forming a through hole in the substrate used for epitaxial growth, and a high-frequency integrated circuit can be formed more easily with a small chip area. Further, by separating the substrate used for epitaxial growth and transferring it to a substrate excellent in heat dissipation, a field effect transistor excellent in heat dissipation can be realized.

  Specifically, in the field effect transistor integrated circuit according to claim 1, a semiconductor layer is formed in this order on a conductive material, a source, a drain, and a gate electrode are in contact with the first semiconductor layer, and the conductive layer is formed. Formed between the material and the semiconductor layer, a through hole is formed in the semiconductor layer, and any of the electrodes is not formed in the semiconductor layer through the through hole. It is electrically connected to a wiring metal formed on the surface on the side, and either the conductive material or the electrode is electrically connected.

  With such a configuration, the electrode can be formed on the back surface through the through hole, so that it is possible to form a field effect transistor or an integrated circuit thereof with a smaller chip area.

  A field effect transistor integrated circuit according to a second aspect is the integrated circuit according to the first aspect, wherein the conductive material and the wiring metal form a microstrip line.

  A microstrip line can be formed by forming a through hole only in a semiconductor layer, and a high-frequency integrated circuit can be formed more easily with a small chip area.

  According to a third aspect of the present invention, there is provided the field effect transistor integrated circuit according to the first or second aspect, wherein a substrate that has better heat dissipation than the conductive material is formed above the wiring metal.

  With such a configuration, it is possible to realize a field effect transistor integrated circuit that is excellent in heat dissipation and capable of high output operation.

The field effect transistor integrated circuit according to claim 4 is the integrated circuit according to claim 3, wherein the substrate excellent in heat dissipation is made of SiC or AlN.
With such a configuration, it is possible to realize a field effect transistor integrated circuit capable of improving heat dissipation by bonding a substrate having a higher thermal conductivity and capable of higher output operation.

  The field effect transistor integrated circuit according to claim 5 is the integrated circuit according to claim 4, wherein at least a part of the conductive material is formed of a thick metal film.

  With such a configuration, a field effect transistor integrated circuit having a small chip area and excellent heat dissipation can be realized more easily without bonding different types of substrates.

  A field effect transistor integrated circuit according to a sixth aspect is the integrated circuit according to the fifth aspect, wherein the metal thick film is composed of a plated layer of Au, Ag, or Cu.

  With such a configuration, the thick metal film can be easily formed by plating, so that a field effect transistor integrated circuit having a small chip area and excellent heat dissipation can be realized more easily.

  A field effect transistor integrated circuit according to a seventh aspect is the integrated circuit according to the first and second aspects, wherein at least a part of the conductive material is formed of a conductive semiconductor substrate.

  With such a configuration, for example, when a Si semiconductor substrate is used, it is possible to realize a field effect transistor integrated circuit that is excellent in processability, is cheaper, and has a small chip area.

  The field effect transistor integrated circuit according to claim 8 is configured such that in the integrated circuit according to claim 7, an electrode containing AuSn is formed so as to be positioned between the semiconductor layer and the conductive semiconductor substrate. .

  With such a configuration, by using AuSn, the conductive semiconductor substrate and the semiconductor layer can be bonded more easily and at a low temperature.

  10. The field effect transistor integrated circuit according to claim 9, wherein the dielectric constant is located between the semiconductor layer and the conductive material, or between the semiconductor layer and the wiring metal. An insulating film having a rate of less than 3.9 is formed, and one of the electrodes is electrically connected to the conductive material or wiring metal through an opening formed in the insulating film.

  With this configuration, the ground between the microstrip line and the wiring can be formed with a thick film having a low dielectric constant, thereby realizing a field effect transistor integrated circuit in which microstrip lines with smaller conductor losses are integrated. Is possible.

  A field effect transistor integrated circuit according to a tenth aspect is the integrated circuit according to the ninth aspect, wherein the insulating film is made of benzocyclobutene.

  By adopting such a configuration, it is possible to realize a field effect transistor integrated circuit in which benzocyclobutene has a relative dielectric constant as small as 2.5 and a microstrip line having a smaller conductor loss is integrated.

  The field effect transistor integrated circuit according to claim 11 is the integrated circuit according to claim 1, wherein a high resistance region is formed in a part of a surface of the semiconductor layer where the electrode is formed, At least one of the through holes is configured to penetrate the high resistance region.

  With such a configuration, the gate electrode and the conductive material or the wiring metal can be connected through the through hole, so that a field effect transistor integrated circuit with a smaller chip area can be realized.

  13. The field effect transistor integrated circuit according to claim 12, wherein in the integrated circuit according to claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, the compound semiconductor in which the semiconductor layer contains nitrogen. It is comprised by.

  By adopting such a configuration, the nitride compound semiconductor has a high saturation drift speed, for example, a field effect transistor capable of operating at a higher speed can be realized by shortening the gate length, and a breakdown electric field is large. Even when the dimensions are reduced, it is possible to realize a field effect transistor capable of operating at a high output with a high withstand voltage and an integrated circuit thereof.

  The field effect transistor integrated circuit according to claim 13 is the integrated circuit according to claim 13, wherein the semiconductor layer includes a heterojunction of AlGaN and GaN.

  By adopting such a configuration, it is possible to realize a field effect transistor integrated circuit capable of realizing a high sheet carrier concentration and high mobility at the interface of the heterojunction, and capable of operating at a high speed with a smaller parasitic resistance. .

  15. The method of manufacturing a field effect transistor integrated circuit according to claim 14, wherein a step of forming a semiconductor layer having a channel region on a substrate, a step of forming a through hole penetrating the semiconductor layer and reaching the substrate surface, and the semiconductor Forming a source, drain and gate electrodes on the surface of the layer; forming a conductive material electrically connected to any of the electrodes; separating the substrate from the semiconductor layer; And a step of forming a wiring metal electrically connected to the electrode.

  By adopting such a configuration, the through hole can be formed only in the semiconductor layer without forming the through hole in the substrate used for crystal growth, and the electrode can be formed on the back surface through this, so it is more convenient and A field effect transistor or an integrated circuit thereof can be formed with a small chip area.

  16. The method of manufacturing a field effect transistor integrated circuit according to claim 15, wherein a second wiring metal is formed on a substrate that is more radiant than the conductive material, and bonded to the wiring metal. It is the structure including the process to make.

  With such a configuration, it is possible to realize a field effect transistor integrated circuit that is excellent in heat dissipation and capable of high output operation.

  The method of manufacturing a field effect transistor integrated circuit according to claim 16, wherein in the manufacturing method of claim 14, the step of bonding the wiring metal to a holding material, the step of bonding a semiconductor substrate to the conductive material, The holding material is separated from the wiring metal.

  By adopting such a configuration, the substrate used for crystal growth is separated after adhering the semiconductor layer to the holding material, and the semiconductor layer is transferred to the semiconductor substrate side to remove the holding material. It becomes possible to easily transfer a thin semiconductor layer of about μm to an arbitrary semiconductor substrate.

  The field effect transistor integrated circuit manufacturing method according to claim 17, wherein, in the manufacturing method according to claim 14, in the step of separating the substrate from the semiconductor layer, light is irradiated from the back surface of the substrate, and the irradiated light is Separation is performed by forming a layer formed by decomposing the semiconductor layer inside the semiconductor layer without being absorbed by the substrate and being absorbed by a part of the semiconductor layer.

  With such a structure, the substrate used for crystal growth and the semiconductor layer can be separated in a large area and with good reproducibility.

  According to a method for manufacturing a field effect transistor integrated circuit according to claim 18, in the manufacturing method according to claim 17, the light source of light irradiated from the back surface of the substrate is a laser that oscillates in a pulse shape.

  With such a configuration, the output power of the irradiated light can be significantly increased, and the semiconductor layer can be easily separated.

  A field effect transistor integrated circuit manufacturing method according to a nineteenth aspect is the manufacturing method according to the fourteenth, fifteenth, sixteenth, seventeenth and eighteenth aspects, wherein the semiconductor layer is made of a compound semiconductor containing nitrogen.

  By adopting such a configuration, the nitride compound semiconductor has a high saturation drift speed, for example, a field effect transistor capable of operating at a higher speed can be realized by shortening the gate length, and a breakdown electric field is large. Even when the dimensions are reduced, it is possible to realize a field effect transistor capable of operating at a high output with a high withstand voltage and an integrated circuit thereof.

  A field effect transistor integrated circuit manufacturing method according to claim 20 is the manufacturing method according to claim 19, wherein the substrate is made of sapphire or Si.

  With this configuration, an AlGaN / GaN heterojunction with excellent crystallinity can be epitaxially grown on the substrate, so that a GaN-based field effect transistor integrated circuit capable of higher speed operation and higher output operation can be realized. Is possible.

  The field effect transistor integrated circuit manufacturing method according to claim 21 is the manufacturing method according to claim 19, wherein the semiconductor substrate is made of Si.

  By adopting such a configuration, by transferring the semiconductor layer to the Si substrate, it is possible to transfer the semiconductor layer to a lower cost semiconductor substrate, and to realize a field effect transistor integrated circuit having a smaller chip area at a lower cost. It becomes possible.

A field effect transistor integrated circuit manufacturing method according to a twenty-second aspect is the manufacturing method according to the nineteenth aspect, wherein the holding material is formed of a polymer material film.
With such a structure, the polymer material film is rich in plasticity and can be uniformly bonded to a large area wafer without being affected by the warp of the semiconductor layer or the substrate used for crystal growth.

  According to the field effect transistor integrated circuit and the method of manufacturing the same of the present invention, a microstrip line can be easily formed without forming a through hole in a substrate used for crystal growth. An integrated circuit can be realized. Furthermore, a microstrip line with smaller conductor loss can be realized by inserting a low dielectric constant film between the wiring metal constituting the microstrip line and the conductive material. In addition, an integrated circuit excellent in heat dissipation can be realized by bonding a field effect transistor integrated circuit to a substrate excellent in heat dissipation.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view of a field effect transistor integrated circuit according to a first embodiment of the present invention. In this figure, 101 is Au plating for source electrode, 102 is BCB (benzocyclobutene) film, 103 is SiN film, 104 is high resistance region, 105 is n-type AlGaN layer, 106 is undoped GaN layer, 107 is Ti / Al source electrode, 108 Ti / Al drain electrode, 109 PdSi gate electrode, 110 Au-plated wiring for drain electrode, 111 Au-plated wiring for gate electrode.

  FIG. 1 shows the structure of a field effect transistor using a nitride semiconductor formed by separating and removing a substrate used for epitaxial growth in the first embodiment. Here, for example, a BCB film, a SiN passivation film, an electrode constituting a field effect transistor, an n-type AlGaN layer, an undoped GaN layer, and a wiring metal on the surface side are formed in this order on an Au plating having a thickness of 10 μm or more, A part of the surface of the n-type AlGaN layer has a high resistance by, for example, selective oxidation or ion implantation. Further, a through hole is formed in the BCB film and the SiN film below the source electrode, and the Au plating layer and the source electrode are electrically connected. Through holes are formed in the undoped GaN and n-type AlGaN layers above the pad portions of the drain electrode and the gate electrode, and Au plating wirings for the drain and gate electrodes are formed above the through holes, respectively. Here, a wiring metal is formed on the n-type AlGaN layer or the high resistance region, and a microstrip line is formed between the source electrode and the Au plating, and this is used as one or a plurality of the field effect transistors. In combination, the millimeter wave integrated circuit may be formed. In order to improve the high frequency characteristics of the transistor, a recess structure may be formed around the gate electrode, and a so-called cap layer such as a low-resistance AlGaN / GaN periodic structure or an InAlGaN quaternary mixed crystal layer may be formed on both sides of the gate. In this embodiment, the substrate used for epitaxial growth is separated and removed, and an Au plating layer is formed on the epitaxial growth layer with the BCB film interposed therebetween, thereby realizing a field effect transistor excellent in heat dissipation. Further, by increasing the thickness of the BCB film, the BCB film has a relative dielectric constant of about 2.5 and can reduce the parasitic capacitance, so that a field effect transistor having excellent high frequency characteristics can be realized. In addition, a microstrip line can be realized only by a process of forming a through hole only in the epitaxial growth layer without forming a through hole in the substrate used for epitaxial growth, and a high-frequency integrated circuit can be formed more easily with a small chip area. Since BCB has a low dielectric constant as described above, the line width of the microstrip line can be increased, and a microstrip line with smaller conductor loss can be realized.

In order to fabricate the field effect transistor integrated circuit shown in FIG. 1, for example, the manufacturing method shown in FIG. 2 can be considered. FIG. 2 is a block diagram showing a method of manufacturing a field effect transistor integrated circuit in the first embodiment of the present invention. In the figure, 201 is a sapphire substrate, 202 is an undoped GaN layer, 203 is an n-type AlGaN layer, 204 is a high resistance region, 205 is a Ti / Al source electrode, 206 is a Ti / Al drain electrode, and 207 is a PdSi gate electrode. , 208 is a SiN film, 209 is a BCB film, 210 is a source wiring Au plating, 211 is a polymer holding material film, 212 is a drain Au plating wiring, and 213 is a gate Au plating wiring. Here, for example, after forming an undoped GaN layer and an n-type AlGaN layer in this order on a sapphire substrate by metal organic chemical vapor deposition (MOCVD), high resistance is obtained as shown in FIG. Forming a control region. The n-type AlGaN layer has an Al composition of 26%, and Si is doped in the whole layer or a part thereof. A typical carrier concentration is 4 × 10 ¹³ cm ⁻³ . Here, for example, when a crystal is grown on a sapphire (0001) plane, a sheet carrier of about 1 × 10 ¹³ cm ⁻³ is generated at the heterointerface even if undoped on the GaN (0001) plane due to the influence of the internal electric field due to polarization. Not necessary. In addition, a GaN (11-20) plane is formed on the sapphire (1-102) plane, the so-called R plane, and a polarization field and sheet carrier due to this polarization do not occur on this plane. Can be formed. The high resistance region is formed, for example, by selective oxidation or selective implantation of ions such as B. Further, a through hole for completely removing the epitaxial growth layer is formed in a part of the portion where the gate electrode or the drain electrode is formed by dry etching such as ICP (Inductive Coupled Plasma) etching. Etching is stopped at the surface of the sapphire and has a depth of about 2 to 3 μm, for example. Further, Ti / Al source and drain electrodes and a PdSi gate electrode are formed by, for example, electron beam evaporation and a lift-off method. The through hole is filled with Ti / Ai or PdSi, or is filled with an electrode such as Au by vacuum deposition separately from the electrode formation. The through hole of the gate electrode is formed by a pad portion formed on the surface of the high resistance region. Subsequently, for example, a 500 nm SiN film is formed by, for example, a plasma CVD (Chemical Vapor Deposition) method, and a BCB film is formed thereon by a coating method to have a thickness of, for example, 3 μm. Further, an opening is formed in the SiN film and the BCB film on the source electrode, and a source wiring is formed by Au plating so as to fill the opening. The source wiring is formed so as to cover the entire BCB film. A polymer film holding material having a thickness of about 100 μm is bonded to the Au plated wiring. The polymer film is made of polyester, for example, and is connected to the Au-plated wiring through an adhesive layer that foams when heated and loses its adhesive strength. Subsequently, a KrF excimer laser (wavelength 248 nm) is irradiated from the back surface of the sapphire substrate while scanning in the wafer surface. The irradiated laser light is not absorbed by the sapphire substrate, but is absorbed only by GaN. Therefore, GaN bonds are decomposed near the interface with the sapphire substrate due to local heat generation. As a result, the sapphire substrate is separated, and a GaN-based transistor structure can be obtained. As a light source to be used, the third harmonic of a YAG laser (wavelength 355 nm) or a mercury lamp emission line (wavelength 365 nm) may be used. Further, as a method of separating the substrate, the substrate may be removed by polishing. Finally, the holding material is heated to, for example, 150 ° C. and separated. As described above, the GaN-based transistor structure separated from the sapphire substrate has through holes formed in the drain and gate electrode portions, and the drain and gate wiring are Au plated on the surface of the undoped GaN layer through the through holes. Form with. The wiring metal and source wiring may form a microstrip line. In this embodiment, a field effect transistor excellent in heat dissipation and high frequency characteristics can be realized with a smaller chip area.

  FIG. 3 is a cross-sectional view of a field effect transistor integrated circuit according to the second embodiment of the present invention. In the figure, 301 is a semi-insulating SiC substrate, 302 is an Au / AuSn / Au electrode, 303 is a SiN film, 304 is an n-type AlGaN layer, 305 is an undoped GaN layer, 306 is an AlN buffer layer, and 307 is a Ti / Al Source electrode, 308 is Ti / Al drain electrode, 309 is PdSi gate electrode, 310 is high resistance region, 311 is Au plating wiring for source electrode, 312 is Au plating wiring for drain electrode, 313 is Au plating wiring for gate electrode It is.

  FIG. 1 shows the structure of a field effect transistor using a nitride semiconductor formed by separating and removing a substrate used for epitaxial growth in the second embodiment. Here, for example, an Au / AuSn / Au electrode is formed on a semi-insulating SiC substrate having a thickness of 150 μm or more, and this electrode is connected to the wiring metal of the drain and gate electrodes formed by Au plating. Above these wiring metals, a SiN passivation film, an electrode constituting a field effect transistor, an n-type AlGaN layer, an undoped GaN layer, an AlN buffer layer, a BCB film, and a source wiring metal on the surface side are formed in this order, A part of the surface of the n-type AlGaN layer has a high resistance by, for example, selective oxidation or ion implantation. Furthermore, through holes are formed in the SiN film below the drain and gate electrodes, and the Au / AuSn / Au electrode and the source and drain electrodes are electrically connected. A through hole is formed above the source electrode in the AlN buffer layer, undoped GaN, and n-type AlGaN layer, and an Au plated wiring for the source electrode is formed above the through hole. A field effect transistor is formed by pulling the Au / AuSn / Au electrode out of the chip. As a form of drawing out the electrode, the area of the upper field effect transistor is made smaller and the area of the lower semi-insulating SiC substrate is made smaller to provide a lead-out portion, or a through-hole is also provided in the semi-insulating SiC substrate, and the back side of the SiC substrate It is also conceivable to form an electrode pattern. Here, a wiring metal is formed on the n-type AlGaN layer or the high resistance region, and a microstrip line is formed between the source electrode and the Au plating, and this is used as one or a plurality of the field effect transistors. In combination, the millimeter wave integrated circuit may be formed. In this embodiment, since the parasitic capacitance can be reduced by increasing the thickness of the BCB film, a field effect transistor having excellent high frequency characteristics can be realized. In addition, a microstrip line can be realized only by a process of forming a through hole only in an epitaxial growth layer without forming a through hole in a substrate used for epitaxial growth, and a high-frequency integrated circuit can be formed more easily with a small chip area. Since BCB has a low dielectric constant as described above, a microstrip line with smaller conductor loss can be realized.

  In order to fabricate the field effect transistor integrated circuit shown in FIG. 3, for example, the manufacturing method shown in FIG. 4 can be considered. FIG. 4 is a block diagram showing a method of manufacturing a field effect transistor integrated circuit in the second embodiment of the present invention. In the figure, 401 is a Si (111) substrate, 402 is an AlN buffer layer, 403 is an undoped GaN layer, 404 is an n-type AlGaN layer, 405 is a high resistance region, 406 is a Ti / Al source electrode, and 407 is a Ti / Al source electrode. Al drain electrode, 408 is PdSi gate electrode, 409 is drain Au plating wiring, 410 is gate Au plating wiring, 411 is SiN film, 412 is semi-insulating SiC substrate, 413 is Au / AuSn / Au electrode, 414 is BCB film , 415 is a source wiring Au plating. Here, for example, after forming an AlN buffer layer, an undoped GaN layer, and an n-type AlGaN layer in this order on a Si (111) substrate by MOCVD, a high resistance region and a Ti / Al source are formed as shown in FIG. -A drain electrode and a PdSi gate electrode are formed. After the electrode formation, a SiN passivation film is formed by a plasma CVD method, for example, about 300 nm. On the gate pad electrode portion and the drain electrode formed on the high resistance region, for example, after forming an opening by reactive ion etching (RIE), the n-type AlGaN layer is formed through these openings. Au plated wiring connected to the drain and gate electrodes is formed (FIG. 4C). Separately, a semi-insulating SiC substrate is prepared, and an Au / AuSn / Au electrode pattern is formed on the surface side. The Au / AuSn / Au electrode pattern formed on the SiC substrate is bonded to the Au plating wiring formed on the Si substrate by applying pressure and heating. After the wafer bonding, the Si substrate is selectively removed with a mixed solution of hydrofluoric acid and nitric acid, for example. A BCB film is formed on the AlN buffer layer exposed after removing the Si substrate. Through holes are formed in the BCB film, the AlN buffer layer, the undoped GaN layer, and the n-type AlGaN layer above the source electrode. The through holes are formed by dry etching such as ICP (Inductive Coupled Plasma) etching. Source wiring Au plating is formed on the BCB film so as to fill the through hole. A microstrip line may be formed by electrode metal on the n-type AlGaN layer and source wiring plating. In the present embodiment, a field effect transistor excellent in high frequency characteristics and a microstrip line with low conductor loss can be realized by using a BCB film having excellent heat dissipation through a SiC substrate and having a low dielectric constant. In addition, a high-frequency integrated circuit can be realized with a smaller chip area.

  FIG. 5 is a cross-sectional view of a field effect transistor integrated circuit according to the third embodiment of the present invention. In the figure, 501 is a Si (100) substrate, 502 is an undoped GaN layer, 503 is an n-type AlGaN layer, 504 is a Ti / Al source electrode, 505 is a Ti / Al drain electrode, 506 is a PdSi gate electrode, and 507 is a high The resistance region, 508 is an SiN film, 509 is an Au plated wiring for a source electrode, 510 is an Au / AuSn / Au electrode, 511 is an Au plated wiring for a drain electrode, and 512 is an Au plated wiring for a gate electrode.

  FIG. 5 shows a structure of a field effect transistor using a nitride semiconductor formed by separating and removing a substrate used for epitaxial growth in the third embodiment. Here, for example, an Au / AuSn / Au electrode, an Au-plated wiring for a source electrode, an undoped GaN layer, and an n-type AlGaN layer are formed in this order on a Si (100) substrate having a thickness of 150 μm or more. A high resistance region is formed in a part of the undoped GaN layer, and source / drain and gate electrodes are formed on the surface of the n-type AlGaN layer. The source electrode and the Au plating wiring for the source electrode are connected through a through hole formed in the undoped GaN layer and the n-type AlGaN layer. An SiN film is formed on the electrode formed in contact with the n-type AlGaN layer and the n-type AlGaN layer, and an opening is formed in the SiN film above the drain electrode and the gate pad electrode. Through this opening, a drain electrode Au plated wiring and a gate electrode Au plated wiring are formed on the SIN surface. These wiring metals may form a microstrip line between the Au plating for the source electrode and combine it with one or more of the field effect transistors to form a millimeter wave integrated circuit. In this embodiment, a field effect transistor excellent in heat dissipation can be realized by separating the sapphire substrate and transferring it onto the Si substrate. In addition, a microstrip line can be realized only by a process of forming a through hole only in an epitaxial growth layer without forming a through hole in a substrate used for epitaxial growth, and a high-frequency integrated circuit can be formed more easily with a small chip area.

  In order to fabricate the field effect transistor integrated circuit shown in FIG. 5, for example, the manufacturing method shown in FIG. 6 can be considered. FIG. 6 is a block diagram showing a method of manufacturing a field effect transistor integrated circuit in the third embodiment of the present invention. In the figure, 601 is a sapphire substrate, 602 is an undoped GaN layer, 603 is an n-type AlGaN layer, 604 is a high resistance region, 605 is a Ti / Al source electrode, 606 is a Ti / Al drain electrode, and 607 is a PdSi gate electrode. , 608 is drain Au plating wiring, 609 is gate Au plating wiring, 610 is SiN film, 611 is polymer holding material film, 612 is Si (100) substrate, 613 is source Au plating wiring, 614 is Au / AuSn / Au Electrode. Here, for example, after forming an undoped GaN layer and an n-type AlGaN layer in this order on a sapphire substrate by MOCVD, a high resistance region, a high resistance region, and a Ti / Al source / drain electrode as shown in FIG. And forming a PdSi gate electrode. After the electrode formation, a SiN passivation film is formed by a plasma CVD method, for example, about 300 nm. Au plating connected to the drain and gate electrodes of the n-type AlGaN layer through these openings after forming openings on the gate pad electrode and drain electrodes formed on the high resistance region, for example, by RIE A wiring is formed (FIG. 6 (c)). A polymer film holding material having a thickness of about 100 μm is bonded to the Au plated wiring. Similar to the first embodiment, the polymer film is connected to the Au-plated wiring through an adhesive layer that is foamed by heating and loses its adhesive force. Subsequently, from the rear surface of the sapphire substrate, a KrF excimer laser (wavelength 248 nm) is irradiated in a scanning manner within the wafer surface, and the sapphire substrate is separated by decomposing GaN near the interface. After separating the sapphire substrate, a through hole is formed in the source electrode portion from the exposed undoped GaN surface by, for example, ICP dry etching. A source Au plated wiring is formed on the surface of the undoped GaN layer so as to fill the through hole. Separately, a Si (100) substrate is prepared, and Au / AuSn / Au electrodes are formed on the surface side. The Au / AuSn / Au electrode formed on the Si substrate is bonded to the Au plated wiring formed on the Si substrate by applying pressure and heating. After the wafer bonding, the Si substrate is selectively removed with a mixed solution of hydrofluoric acid and nitric acid, for example. Further, the polymer holding material film is separated by heating to 150 ° C., for example. As described above, a through hole is formed in the source electrode portion of the GaN transistor structure separated from the sapphire substrate, and the source electrode is connected to the Si substrate through the through hole. A microstrip line may be formed by a SiN passivation film and the source Au plating wiring. In this embodiment, a field effect transistor excellent in heat dissipation and high frequency characteristics can be realized with a smaller chip area.

The Si substrate and sapphire substrate used for crystal growth of GaN used in the embodiments shown in FIGS. 1 to 6 may have any plane orientation, and for example, an off-angle from a representative plane such as the (0001) plane or the (111) plane. It may be a plane orientation. In particular, on nonpolar surfaces such as the (11-20) plane and the (1-100) plane, a transistor exhibiting normally-off characteristics without being affected by polarization can be easily configured, which is advantageous as a power switching element. The substrate used for crystal growth may be SiC, ZnO, Si, GaAs, GaP, InP, LiGaO _2, LiAlO ₂ or a mixed crystal thereof. The buffer layer is not only an AlN layer on Si, for example, as long as a good GaN crystal can be formed on the buffer layer, for example, a shape containing a GaN / AlN periodic structure, or GaN or a nitride semiconductor layer of any composition ratio. Good. The epitaxial growth layer of the field effect transistor shown here may include any composition ratio or any multilayer structure as long as the desired transistor characteristics can be realized, and the crystal growth method is not MOCVD, for example, molecular beam epitaxy (Molecular Beam Epitaxy). Epitaxy (MBE) or hydride vapor phase epitaxy (HVPE) may be included. The epitaxial growth layer of the field effect transistor may contain a group V element such as As or P or a group III element such as B as a constituent element.

  The field effect transistor integrated circuit according to the present invention is useful as a high-frequency transistor used in an on-vehicle radar, a mobile phone base station, or the like, or an integrated circuit thereof.

It is sectional drawing which shows the field effect transistor in 1st Example of this invention. It is a block diagram which shows the manufacturing method of the field effect transistor in 1st Example of this invention. It is sectional drawing which shows the field effect transistor in the 2nd Example of this invention. It is a block diagram which shows the manufacturing method of the field effect transistor in 2nd Example of this invention. It is sectional drawing which shows the field effect transistor in the 3rd Example of this invention. It is a block diagram which shows the manufacturing method of the field effect transistor in the 3rd Example of this invention.

Explanation of symbols

101 Au plating for source electrode
102 BCB (benzocyclobutene) membrane
103 SiN film
104 High resistance region
105 n-type AlGaN layer
106 Undoped GaN layer
107 Ti / Al source electrode
108 Ti / Al drain electrode
109 PdSi gate electrode
110 Au plated wiring for drain electrode
111 Au-plated wiring for gate electrode
201 Sapphire substrate
202 Undoped GaN layer
203 n-type AlGaN layer
204 High resistance region
205 Ti / Al source electrode
206 Ti / Al drain electrode
207 PdSi gate electrode
208 SiN film
209 BCB membrane
210 Source wiring Au plating
211 Polymer holding material film
212 Drain Au plating wiring
213 Gate Au plating wiring
301 Semi-insulating SiC substrate
302 Au / AuSn / Au electrode
303 SiN film
304 n-type AlGaN layer
305 Undoped GaN layer
306 AlN buffer layer
307 Ti / Al source electrode
308 Ti / Al drain electrode
309 PdSi gate electrode
310 High resistance region
311 Au plated wiring for source electrode
312 Au plated wiring for drain electrode
313 Au plating wiring for gate electrode
401 Si (111) substrate
402 AlN buffer layer
403 Undoped GaN layer
404 n-type AlGaN layer
405 High resistance region
406 Ti / Al source electrode
407 Ti / Al drain electrode
408 PdSi gate electrode
409 Drain Au plating wiring
410 Gate Au plating wiring
411 SiN film
412 Semi-insulating SiC substrate
413 Au / AuSn / Au electrode
414 BCB membrane
415 Source wiring Au plating
501 Si (100) substrate
502 Undoped GaN layer
503 n-type AlGaN layer
504 Ti / Al source electrode
505 Ti / Al drain electrode
506 PdSi gate electrode
507 High resistance region
508 SiN film
509 Au plated wiring for source electrode
510 Au / AuSn / Au electrode
511 Au plated wiring for drain electrode
512 Au plated wiring for gate electrode
601 Sapphire substrate
602 Undoped GaN layer
603 n-type AlGaN layer
604 High resistance region
605 Ti / Al source electrode
606 Ti / Al drain electrode
607 PdSi gate electrode
608 Drain Au plating wiring
609 Gate Au plating wiring
610 SiN film
611 Polymer holding material film
612 Si (100) substrate
613 Source Au plating wiring
614 Au / AuSn / Au electrode

Claims (22)

  A semiconductor layer is formed in this order above the conductive material, and a source, a drain, and a gate electrode are formed in contact with the first semiconductor layer and positioned between the conductive material and the semiconductor layer, and A through hole is formed in the semiconductor layer, and through the through hole, one of the electrodes is electrically connected to a wiring metal formed on the surface of the semiconductor layer on which the electrode is not formed, A field effect transistor integrated circuit, wherein a conductive material and one of the electrodes are electrically connected.   2. The field effect transistor integrated circuit according to claim 1, wherein the conductive material and the wiring metal form a microstrip line.   3. The field effect transistor integrated circuit according to claim 1, wherein a substrate that is more radiant than the conductive material is formed above the wiring metal.   4. The field effect transistor integrated circuit according to claim 3, wherein the substrate excellent in heat dissipation is made of SiC or AlN.   3. The field effect transistor integrated circuit according to claim 1, wherein at least a part of the conductive material is formed of a metal thick film.   6. The field effect transistor integrated circuit according to claim 5, wherein the thick metal film is formed of a plated layer of Au, Ag, or Cu.   3. The field effect transistor integrated circuit according to claim 1, wherein at least a part of the conductive material is formed of a conductive semiconductor substrate.   8. The field effect transistor integrated circuit according to claim 7, wherein an electrode containing AuSn is formed so as to be positioned between the semiconductor layer and the conductive semiconductor substrate.   An insulating film having a relative dielectric constant of less than 3.9 is formed between the semiconductor layer and the conductive material, or between the semiconductor layer and the wiring metal, and through an opening formed in the insulating film. 3. The field effect transistor integrated circuit according to claim 1, wherein any one of the electrodes and the conductive material or the wiring metal are electrically connected.   10. The field effect transistor integrated circuit according to claim 9, wherein the insulating film is made of benzocyclobutene.   A high resistance region is formed in a part of a surface of the semiconductor layer where the electrode is formed, and at least one of the through holes is formed so as to penetrate the high resistance region. The field effect transistor integrated circuit according to claim 1 or 2.   The field effect transistor integrated circuit according to claim 1, wherein the semiconductor layer is made of a compound semiconductor containing nitrogen.   13. The field effect transistor integrated circuit according to claim 12, wherein the semiconductor layer includes a heterojunction of AlGaN and GaN. Forming a semiconductor layer having a channel region on a substrate plate;
Forming a through hole penetrating the semiconductor layer and reaching the substrate surface;
Forming a source, a drain and a gate electrode on the surface of the semiconductor layer;
Forming a conductive material electrically connected to any of the electrodes; separating the substrate from the semiconductor layer;
A method of manufacturing a field effect transistor integrated circuit comprising the step of forming a wiring metal electrically connected to the electrode through the through hole.   15. The method of manufacturing a field effect transistor integrated circuit according to claim 14, further comprising a step of forming a second wiring metal on a substrate that has better heat dissipation than the conductive material and bonding the second wiring metal to the wiring metal.   15. The electric field according to claim 14, comprising a step of bonding the wiring metal to a holding material, a step of bonding a semiconductor substrate to the conductive material, and a step of separating the holding material from the wiring metal. Manufacturing method of effect transistor integrated circuit.   In the step of separating the substrate from the semiconductor layer, light is irradiated from the back surface of the substrate, and the irradiated light is not absorbed by the substrate but is absorbed by a part of the semiconductor layer, and the semiconductor layer is inside the semiconductor layer. 15. The method of manufacturing a field effect transistor integrated circuit according to claim 14, wherein the separation is performed by forming a layer formed by decomposing.   18. The method of manufacturing a field effect transistor integrated circuit according to claim 17, wherein a light source of light irradiated from the back surface of the substrate is a laser that oscillates in a pulse shape.   The method of manufacturing a field effect transistor integrated circuit according to claim 14, wherein the semiconductor layer is formed of a compound semiconductor containing nitrogen.   20. The method of manufacturing a field effect transistor integrated circuit according to claim 19, wherein the substrate is made of sapphire or Si.   20. The method of manufacturing a field effect transistor integrated circuit according to claim 19, wherein the semiconductor substrate is made of Si.   20. The method of manufacturing a field effect transistor integrated circuit according to claim 19, wherein the holding material is made of a polymer material film.

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