SG11201807164XA - Circuit arrangement, method of forming and operating the same - Google Patents

Circuit arrangement, method of forming and operating the same

Info

Publication number
SG11201807164XA
SG11201807164XA SG11201807164XA SG11201807164XA SG11201807164XA SG 11201807164X A SG11201807164X A SG 11201807164XA SG 11201807164X A SG11201807164X A SG 11201807164XA SG 11201807164X A SG11201807164X A SG 11201807164XA SG 11201807164X A SG11201807164X A SG 11201807164XA
Authority
SG
Singapore
Prior art keywords
circuit arrangement
international
driver circuit
spin
pct
Prior art date
Application number
SG11201807164XA
Inventor
Sunny Yan Hwee Lua
Aarthy Mani
Original Assignee
Agency Science Tech & Res
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency Science Tech & Res filed Critical Agency Science Tech & Res
Publication of SG11201807164XA publication Critical patent/SG11201807164XA/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/45—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of non-linear magnetic or dielectric devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1693—Timing circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1697—Power supply circuits

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property , Organization IIIM141101110101011111 $1111101110101111110110011101M10 ill OEN International Bureau .. ..... ..Yi j (10) International Publication Number (43) International Publication Date ..... ...r .....1 WO 2017/146644 Al 31 August 2017 (31.08.2017) WIPO I PCT (51) International Patent Classification: (72) Inventors: LUA, Sunny Yan Hwee; c/o Data Storage In- H03K 19/18 (2006.01) H01L 43/08 (2006.01) stitute, 2 Fusionopolis Way, #08-01 DSI, Innovis, Singa- G11C 11/16 (2006.01) pore 138634 (SG). MANI, Aarthy; c/o Data Storage Insti- tute, 2 Fusionopolis Way, #08-01 DSI, Innovis, Singapore (21) International Application Number: 138634 (SG). PCT/SG2017/050067 (74) Agent: VIERING, JENTSCHURA & PARTNER LLP; (22) International Filing Date: P.O. Box 1088, Rochor Post Office, Rochor Road, Singa- 16 February 2017 (16.02.2017) pore 911833 (SG). (25) Filing Language: English (81) Designated States (unless otherwise indicated, for every (26) Publication Language: English kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, (30) Priority Data: BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, 10201601428W 25 February 2016 (25.02.2016) SG DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, (71) Applicant: AGENCY FOR SCIENCE, TECHNOLOGY HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, AND RESEARCH [SG/SG]; 1 Fusionopolis Way, #20-10 KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, Connexis, Singapore 138632 (SG). MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, [Continued on next page] = (54) Title: CIRCUIT ARRANGEMENT, METHOD OF FORMING AND OPERATING THE SAME (57) : Various embodiments may provide a circuit arrangement. FIG. 2 - _ 200 The circuit arrangement may include a first spin-orbit torque magnetic — tunnel junction cell, a second spin-orbit torque magnetic tunnel junction / cell, . first driver circuit arrangement \ _ a first driver circuit arrangement, a second driver circuit arrange- ment, and a read circuit arrangement. The circuit arrangement allows for the operation of a non-volatile flip-flop based on spin-orbit torque effect. — — 202 \ 206 204 — first SOT MTJ cell / second SOT MTJ cell / . . 208 I \ 210 1-1 71. 71. second driver circuit arrangement read circuit arrangement 71. 1-1 IN 1-1 0 ei . . O WO 2017/146644 All#110HOMOIDEMOIDEMOMMEHMOIMMEDIMIE (84) RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. Designated States (unless otherwise indicated, for every DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ GW, KM, ML, MR, NE, SN, TD, TG). , kind of regional protection available): ARIPO (BW, GH, Published: GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, — TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, with international search report (Art. 21(3)) TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE,
SG11201807164XA 2016-02-25 2017-02-16 Circuit arrangement, method of forming and operating the same SG11201807164XA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG10201601428W 2016-02-25
PCT/SG2017/050067 WO2017146644A1 (en) 2016-02-25 2017-02-16 Circuit arrangement, method of forming and operating the same

Publications (1)

Publication Number Publication Date
SG11201807164XA true SG11201807164XA (en) 2018-09-27

Family

ID=59686389

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201807164XA SG11201807164XA (en) 2016-02-25 2017-02-16 Circuit arrangement, method of forming and operating the same

Country Status (3)

Country Link
US (1) US10453511B2 (en)
SG (1) SG11201807164XA (en)
WO (1) WO2017146644A1 (en)

Families Citing this family (13)

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Publication number Priority date Publication date Assignee Title
WO2018136003A1 (en) * 2017-01-17 2018-07-26 Agency For Science, Technology And Research Memory cell, memory array, method of forming and operating memory cell
US11502188B2 (en) 2018-06-14 2022-11-15 Intel Corporation Apparatus and method for boosting signal in magnetoelectric spin orbit logic
US11476412B2 (en) 2018-06-19 2022-10-18 Intel Corporation Perpendicular exchange bias with antiferromagnet for spin orbit coupling based memory
US11444237B2 (en) * 2018-06-29 2022-09-13 Intel Corporation Spin orbit torque (SOT) memory devices and methods of fabrication
US10447277B1 (en) * 2018-09-04 2019-10-15 University Of Rochester Method of electrical reconfigurability and an electrical reconfigurable logic gate device instrinsically enabled by spin-orbit materials
US11594673B2 (en) 2019-03-27 2023-02-28 Intel Corporation Two terminal spin orbit memory devices and methods of fabrication
US11557629B2 (en) 2019-03-27 2023-01-17 Intel Corporation Spin orbit memory devices with reduced magnetic moment and methods of fabrication
US11683939B2 (en) * 2019-04-26 2023-06-20 Intel Corporation Spin orbit memory devices with dual electrodes, and methods of fabrication
CN112863565B (en) * 2019-11-27 2022-08-23 浙江驰拓科技有限公司 Spin orbit torque-based differential storage unit and preparation method thereof
US11251362B2 (en) 2020-02-18 2022-02-15 International Business Machines Corporation Stacked spin-orbit-torque magnetoresistive random-access memory
JP7028372B2 (en) * 2020-03-05 2022-03-02 Tdk株式会社 Magnetic recording array and magnetoresistive effect unit
CN111540395B (en) * 2020-03-25 2022-11-01 北京航空航天大学 Magnetic random access memory cell and data writing method thereof
CN113782078B (en) * 2021-09-18 2023-10-10 北京航空航天大学 Data processing method and device based on magnetic tunnel junction

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453949A (en) * 1994-08-31 1995-09-26 Exponential Technology, Inc. BiCMOS Static RAM with active-low word line
US8476925B2 (en) * 2010-08-01 2013-07-02 Jian-Gang (Jimmy) Zhu Magnetic switching cells and methods of making and operating same
US9105830B2 (en) 2012-08-26 2015-08-11 Samsung Electronics Co., Ltd. Method and system for providing dual magnetic tunneling junctions using spin-orbit interaction-based switching and memories utilizing the dual magnetic tunneling junctions
KR102154296B1 (en) * 2012-12-18 2020-09-14 삼성전자 주식회사 A driving method of nonvolatile memory device using variable resistive element and the nonvolatile memory device
US9741414B2 (en) 2013-09-24 2017-08-22 National University Of Singapore Spin orbit and spin transfer torque-based spintronics devices
US9384812B2 (en) 2014-01-28 2016-07-05 Qualcomm Incorporated Three-phase GSHE-MTJ non-volatile flip-flop

Also Published As

Publication number Publication date
WO2017146644A1 (en) 2017-08-31
US10453511B2 (en) 2019-10-22
US20190057731A1 (en) 2019-02-21

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