SG11201811063QA - Array data bit inversion - Google Patents

Array data bit inversion

Info

Publication number
SG11201811063QA
SG11201811063QA SG11201811063QA SG11201811063QA SG11201811063QA SG 11201811063Q A SG11201811063Q A SG 11201811063QA SG 11201811063Q A SG11201811063Q A SG 11201811063QA SG 11201811063Q A SG11201811063Q A SG 11201811063QA SG 11201811063Q A SG11201811063Q A SG 11201811063QA
Authority
SG
Singapore
Prior art keywords
logic state
international
cell
boise
transistors
Prior art date
Application number
SG11201811063QA
Inventor
Charles Ingalls
Scott Derner
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of SG11201811063QA publication Critical patent/SG11201811063QA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2275—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Abstract

b-1 425-b-2 r -1- 1 115-b DLREF DL 420-a WL 7110-b 105 -b 420-b 105-c WE 110-ci Cell 240-c 240-d PL 210-b l 400-a \ -210-a 410 430 FIG. 4A (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 28 December 2017 (28.12.2017) WI P0 I PC T Iiiimmomiolollmolommoolomomolomommovom (10) International Publication Number WO 2017/222775 Al (51) International Patent Classification: Gl1C 11/22 (2006.01) (21) International Application Number: PCT/US2017/035452 (22) International Filing Date: 01 June 2017 (01.06.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/188,890 21 June 2016 (21.06.2016) US (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; 8000 S. Federal Way, Boise, ID 83716-9632 (US). (72) Inventors: INGALLS, Charles, L.; 8000 S. Federal Way, Boise, ID 83716-9632 (US). DERNER, Scott, J.; 8000 S. Federal Way, Boise, ID 83716-9632 (US). (74) Agent: HARRIS, Philip, W.; Holland & Hart LLP, P.O. Box 11583, Salt Lake City, UT 84147 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). (54) Title: ARRAY DATA BIT INVERSION (57) : Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state. [Continued on next page] WO 2017/222775 Al IMEDIMOMMIONOIDEMEEHOHMEMERVOIMIE Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(H)) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3))
SG11201811063QA 2016-06-21 2017-06-01 Array data bit inversion SG11201811063QA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/188,890 US9715919B1 (en) 2016-06-21 2016-06-21 Array data bit inversion
PCT/US2017/035452 WO2017222775A1 (en) 2016-06-21 2017-06-01 Array data bit inversion

Publications (1)

Publication Number Publication Date
SG11201811063QA true SG11201811063QA (en) 2019-01-30

Family

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SG11201811063QA SG11201811063QA (en) 2016-06-21 2017-06-01 Array data bit inversion
SG10202002046PA SG10202002046PA (en) 2016-06-21 2017-06-01 Array data bit inversion

Family Applications After (1)

Application Number Title Priority Date Filing Date
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Country Status (8)

Country Link
US (6) US9715919B1 (en)
EP (1) EP3472837A4 (en)
JP (2) JP6705117B2 (en)
KR (2) KR102067365B1 (en)
CN (2) CN109416921B (en)
SG (2) SG11201811063QA (en)
TW (2) TWI675370B (en)
WO (1) WO2017222775A1 (en)

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US10573372B2 (en) * 2018-05-31 2020-02-25 Micron Technology, Inc. Sensing operations in memory by comparing inputs in a sense amplifier
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Also Published As

Publication number Publication date
JP6705117B2 (en) 2020-06-03
US9715919B1 (en) 2017-07-25
EP3472837A1 (en) 2019-04-24
KR20200006187A (en) 2020-01-17
JP6802401B2 (en) 2020-12-16
SG10202002046PA (en) 2020-04-29
CN109416921A (en) 2019-03-01
US20210398582A1 (en) 2021-12-23
TW201812758A (en) 2018-04-01
JP2020091935A (en) 2020-06-11
JP2019525374A (en) 2019-09-05
US20200388316A1 (en) 2020-12-10
US10431282B2 (en) 2019-10-01
EP3472837A4 (en) 2020-02-26
US10043566B2 (en) 2018-08-07
KR20190019196A (en) 2019-02-26
US20200043541A1 (en) 2020-02-06
CN111383680B (en) 2022-04-12
KR102297894B1 (en) 2021-09-06
CN111383680A (en) 2020-07-07
KR102067365B1 (en) 2020-01-16
WO2017222775A1 (en) 2017-12-28
US20180350420A1 (en) 2018-12-06
US10748596B2 (en) 2020-08-18
TWI675370B (en) 2019-10-21
CN109416921B (en) 2020-04-14
US20170365318A1 (en) 2017-12-21
TW201842501A (en) 2018-12-01
US11636890B2 (en) 2023-04-25
TWI636457B (en) 2018-09-21
US11062753B2 (en) 2021-07-13

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