SG11201806244PA - System and method for reducing programming voltage stress on memory cell devices - Google Patents

System and method for reducing programming voltage stress on memory cell devices

Info

Publication number
SG11201806244PA
SG11201806244PA SG11201806244PA SG11201806244PA SG11201806244PA SG 11201806244P A SG11201806244P A SG 11201806244PA SG 11201806244P A SG11201806244P A SG 11201806244PA SG 11201806244P A SG11201806244P A SG 11201806244PA SG 11201806244P A SG11201806244P A SG 11201806244PA
Authority
SG
Singapore
Prior art keywords
international
memory cells
california
local word
word line
Prior art date
Application number
SG11201806244PA
Inventor
Sei Seung Yoon
Anil Kota
Bjorn Grubelich
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of SG11201806244PA publication Critical patent/SG11201806244PA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Storage Device Security (AREA)

Abstract

WO 17 / 15 130 2 Al r 33D CONTROLLER 350 SENSE AMPLIFIER 340 BL PROGRAMMING DECODER 320 (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (10) International Publication Number (43) International Publication Date WO 2017/151302 Al 8 September 2017 (08.09.2017) WIPO I PCT 1111111111111101110101011111010111110111011111111011101111101011111111111110111111 (51) International Patent Classification: G11C 8/08 (2006.01) G1 1C 17/16 (2006.01) G11C 8/14 (2006.01) G11C 17/18 (2006.01) G11C 8/12 (2006.01) (21) International Application Number: PCT/US2017/017725 (22) International Filing Date: 13 February 2017 (13.02.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/061,882 4 March 2016 (04.03.2016) US (71) Applicant: QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration, 5775 Morehouse Drive, San Diego, California 92121-1714 (US). (72) Inventors: YOON, Sei Seung; 5775 Morehouse Drive, San Diego, California 92121-1714 (US). KOTA, Anil; 5775 Morehouse Drive, San Diego, California 92121-1714 (US). GRUBELICH, Bjorn; 5775 Morehouse Drive, San Diego, California 92121-1714 (US). (74) Agent: FOUNTAIN, George; Loza & Loza, LLP, 305 North Second Avenue #127, Upland, California 91786 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, [Continued on next page] (54) Title: SYSTEM AND METHOD FOR REDUCING PROGRAMMING VOLTAGE STRESS ON MEMORY CELL DEVICES (57) : A memory array includes a first subarray of memory cells and a second set of memory cells. The first and second subarrays of memory cells share a set of global word lines. The first and second subarrays of memory cells are coupled to first and second sets of bit lines, respectively. The first subarray includes rows of memory cells coupled to a first set of local word line drivers via a first set of local word lines, respectively. The second subarray includes rows of memory cells coupled to a second set of local word line drivers via a second set of local word lines, respectively. A selected local word line drivers generates a first asserted local word line signal for accessing at least one memory cell for reading or programming purpose in response to re- ceiving a second asserted signal via a global word line and a third as- serted signal. WO 2017/151302 Al 1#11101113101 010IR0101311011011111101n#011 GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(ii)) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3))
SG11201806244PA 2016-03-04 2017-02-13 System and method for reducing programming voltage stress on memory cell devices SG11201806244PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/061,882 US9570192B1 (en) 2016-03-04 2016-03-04 System and method for reducing programming voltage stress on memory cell devices
PCT/US2017/017725 WO2017151302A1 (en) 2016-03-04 2017-02-13 System and method for reducing programming voltage stress on memory cell devices

Publications (1)

Publication Number Publication Date
SG11201806244PA true SG11201806244PA (en) 2018-09-27

Family

ID=57964284

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201806244PA SG11201806244PA (en) 2016-03-04 2017-02-13 System and method for reducing programming voltage stress on memory cell devices

Country Status (9)

Country Link
US (1) US9570192B1 (en)
EP (1) EP3424051B1 (en)
JP (1) JP6487129B1 (en)
KR (1) KR101953876B1 (en)
CN (1) CN109074834B (en)
BR (1) BR112018067658A2 (en)
ES (1) ES2776390T3 (en)
SG (1) SG11201806244PA (en)
WO (1) WO2017151302A1 (en)

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CN109905115B (en) * 2019-02-27 2020-08-04 华中科技大学 Reversible logic circuit and operation method thereof
US10867661B2 (en) * 2019-04-30 2020-12-15 Micron Technology, Inc. Main word line driver circuit
KR20210110012A (en) * 2020-02-28 2021-09-07 에스케이하이닉스 주식회사 Sub-wordline driver
US11114176B1 (en) 2020-03-06 2021-09-07 Qualcomm Incorporated Systems and methods to provide write termination for one time programmable memory cells
US11817159B2 (en) * 2020-07-16 2023-11-14 Changxin Memory Technologies, Inc. Circuit for detecting anti-fuse memory cell state and memory
US20230061700A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional one time programmable memory

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Also Published As

Publication number Publication date
CN109074834B (en) 2019-11-01
EP3424051B1 (en) 2020-01-08
KR20180101621A (en) 2018-09-12
KR101953876B1 (en) 2019-03-04
ES2776390T3 (en) 2020-07-30
JP6487129B1 (en) 2019-03-20
US9570192B1 (en) 2017-02-14
EP3424051A1 (en) 2019-01-09
CN109074834A (en) 2018-12-21
BR112018067658A2 (en) 2019-01-08
JP2019510331A (en) 2019-04-11
WO2017151302A1 (en) 2017-09-08

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