SG11201808666PA - Charge extraction from ferroelectric memory cell - Google Patents

Charge extraction from ferroelectric memory cell

Info

Publication number
SG11201808666PA
SG11201808666PA SG11201808666PA SG11201808666PA SG11201808666PA SG 11201808666P A SG11201808666P A SG 11201808666PA SG 11201808666P A SG11201808666P A SG 11201808666PA SG 11201808666P A SG11201808666P A SG 11201808666PA SG 11201808666P A SG11201808666P A SG 11201808666PA
Authority
SG
Singapore
Prior art keywords
international
memory cell
capacitor
ferroelectric
digit line
Prior art date
Application number
SG11201808666PA
Inventor
Daniele Vimercati
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of SG11201808666PA publication Critical patent/SG11201808666PA/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225Auxiliary circuits
    • G11C11/2273Reading or sensing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225Auxiliary circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225Auxiliary circuits
    • G11C11/2253Address circuits or decoders
    • G11C11/2255Bit-line or column circuits

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property MD 1101111 0 DOI 0I0 11111 0I0 11111 0 111 0I0 Ell EOM 100 HMI 1111 HMI Organization International Bureau (10) International Publication Number 0 (43) International Publication Date .....0\"\" WO 2017/176467 A3 12 October 2017 (12.10.2017) WIPO I PCT (51) International Patent Classification: (72) Inventor: VIMERCATI, Daniele; 8000 S. Federal Way, G11C 11/22 (2006.01) Boise, ID 83716 (US). (21) International Application Number: (74) Agent: KRAFT, Aaron, J.; Holland & Hart LLP, P.O. Box PCT/US2017/023907 11583, Salt Lake City, UT 84147 (US). (22) International Filing Date: (81) Designated States (unless otherwise indicated, for every 23 March 2017 (23.03.2017) kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, (25) Filing Language: English CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, (26) Publication Language: English DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, (30) Priority Data: KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, 15/090,789 05 April 2016 (05.04.2016) US MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, 8000 S. Federal Way, Boise, ID 83716 (US). SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (54) Title: CHARGE EXTRACTION FROM FERROELECTRIC MEMORY 115-b I05-b i r 415 ci CELL 435 225-a T T 1 DL 125-b 110-b 440 -\.• IV I VL—I = = \ 401 I5 — 7 Ea 111 Reference Component f\") ,- mu 220-a 205-a\ 410 420 425 M ..11 (57) : Methods, systems, IN of a memory cell may be in grounded during memory cell Z stored charge of the ferroelectric IN be achieved by activating a switching --... 7 1 line. The charge of the ferroelectric IN voltage of the sense capacitor Il 0 ei —P, c .' 210-a electronic sensing, limiting capacitor to a reference voltage in order to determine the stored logic state of the memory cell. and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric capacitor capacitor component (e.g., a p-type field-effect communication FIG. 4 with a sense capacitor or avoiding voltage drop across to be extracted and transferred to may be transferred through the L M ) I I 430 the the sense capacitor. Virtually grounding the digit line may transistor) switching through \\"--- 400 a digit line. The digit line may be virtually digit line, and allowing all or substantially all of the that is electronic communication with the digit component. A sense amplifier may compare the O [Continued on next page] WO 2017/176467 A3 MIDEDIM011111111111111111111111111111111111111111 11111 VIII 1110111111111111111 (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: — as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(ii)) — as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3)) (88) Date of publication of the international search report: 16 August 2018 (16.08.2018)
SG11201808666PA 2016-04-05 2017-03-23 Charge extraction from ferroelectric memory cell SG11201808666PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/090,789 US10192606B2 (en) 2016-04-05 2016-04-05 Charge extraction from ferroelectric memory cell using sense capacitors
PCT/US2017/023907 WO2017176467A2 (en) 2016-04-05 2017-03-23 Charge extraction from ferroelectric memory cell

Publications (1)

Publication Number Publication Date
SG11201808666PA true SG11201808666PA (en) 2018-11-29

Family

ID=59961179

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201808666PA SG11201808666PA (en) 2016-04-05 2017-03-23 Charge extraction from ferroelectric memory cell

Country Status (8)

Country Link
US (3) US10192606B2 (en)
EP (1) EP3440674A4 (en)
JP (1) JP6884158B2 (en)
KR (1) KR102282888B1 (en)
CN (1) CN109074836B (en)
SG (1) SG11201808666PA (en)
TW (1) TWI636456B (en)
WO (1) WO2017176467A2 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10083973B1 (en) * 2017-08-09 2018-09-25 Micron Technology, Inc. Apparatuses and methods for reading memory cells
US10762944B2 (en) 2017-12-18 2020-09-01 Micron Technology, Inc. Single plate configuration and memory array operation
US10529410B2 (en) 2017-12-18 2020-01-07 Micron Technology, Inc. Techniques for accessing an array of memory cells to reduce parasitic coupling
US10504576B2 (en) 2017-12-19 2019-12-10 Micron Technology, Inc. Current separation for memory sensing
US10446232B2 (en) 2017-12-19 2019-10-15 Micron Technology, Inc. Charge separation for memory sensing
US10566052B2 (en) * 2017-12-22 2020-02-18 Micron Technology, Inc. Auto-referenced memory cell read techniques
US10431301B2 (en) 2017-12-22 2019-10-01 Micron Technology, Inc. Auto-referenced memory cell read techniques
US10388353B1 (en) 2018-03-16 2019-08-20 Micron Technology, Inc. Canceling memory cell variations by isolating digit lines
US10667621B2 (en) * 2018-04-19 2020-06-02 Micron Technology, Inc. Multi-stage memory sensing
US11127449B2 (en) 2018-04-25 2021-09-21 Micron Technology, Inc. Sensing a memory cell
US10446214B1 (en) 2018-08-13 2019-10-15 Micron Technology, Inc. Sense amplifier with split capacitors
US10726917B1 (en) * 2019-01-23 2020-07-28 Micron Technology, Inc. Techniques for read operations
US11017831B2 (en) * 2019-07-15 2021-05-25 Micron Technology, Inc. Ferroelectric memory cell access
US11289146B2 (en) 2019-08-27 2022-03-29 Micron Technology, Inc. Word line timing management
US11152049B1 (en) 2020-06-08 2021-10-19 Micron Technology, Inc. Differential sensing for a memory device

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5487030A (en) 1994-08-26 1996-01-23 Hughes Aircraft Company Ferroelectric interruptible read memory
US6031754A (en) * 1998-11-02 2000-02-29 Celis Semiconductor Corporation Ferroelectric memory with increased switching voltage
KR100381023B1 (en) 1999-05-13 2003-04-23 주식회사 하이닉스반도체 Ferroelectric random access memory having bitline charge pumping circuit
DE10019481C1 (en) * 2000-04-19 2001-11-29 Infineon Technologies Ag Circuit arrangement for reading a memory cell with a ferroelectric capacitor
TW465071B (en) * 2000-09-21 2001-11-21 Acer Comm & Amp Multimedia Inc Protection loop for horizontal transistor
JP4031904B2 (en) * 2000-10-31 2008-01-09 富士通株式会社 DATA READING CIRCUIT, DATA READING METHOD, AND DATA STORAGE DEVICE
US6577525B2 (en) 2001-08-28 2003-06-10 Micron Technology, Inc. Sensing method and apparatus for resistance memory device
US6459609B1 (en) 2001-12-13 2002-10-01 Ramtron International Corporation Self referencing 1T/1C ferroelectric random access memory
US6704218B2 (en) * 2002-04-02 2004-03-09 Agilent Technologies, Inc. FeRAM with a single access/multiple-comparison operation
US6856535B2 (en) 2003-01-21 2005-02-15 Texas Instruments Incorporated Reference voltage generator for ferroelectric memory
US6819601B2 (en) * 2003-03-07 2004-11-16 Texas Instruments Incorporated Programmable reference for 1T/1C ferroelectric memories
CN100578663C (en) * 2003-04-10 2010-01-06 富士通微电子株式会社 Ferroelectric memory and method for reading data thereof
JP4157528B2 (en) * 2004-03-08 2008-10-01 富士通株式会社 Semiconductor memory
US7227769B2 (en) * 2004-03-08 2007-06-05 Fujitsu Limited Semiconductor memory
JP4638193B2 (en) * 2004-09-24 2011-02-23 パトレネラ キャピタル リミテッド, エルエルシー memory
JP4647313B2 (en) * 2005-01-06 2011-03-09 富士通セミコンダクター株式会社 Semiconductor memory
JP4452631B2 (en) * 2005-01-21 2010-04-21 パトレネラ キャピタル リミテッド, エルエルシー memory
JP4186119B2 (en) * 2005-07-27 2008-11-26 セイコーエプソン株式会社 Ferroelectric memory device
JP4305960B2 (en) * 2005-12-28 2009-07-29 セイコーエプソン株式会社 Ferroelectric memory device
JP4996177B2 (en) * 2006-08-30 2012-08-08 富士通セミコンダクター株式会社 Semiconductor memory device and data reading method
JP2008305469A (en) * 2007-06-06 2008-12-18 Toshiba Corp Semiconductor memory
WO2009034603A1 (en) * 2007-09-14 2009-03-19 Fujitsu Microelectronics Limited Semiconductor memory
JP2009301658A (en) 2008-06-13 2009-12-24 Seiko Epson Corp Ferroelectric memory device, method for driving ferroelectric memory device and electronic equipment
US8531862B2 (en) * 2008-10-27 2013-09-10 Nxp B.V. Generating and exploiting an asymmetric capacitance hysteresis of ferroelectric MIM capacitors
US8130580B1 (en) * 2010-09-03 2012-03-06 Atmel Corporation Low power sense amplifier for reading memory
JP5156069B2 (en) 2010-09-17 2013-03-06 株式会社東芝 Ferroelectric memory
US9786346B2 (en) * 2015-05-20 2017-10-10 Micron Technology, Inc. Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory
US9552864B1 (en) * 2016-03-11 2017-01-24 Micron Technology, Inc. Offset compensation for ferroelectric memory cell sensing

Also Published As

Publication number Publication date
JP2019518300A (en) 2019-06-27
US20190096466A1 (en) 2019-03-28
KR20180121697A (en) 2018-11-07
KR102282888B1 (en) 2021-07-29
US10192606B2 (en) 2019-01-29
CN109074836A (en) 2018-12-21
EP3440674A2 (en) 2019-02-13
US11087816B2 (en) 2021-08-10
CN109074836B (en) 2022-08-16
TW201802806A (en) 2018-01-16
TWI636456B (en) 2018-09-21
US20190096467A1 (en) 2019-03-28
WO2017176467A3 (en) 2018-08-16
US20170287541A1 (en) 2017-10-05
US11322191B2 (en) 2022-05-03
EP3440674A4 (en) 2019-12-11
JP6884158B2 (en) 2021-06-09
WO2017176467A2 (en) 2017-10-12

Similar Documents

Publication Publication Date Title
SG11201808666PA (en) Charge extraction from ferroelectric memory cell
SG11201807496XA (en) Offset compensation for ferroelectric memory cell sensing
SG11201810128WA (en) Charge mirror-based sensing for ferroelectric memory
SG11201900816TA (en) A hybrid memory device
SG11201810132WA (en) Ferroelectric memory cell recovery
SG11201811065SA (en) Memory cell imprint avoidance
SG11201811061UA (en) Writing to cross-point non-volatile memory
SG11201811063QA (en) Array data bit inversion
SG11201906878SA (en) Multiple gate-induced drain leakage current generator
SG11201901213YA (en) Storing memory array operational information in nonvolatile subarrays
SG11201902707WA (en) Apparatuses including memory cells and methods of operation of same
SG11201907679TA (en) Business verification method and apparatus
SG11201900341WA (en) Apparatuses including multi-level memory cells and methods of operation of same
SG11201907437UA (en) Efficient utilization of memory die area
SG11201805300QA (en) Heterocyclic compounds as immunomodulators
SG11201807962QA (en) Thermal insulation for three-dimensional memory arrays
SG11201811465WA (en) Semiconductor package and method of forming the same
SG11201901210UA (en) Ferroelectric memory cells
SG11201710421WA (en) Vending machine
SG11201807164XA (en) Circuit arrangement, method of forming and operating the same
SG11201901168UA (en) Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory
SG11201908050TA (en) Multiple plate line architecture for multideck memory array
SG11201805648PA (en) Crypto multiple security asset creation and redemption platform
SG11201901211XA (en) Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory
SG11201900375YA (en) Link error correction in memory system