SG11201900375YA - Link error correction in memory system - Google Patents
Link error correction in memory systemInfo
- Publication number
- SG11201900375YA SG11201900375YA SG11201900375YA SG11201900375YA SG11201900375YA SG 11201900375Y A SG11201900375Y A SG 11201900375YA SG 11201900375Y A SG11201900375Y A SG 11201900375YA SG 11201900375Y A SG11201900375Y A SG 11201900375YA SG 11201900375Y A SG11201900375Y A SG 11201900375YA
- Authority
- SG
- Singapore
- Prior art keywords
- international
- memory
- link error
- error correction
- pct
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/31—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining coding for error detection or correction and efficient use of the spectrum
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Human Computer Interaction (AREA)
- Computer Security & Cryptography (AREA)
- Probability & Statistics with Applications (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Correction Of Errors (AREA)
- Memory System (AREA)
- Error Detection And Correction (AREA)
Abstract
INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property 1 MI 10H 0 ill 010 la 01 110 1 0 0111E011H H 0111 0011110 1111 OEN Organization International Bureau (10) International Publication Number (43) International Publication Date .....0\"\"\"1 WO 2018/038813 Al 01 March 2018 (01.03.2018) W I PO I PCT (51) International Patent Classification: (72) Inventor: SUH, Jungwon; QUALCOMM INCORPO- GO6F 11/10 (2006.01) RATED, 5775 Morehouse Drive, San Diego, California (21) International Application Number: 92121-1714 (US). PCT/US2017/041129 (74) Agent: OLDS, Mark E. et al.; Muncy, Geissler, Olds & (22) International Filing Date: Lowe, P.C., 4000 Legato Road, Suite 310, Fairfax, Virginia 07 July 2017 (07.07.2017) 22033 (US). (25) Filing Language: English (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, (26) Publication Language: English AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, (30) Priority Data: CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, 62/380,104 26 August 2016 (26.08.2016) US DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, 15/643,455 06 July 2017 (06.07.2017) US HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, (71) Applicant: QUALCOMM INCORPORATED [US/US]; MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, ATTN: International IP Administration, 5775 Morehouse OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, Drive, San Diego, California 92121-1714 (US). SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. = (54) Title: LINK ERROR CORRECTION IN MEMORY SYSTEM 400 490 , 460 _ .------N DQ[0 7] w — DM ► I = / DATA CK 432 READ STROBE CK ► 464 = 4 = 434 462 = COMMAND & ADDRESS CA[0 n] / ► = ► r. 6. = _ CA CK = — _ = — 420 430 410 450 —,,....._ 470 Il FIG. 4 M 1-1 of (57) : Conventional link error correction techniques in memory subsystems include either widening the I/O width or increasing Op the burst length. However, both techniques have drawbacks. In one or more aspects, it is proposed to incorporate link error correction C in both the host and the memory devices to address the drawbacks associated with the conventional techniques. The proposed memory ---, subsystem is advantageous in that the interface architecture of conventional memory systems can be maintained. Also, the link error 0 1-1 0 correction is capability is provided with the proposed memory subsystem without increasing the I/O width and without increasing the cz burst length. N C [Continued on next page] WO 2018/038813 Al MIDEDIMOMOIDEIREIHNIMIOMBHOMMOVOIS (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3))
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201662380104P | 2016-08-26 | 2016-08-26 | |
| US15/643,455 US10331517B2 (en) | 2016-08-26 | 2017-07-06 | Link error correction in memory system |
| PCT/US2017/041129 WO2018038813A1 (en) | 2016-08-26 | 2017-07-07 | Link error correction in memory system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11201900375YA true SG11201900375YA (en) | 2019-03-28 |
Family
ID=61242685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11201900375YA SG11201900375YA (en) | 2016-08-26 | 2017-07-07 | Link error correction in memory system |
Country Status (20)
| Country | Link |
|---|---|
| US (1) | US10331517B2 (en) |
| EP (1) | EP3479241B1 (en) |
| JP (1) | JP6630869B2 (en) |
| KR (1) | KR102045712B1 (en) |
| CN (1) | CN109643257B (en) |
| AU (2) | AU2017315303B2 (en) |
| BR (1) | BR112019003473A2 (en) |
| CA (1) | CA3032278C (en) |
| CO (1) | CO2019001630A2 (en) |
| ES (1) | ES2829331T3 (en) |
| IL (1) | IL264303B (en) |
| MX (1) | MX2019002194A (en) |
| MY (1) | MY201067A (en) |
| PH (1) | PH12019500160A1 (en) |
| RU (1) | RU2710977C1 (en) |
| SA (1) | SA519401035B1 (en) |
| SG (1) | SG11201900375YA (en) |
| TW (1) | TWI684102B (en) |
| WO (1) | WO2018038813A1 (en) |
| ZA (1) | ZA201901194B (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107039086B (en) * | 2017-05-17 | 2024-08-30 | 西安紫光国芯半导体有限公司 | Memory with error correction function compatible with different data lengths and error correction method |
| US10387242B2 (en) | 2017-08-21 | 2019-08-20 | Qualcomm Incorporated | Dynamic link error protection in memory systems |
| US10725912B2 (en) * | 2018-12-19 | 2020-07-28 | Micron Technology, Inc. | Power loss protection in memory sub-systems |
| US11537464B2 (en) * | 2019-06-14 | 2022-12-27 | Micron Technology, Inc. | Host-based error correction |
| US11372717B2 (en) * | 2019-08-30 | 2022-06-28 | Qualcomm Incorporated | Memory with system ECC |
| CN110750406B (en) * | 2019-10-29 | 2023-10-31 | 湖南国科微电子股份有限公司 | Detection method and device and SOC chip |
| US11493949B2 (en) * | 2020-03-27 | 2022-11-08 | Qualcomm Incorporated | Clocking scheme to receive data |
| US11728003B2 (en) | 2020-05-12 | 2023-08-15 | Qualcomm Incorporated | System and memory with configurable error-correction code (ECC) data protection and related methods |
| US11157359B2 (en) * | 2020-09-24 | 2021-10-26 | Intel Corporation | Techniques to implement a hybrid error correction code scheme |
| KR20230021409A (en) | 2021-08-05 | 2023-02-14 | 에스케이하이닉스 주식회사 | Semiconductor system for performing training operation |
| US11687273B2 (en) * | 2021-09-29 | 2023-06-27 | Micron Technology, Inc. | Memory controller for managing data and error information |
| CN114006819A (en) * | 2021-11-03 | 2022-02-01 | 北京天融信网络安全技术有限公司 | Detection strategy generation and device, and data transmission method and device |
| US12073901B2 (en) * | 2021-11-30 | 2024-08-27 | Qualcomm Incorporated | Hybrid memory system with increased bandwidth |
| US20240126438A1 (en) * | 2022-10-18 | 2024-04-18 | Qualcomm Incorporated | Metadata registers for a memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2154897C2 (en) * | 1995-04-03 | 2000-08-20 | Матсусита Электрик Индастриал Ко., Лтд. | Data transmission system, data recording and reproducing device, and record medium using data representation format based on error-correction code |
| US7032056B2 (en) * | 2003-05-08 | 2006-04-18 | International Business Machines Corporation | Encoding of message onto strobe signals |
| KR100978268B1 (en) * | 2004-07-15 | 2010-08-26 | 엘에스산전 주식회사 | Dual data copy board for high performance in distributed control system |
| KR100755371B1 (en) | 2005-05-03 | 2007-09-04 | 삼성전자주식회사 | Semiconductor memory device and data output strobe signal generating method thereof |
| CN101060015A (en) * | 2007-05-23 | 2007-10-24 | 北京芯技佳易微电子科技有限公司 | A multi-bit flash memory and its error detection and remedy method |
| EP2223301A4 (en) | 2007-12-21 | 2012-04-04 | Mosaid Technologies Inc | Non-volatile semiconductor memory device with power saving feature |
| US8255783B2 (en) | 2008-04-23 | 2012-08-28 | International Business Machines Corporation | Apparatus, system and method for providing error protection for data-masking bits |
| US8341498B2 (en) * | 2010-10-01 | 2012-12-25 | Sandisk Technologies Inc. | System and method of data encoding |
| US8707133B2 (en) * | 2011-12-05 | 2014-04-22 | Lsi Corporation | Method and apparatus to reduce a quantity of error detection/correction bits in memory coupled to a data-protected processor port |
| CN102546755A (en) * | 2011-12-12 | 2012-07-04 | 华中科技大学 | Data storage method of cloud storage system |
| US8990670B2 (en) * | 2012-09-28 | 2015-03-24 | Intel Corporation | Endurance aware error-correcting code (ECC) protection for non-volatile memories |
| US9064606B2 (en) | 2012-12-20 | 2015-06-23 | Advanced Micro Devices, Inc. | Memory interface supporting both ECC and per-byte data masking |
| US9164834B2 (en) * | 2013-05-06 | 2015-10-20 | Samsung Electronics Co., Ltd. | Semiconductor memory devices, memory systems including the same and method of writing data in the same |
| CN105468292B (en) * | 2014-09-05 | 2019-04-23 | 群联电子股份有限公司 | Data access method, memorizer memory devices and memorizer control circuit unit |
| US9558066B2 (en) * | 2014-09-26 | 2017-01-31 | Intel Corporation | Exchanging ECC metadata between memory and host system |
| KR102438552B1 (en) * | 2015-02-04 | 2022-09-01 | 에스케이하이닉스 주식회사 | Memory system and operation method for the same |
| US9965352B2 (en) * | 2015-11-20 | 2018-05-08 | Qualcomm Incorporated | Separate link and array error correction in a memory system |
| US20180059976A1 (en) * | 2016-08-26 | 2018-03-01 | Sandisk Technologies Llc | Storage System with Integrated Components and Method for Use Therewith |
-
2017
- 2017-07-06 US US15/643,455 patent/US10331517B2/en active Active
- 2017-07-07 ES ES17740597T patent/ES2829331T3/en active Active
- 2017-07-07 KR KR1020197005234A patent/KR102045712B1/en active IP Right Grant
- 2017-07-07 SG SG11201900375YA patent/SG11201900375YA/en unknown
- 2017-07-07 CA CA3032278A patent/CA3032278C/en active Active
- 2017-07-07 AU AU2017315303A patent/AU2017315303B2/en active Active
- 2017-07-07 JP JP2019510446A patent/JP6630869B2/en active Active
- 2017-07-07 MX MX2019002194A patent/MX2019002194A/en unknown
- 2017-07-07 CN CN201780051324.XA patent/CN109643257B/en active Active
- 2017-07-07 BR BR112019003473-0A patent/BR112019003473A2/en unknown
- 2017-07-07 MY MYPI2019000091A patent/MY201067A/en unknown
- 2017-07-07 RU RU2019104878A patent/RU2710977C1/en active
- 2017-07-07 EP EP17740597.4A patent/EP3479241B1/en active Active
- 2017-07-07 WO PCT/US2017/041129 patent/WO2018038813A1/en active Search and Examination
- 2017-07-28 TW TW106125466A patent/TWI684102B/en active
-
2019
- 2019-01-17 IL IL264303A patent/IL264303B/en active IP Right Grant
- 2019-01-22 PH PH12019500160A patent/PH12019500160A1/en unknown
- 2019-02-05 SA SA519401035A patent/SA519401035B1/en unknown
- 2019-02-22 CO CONC2019/0001630A patent/CO2019001630A2/en unknown
- 2019-02-25 ZA ZA2019/01194A patent/ZA201901194B/en unknown
- 2019-08-30 AU AU2019222960A patent/AU2019222960B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109643257B (en) | 2020-07-03 |
| AU2017315303B2 (en) | 2020-06-18 |
| US20180060171A1 (en) | 2018-03-01 |
| ZA201901194B (en) | 2020-12-23 |
| WO2018038813A1 (en) | 2018-03-01 |
| SA519401035B1 (en) | 2021-11-06 |
| PH12019500160A1 (en) | 2019-11-11 |
| CO2019001630A2 (en) | 2019-05-10 |
| AU2017315303A1 (en) | 2019-02-07 |
| AU2019222960A1 (en) | 2019-09-26 |
| MY201067A (en) | 2024-02-01 |
| MX2019002194A (en) | 2019-06-24 |
| TWI684102B (en) | 2020-02-01 |
| CA3032278A1 (en) | 2018-03-01 |
| TW201810056A (en) | 2018-03-16 |
| CN109643257A (en) | 2019-04-16 |
| EP3479241A1 (en) | 2019-05-08 |
| CA3032278C (en) | 2021-01-12 |
| IL264303B (en) | 2019-08-29 |
| KR20190043540A (en) | 2019-04-26 |
| NZ750205A (en) | 2020-10-30 |
| EP3479241B1 (en) | 2020-08-19 |
| JP2019525356A (en) | 2019-09-05 |
| KR102045712B1 (en) | 2019-11-15 |
| US10331517B2 (en) | 2019-06-25 |
| ES2829331T3 (en) | 2021-05-31 |
| JP6630869B2 (en) | 2020-01-15 |
| RU2710977C1 (en) | 2020-01-14 |
| IL264303A (en) | 2019-02-28 |
| AU2019222960B2 (en) | 2020-10-15 |
| BR112019003473A2 (en) | 2019-05-21 |
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