SG11201811065SA - Memory cell imprint avoidance - Google Patents

Memory cell imprint avoidance

Info

Publication number
SG11201811065SA
SG11201811065SA SG11201811065SA SG11201811065SA SG11201811065SA SG 11201811065S A SG11201811065S A SG 11201811065SA SG 11201811065S A SG11201811065S A SG 11201811065SA SG 11201811065S A SG11201811065S A SG 11201811065SA SG 11201811065S A SG11201811065S A SG 11201811065SA
Authority
SG
Singapore
Prior art keywords
cell
international
boise
idaho
logic state
Prior art date
Application number
SG11201811065SA
Inventor
Alessandro Calderoni
Durai Vishak Nirmal Ramaswamy
Kirk Prall
Ferdinando Bedeschi
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of SG11201811065SA publication Critical patent/SG11201811065SA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2275—Writing or programming circuits or methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Heterocyclic Carbon Compounds Containing A Hetero Ring Having Oxygen Or Sulfur (AREA)
  • Peptides Or Proteins (AREA)

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property 1111111011110111010101111101011111001111111111111101H11111111111111111111110111111 Organization International Bureau (10) International Publication Number (43) International Publication Date ......0\"\" WO 2017/222786 Al 28 December 2017 (28.12.2017) WIP0 I PCT (51) International Patent Classification: DESCHI, Ferdinando; 8000 South Federal Way, Boise, Gl1C 11/22 (2006.01) Idaho 83716-9632 (US). (21) International Application Number: (74) Agent: HARRIS, Philip W.; Holland & Hart LLP, P.O. PCT/US2017/035758 Box 11583, Salt Lake City, Utah 84147 (US). (22) International Filing Date: (81) Designated States (unless otherwise indicated, for every 02 June 2017 (02.06.2017) kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, (25) Filing Language: English CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, (26) Publication Language: English DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, (30) Priority Data: KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, 15/188,886 21 June 2016 (21.06.2016) US MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, 8000 South Federal Way, Boise, Idaho 83716-9632 (US). SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (72) Inventors: CALDERONI, Alessandro; 8000 South Federal Way, Boise, Idaho 83716-9632 (US). RA- (84) Designated States (unless otherwise indicated, for every MASWAMY, Durai Vishak Nirmal; 8000 South Federal kind of regional protection available): ARIPO (BW, GH, Way, Boise, Idaho 83716-9632 (US). PRALL, Kirk; 8000 GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, South Federal Way, Boise, Idaho 83716-9632 (US). BE- UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, (54) Title: MEMORY CELL IMPRINT AVOIDANCE 430 Non-Volatile Latch Indicator,' 435 , . >i FCC 3 ,i Component f 440 115-b \ 405 (—I J-225-a DL, tm 105-b ‘._ ssvt., l a 415-a )420- . , ......... 420-b l a 415-b Memory _.-b_ 110-bT Cell 425-a{ 425-a{ } 4 b pt N210-a > a \-- 1 125-b 4- 1 410 ,-1 FIG. 4 \----- 400 .4 (57) : Methods, systems, and devices for operating a ferroelectric memory cell or cells are described, A cell may be written GO N with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has ei stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently ei ----. stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based IN ,_ 1 on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period. 0 ei C [Continued on next page] WO 2017/222786 Al IMEDIMOMMIDIRMEMODIOHOHOMEINOME#011# TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: — as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(H)) — as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3))
SG11201811065SA 2016-06-21 2017-06-02 Memory cell imprint avoidance SG11201811065SA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/188,886 US9721639B1 (en) 2016-06-21 2016-06-21 Memory cell imprint avoidance
PCT/US2017/035758 WO2017222786A1 (en) 2016-06-21 2017-06-02 Memory cell imprint avoidance

Publications (1)

Publication Number Publication Date
SG11201811065SA true SG11201811065SA (en) 2019-01-30

Family

ID=59382659

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201811065SA SG11201811065SA (en) 2016-06-21 2017-06-02 Memory cell imprint avoidance

Country Status (8)

Country Link
US (5) US9721639B1 (en)
EP (2) EP3926629A1 (en)
JP (2) JP7118012B2 (en)
KR (2) KR102220990B1 (en)
CN (2) CN109313921B (en)
SG (1) SG11201811065SA (en)
TW (2) TWI663596B (en)
WO (1) WO2017222786A1 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9697913B1 (en) * 2016-06-10 2017-07-04 Micron Technology, Inc. Ferroelectric memory cell recovery
US9721639B1 (en) 2016-06-21 2017-08-01 Micron Technology, Inc. Memory cell imprint avoidance
US10388351B2 (en) 2017-08-30 2019-08-20 Micron Technology, Inc. Wear leveling for random access and ferroelectric memory
US10446502B2 (en) * 2017-08-30 2019-10-15 Micron, Technology, Inc. Apparatuses and methods for shielded memory architecture
US10431281B1 (en) * 2018-08-17 2019-10-01 Micron Technology, Inc. Access schemes for section-based data protection in a memory device
US10991411B2 (en) 2018-08-17 2021-04-27 Micron Technology, Inc. Method and apparatuses for performing a voltage adjustment operation on a section of memory cells based on a quantity of access operations
US11456033B2 (en) 2018-09-12 2022-09-27 Micron Technology, Inc. Dedicated commands for memory operations
US10622065B2 (en) * 2018-09-12 2020-04-14 Micron Technology, Inc. Dedicated commands for memory operations
US20200119838A1 (en) * 2018-10-12 2020-04-16 Micron Technology, Inc. Adapting channel current
US10839935B2 (en) * 2019-02-05 2020-11-17 International Business Machines Corporation Dynamic redundancy for memory
US10692557B1 (en) * 2019-04-11 2020-06-23 Micron Technology, Inc. Reference voltage management
US10998080B2 (en) * 2019-09-24 2021-05-04 Micron Technology, Inc. Imprint recovery for memory cells
US20210089385A1 (en) * 2019-09-24 2021-03-25 Micron Technology, Inc. Imprint recovery management for memory systems
US11094394B2 (en) * 2019-09-24 2021-08-17 Micron Technology, Inc. Imprint management for memory
EP4082015A4 (en) * 2019-12-23 2023-07-19 Micron Technology, Inc. Counter-based read in memory device
TWI766462B (en) 2019-12-23 2022-06-01 美商美光科技公司 Counter-based read in memory device
US11521979B2 (en) * 2020-12-04 2022-12-06 Micron Technology, Inc. Power gating in a memory device

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3191550B2 (en) * 1994-02-15 2001-07-23 松下電器産業株式会社 Semiconductor memory device
US5525528A (en) * 1994-02-23 1996-06-11 Ramtron International Corporation Ferroelectric capacitor renewal method
TW378323B (en) * 1994-09-22 2000-01-01 Matsushita Electric Ind Co Ltd Ferroelectric memory device
JP3919312B2 (en) * 1996-12-27 2007-05-23 ローム株式会社 Ferroelectric memory device
US6246603B1 (en) * 2000-06-30 2001-06-12 Stmicroelectronics, Inc. Circuit and method for substantially preventing imprint effects in a ferroelectric memory device
JP2002184172A (en) 2000-10-04 2002-06-28 Rohm Co Ltd Data storage device
JP2002124100A (en) * 2000-10-16 2002-04-26 Matsushita Electric Ind Co Ltd Ferroelectric memory device
JP2002343078A (en) 2001-05-21 2002-11-29 Matsushita Electric Ind Co Ltd Ferroelectric memory device
US6522570B1 (en) * 2001-12-13 2003-02-18 Micron Technology, Inc. System and method for inhibiting imprinting of capacitor structures of a memory
US6650562B2 (en) * 2002-01-23 2003-11-18 Hewlett-Packard Development Company, L.P. System and method for determining the logic state of a memory cell in a magnetic tunnel junction memory device
US6809949B2 (en) * 2002-05-06 2004-10-26 Symetrix Corporation Ferroelectric memory
US6590798B1 (en) * 2002-05-08 2003-07-08 Texas Instruments Incorporated Apparatus and methods for imprint reduction for ferroelectric memory cell
KR100448921B1 (en) * 2002-05-21 2004-09-16 삼성전자주식회사 High-speed ferroelectric memory device and write methdo thereof
KR100496858B1 (en) * 2002-08-02 2005-06-22 삼성전자주식회사 Magnetic random access memory for flowing constant(I(H)+I(L))/2) current to reference cell without regard of bitline clamp voltage
US20040190322A1 (en) * 2003-03-28 2004-09-30 Baumann Robert C Circuit and method for reducing the effects of memory imprinting
US6954373B2 (en) * 2003-06-27 2005-10-11 Hewlett-Packard Development Company, L.P. Apparatus and method for determining the logic state of a magnetic tunnel junction memory device
JP4270994B2 (en) * 2003-09-29 2009-06-03 株式会社東芝 Nonvolatile semiconductor memory device
US6950328B2 (en) * 2003-12-11 2005-09-27 Infineon Technologies Ag Imprint suppression circuit scheme
NO322040B1 (en) * 2004-04-15 2006-08-07 Thin Film Electronics Asa Bimodal operation of ferroelectric and electret memory cells and devices
JP4117683B2 (en) * 2004-07-20 2008-07-16 セイコーエプソン株式会社 Ferroelectric memory device and driving method thereof
KR100665841B1 (en) * 2004-12-14 2007-01-09 삼성전자주식회사 Circuits for driving FRAM
KR100665844B1 (en) * 2005-01-04 2007-01-09 삼성전자주식회사 Ferroelectric Random Access Memory device and method for driving the same
WO2006073308A1 (en) 2005-01-04 2006-07-13 Thin Film Electronics Asa Method for operating a passive matrix-addressable ferroelectric or electret memory device
KR100702840B1 (en) * 2005-07-13 2007-04-03 삼성전자주식회사 Ferroelectric Random Access Memory device and method for control writing sections therefore
JP2008071440A (en) 2006-09-14 2008-03-27 Matsushita Electric Ind Co Ltd Ferroelectric memory device and its control method
JP2008135136A (en) 2006-11-29 2008-06-12 Fujitsu Ltd Ferroelectric memory and operation method of ferroelectric memory
US7729156B2 (en) * 2007-12-26 2010-06-01 Texas Instruments Incorporated Cycling to mitigate imprint in ferroelectric memories
US8495438B2 (en) * 2007-12-28 2013-07-23 Texas Instruments Incorporated Technique for memory imprint reliability improvement
US7983089B2 (en) * 2008-06-06 2011-07-19 Spansion Llc Sense amplifier with capacitance-coupled differential sense amplifier
KR101497545B1 (en) * 2008-09-12 2015-03-03 삼성전자주식회사 Method and apparatus for detecting free page and error correction code decoding method and apparatus using the same
JP5185098B2 (en) * 2008-12-22 2013-04-17 株式会社東芝 Ferroelectric memory
US9123429B2 (en) * 2009-07-27 2015-09-01 Sidense Corp. Redundancy system for non-volatile memory
EP2357783B1 (en) * 2010-02-16 2013-06-05 STMicroelectronics (Rousset) SAS Method for detecting potentially suspicious operation of an electronic device and corresponding electronic device
KR20140113657A (en) * 2012-01-16 2014-09-24 소니 주식회사 Storage control device, storage device, information processing system, and processing methods in same
US8756558B2 (en) * 2012-03-30 2014-06-17 Texas Instruments Incorporated FRAM compiler and layout
US9001575B2 (en) 2012-03-30 2015-04-07 Micron Technology, Inc. Encoding program bits to decouple adjacent wordlines in a memory device
US9105314B2 (en) 2012-04-27 2015-08-11 Micron Technology, Inc. Program-disturb decoupling for adjacent wordlines of a memory device
US8910000B2 (en) 2012-05-17 2014-12-09 Micron Technology, Inc. Program-disturb management for phase change memory
US8971105B2 (en) 2013-03-13 2015-03-03 Micron Technology, Inc. Methods and apparatuses for controlling memory write sequences
JP6136767B2 (en) 2013-08-29 2017-05-31 富士通セミコンダクター株式会社 Semiconductor memory device and writing method thereof
US9361965B2 (en) * 2013-10-11 2016-06-07 Texas Instruments Incorporated Circuit and method for imprint reduction in FRAM memories
KR102140784B1 (en) * 2013-12-03 2020-08-03 삼성전자주식회사 Method for writing data of nonvolatile memory device
US9275730B2 (en) * 2014-04-11 2016-03-01 Micron Technology, Inc. Apparatuses and methods of reading memory cells based on response to a test pulse
JP6444668B2 (en) * 2014-09-10 2018-12-26 ローム株式会社 Data holding control circuit, data writing method, data reading method, ferroelectric memory unit characteristic test method, semiconductor chip
US9721639B1 (en) * 2016-06-21 2017-08-01 Micron Technology, Inc. Memory cell imprint avoidance

Also Published As

Publication number Publication date
CN109313921A (en) 2019-02-05
EP3472838A1 (en) 2019-04-24
TW201907398A (en) 2019-02-16
KR20190017999A (en) 2019-02-20
EP3926629A1 (en) 2021-12-22
WO2017222786A1 (en) 2017-12-28
US10475500B2 (en) 2019-11-12
JP2021166114A (en) 2021-10-14
US11501817B2 (en) 2022-11-15
US10083732B2 (en) 2018-09-25
KR102220990B1 (en) 2021-03-02
TW201802807A (en) 2018-01-16
JP7118012B2 (en) 2022-08-15
US20180366176A1 (en) 2018-12-20
JP2019525375A (en) 2019-09-05
US9721639B1 (en) 2017-08-01
US20210280231A1 (en) 2021-09-09
EP3472838A4 (en) 2020-03-04
TWI632548B (en) 2018-08-11
CN109313921B (en) 2021-04-02
CN112967742A (en) 2021-06-15
TWI663596B (en) 2019-06-21
US10978128B2 (en) 2021-04-13
EP3472838B1 (en) 2021-08-04
US20170365323A1 (en) 2017-12-21
KR102349353B1 (en) 2022-01-10
KR20210022158A (en) 2021-03-02
US20200090728A1 (en) 2020-03-19

Similar Documents

Publication Publication Date Title
SG11201811065SA (en) Memory cell imprint avoidance
SG11201811063QA (en) Array data bit inversion
SG11201810132WA (en) Ferroelectric memory cell recovery
SG11201811095UA (en) Multi-level storage in ferroelectric memory
SG11201807496XA (en) Offset compensation for ferroelectric memory cell sensing
SG11201902707WA (en) Apparatuses including memory cells and methods of operation of same
SG11201900341WA (en) Apparatuses including multi-level memory cells and methods of operation of same
SG11201806781SA (en) Registry and automated management method for blockchain-enforced smart contracts
SG11201810128WA (en) Charge mirror-based sensing for ferroelectric memory
SG11201811061UA (en) Writing to cross-point non-volatile memory
SG11201808666PA (en) Charge extraction from ferroelectric memory cell
SG11201901213YA (en) Storing memory array operational information in nonvolatile subarrays
SG11201804807VA (en) Computer architecture and method for modifying data intake parameters based on a predictive model
SG11201900116RA (en) Communication flow for verification and identification check
SG11201908050TA (en) Multiple plate line architecture for multideck memory array
SG11201809795VA (en) Memory access techniques in memory devices with multiple partitions
SG11201901168UA (en) Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory
SG11201909850PA (en) Programming enhancement in self-selecting memory
SG11201805648PA (en) Crypto multiple security asset creation and redemption platform
SG11201806413WA (en) Cell-based reference voltage generation
SG11201906878SA (en) Multiple gate-induced drain leakage current generator
SG11201811343SA (en) System and methods for detecting online fraud
SG11201805020QA (en) Synthesis of inorganic sio2 microcapsules containing phase change materials and applications therein
SG11201901211XA (en) Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory
SG11201807493WA (en) Ground reference scheme for a memory cell