JP2002124100A - Ferroelectric memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a ferroelectric memory device which can detect surely occurrence of imprint of a ferroelectric memory cell using more simple and smaller circuit than a soya tower circuit. SOLUTION: This device is provided with a data store section 3 and a comparing circuit section 4, data is read out from a ferroelectric memory cell in a ferroelectric memory cell section 8 and after it is held in the data store section 3, data being inverse to data held in the data store section 3 is written in the ferroelectric memory cell, after that, occurrence of imprint of the ferroelectric memory cell can be detected surely by comparing data read out from the ferroelectric memory cell with data stored in the data store section 3. Thereby, imprint relaxation operation can be performed as necessary, a ferroelectric memory device having a long lifetime can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device using a ferroelectric.

[0002]

2. Description of the Related Art A ferroelectric memory using a ferroelectric is known as a nonvolatile semiconductor memory. FIG. 10 shows 2Tr-2C (2 Transistor-2) using a conventional ferroelectric material.
2 shows a part of a circuit showing an example of a (capacitance) type semiconductor memory device. In FIG. 10, reference numerals 19 and 20 denote ferroelectrics used as memory cells, and reference numerals 21 and 22 denote access transistors corresponding to the ferroelectrics 19 and 20. 23 is a word line, 24 is a cell plate, 25 and 26
Is a bit line, and 27 is a differential amplifier for amplifying the potential difference between the bit lines 25 and 26. Read and write operations of the ferroelectric memory device in this circuit will be briefly described.

As a read operation, first, a word line 23
Are turned on, the access transistors 21 and 22 are turned on. Next, by raising the potential of the cell plate 24, different potentials appear on the bit lines 25 and 26 depending on whether or not the spontaneous polarization directions of the ferroelectrics 19 and 20 are reversed. At this time, bit lines 25 and 2
The potential appearing in 6 will be explained by a diagrammatic solution described later. The potential difference appearing on the bit lines 25 and 26 is amplified by the activated differential amplifier 27, and the potential of the bit lines 25 and 26 is set to the power supply voltage (VDD) or the ground. Based on the set potential of the bit line 25 or 26, it is possible to determine the ferroelectric substance, that is, the data held in the memory cell. On the other hand, since the data of the memory cell has been destroyed by reading, the operation of rewriting is started subsequently. By keeping the differential amplifier 27 activated for a certain period of time and then lowering the potential of the cell plate 24, data is re-stored in the memory cell due to the potential difference between the bit line 25 or 26 and the cell plate 24. Is written.

[0006] The write operation is realized by externally determining the potential of the bit line in the above-described rewrite operation. That is, a potential corresponding to the write data is externally applied to the bit line 25 or 26, and the cell plate 24
By raising and then lowering the potential, the data "H"
(High) and "L" (low) are written.

By performing the above operation, the ferroelectric is actually used as a nonvolatile semiconductor memory device. Since this ferroelectric memory is a nonvolatile memory,
Data must be retained for a long period of time and data must be rewritten smoothly thereafter, but this retention characteristic is adversely affected by the shape change characteristic of a hysteresis curve generally known as "imprint".

This imprint means that when high-temperature storage is performed with arbitrary binary data written, the applied voltage and the amount of polarization in the ferroelectric material change, and the data written before storage is changed. This is a phenomenon that makes it difficult to write the reverse data. Further, even if the same data is continuously written a plurality of times, a similar change in the shape of the hysteresis curve occurs, which has the same effect on the holding characteristics as described above. The shape change of the hysteresis curve due to the imprint will be described below.

FIG. 11 is a graph showing the hysteresis characteristics of a normal ferroelectric substance. The abscissa represents the voltage applied to the ferroelectric, and the ordinate represents the amount of polarization in the ferroelectric. The two different polarization states 28 and 29 represent the amount of polarization in the ferroelectric when the applied voltage is zero. The binary data is stored in the ferroelectric capacitor by setting the amount of polarization in either of the two polarization states 28 or 29. Regarding the setting of the polarization state, setting from the polarization state 28 to 29 applies the polarization reversal voltage 33 from outside the ferroelectric, and setting from the polarization state 29 to 28 applies the applied voltage 3
4 can be realized by applying it externally.
The applied voltage 30 is a voltage applied to the ferroelectric at the time of reading,
In other words, it indicates the potential of the cell plate 24 at the time of reading, and when the voltage 30 is applied to the ferroelectric, the bit line 25
And 26 generate a potential difference 31. The slope of the straight line 32 used in this graphical solution is determined by the ratio of the parasitic capacitance of the bit line 25 or 26 to the capacitance when the ferroelectric is recognized as a capacitor. The potential difference 31 is amplified by the differential amplifier 27, and the data written in the memory cell can be determined based on the amplified potential appearing on the bit line 25 or 26.

In FIG. 11, the polarization amount is changed to the polarization state 2
After setting the ferroelectric memory device to 8 or 29, if the ferroelectric memory device is stored at a high temperature or the same data is continuously written, the above-described imprint occurs, and the hysteresis curve shifts in a direction depending on the polarization state. . As an example, FIG. 12 shows a change in the hysteresis curve when the polarization state is 28. The hysteresis curve 35 is a curve before imprint has occurred, and the hysteresis curve 36 is a curve after imprint has occurred. As shown in FIG.
Since the hysteresis curve is shifted to the left as a whole due to the occurrence of the imprint, the polarization inversion voltage 38 necessary for the polarization inversion after the imprint has occurred is higher than the polarization inversion voltage 33 before the imprint has occurred. You can easily understand. In other words, it can be said that the voltage required for data inversion in the ferroelectric memory has increased, and it has become difficult to write reverse data. Further, when the polarization inversion voltage 38 increases according to the degree of progress of imprint, data inversion is not performed, and the ferroelectric memory device does not operate normally.

In order to prevent the occurrence of the operation failure of the ferroelectric memory device due to the above-described imprint, Japanese Patent Laid-Open No.
The ferroelectric memory device described in JP-A-241375 has a circuit for writing continuous inverted data and detecting the disappearance of imprint. This ferroelectric memory device will be described.

FIG. 13 shows the structure of the above-described ferroelectric memory device. The information storage unit 43 has a ferroelectric memory composed of ferroelectric elements, and has a reading and writing function of these ferroelectric memories. Further, the information storage unit 43 has a waveform detection unit 45 that detects a waveform representing the characteristics of the ferroelectric substance. The waveform detection section 45 is configured by a general saw tower circuit. The control signal generator 41 generates a signal at a predetermined timing described later.
The polarization inversion control unit 42 inverts data in the ferroelectric memory included in the information storage unit 43 based on a signal from the control signal generation unit 41. Further, after inverting the data in the ferroelectric memory, the polarization inversion control unit 42 performs a write operation to the ferroelectric memory a predetermined number of times while further holding the inverted data. The input gate unit 39 inverts input data based on a signal generated by the gate control unit 44 or sends data to the information storage unit 43 without inversion. The output gate unit 40 inverts the data read from the information storage unit 43 based on the signal generated by the gate control unit 44, or outputs the data to the outside without inversion.
The gate control unit 44 controls the input gate unit 39 and the output gate unit 40 based on the signal generated by the control signal generation unit 41.

The operation of the ferroelectric memory device thus configured will be briefly described. When the information storage unit 43 is turned on, the control signal generation unit 41 detects that the power is turned on, and generates a memory startup signal.
The polarization inversion control unit 42 receives the above-described memory start-up signal, and inverts data of all the ferroelectric memories included in the information storage unit 43. Further, the polarization inversion control unit 42 writes the same data to the ferroelectric memory continuously a predetermined number of times while holding the above-described inverted data. When an imprint occurs in a ferroelectric memory, the hysteresis curve shifts in a certain direction as described above. However, by writing the above-described inverted data continuously, the hysteresis curve can be returned to the state before the imprint occurred. it can. Further, the presence or absence of imprint in the ferroelectric memory included in the information storage unit 43 is detected by the waveform detection unit 45, and if imprint remains, the inverted data is continuously written. As a result, imprinting can be eliminated, and imprinting in the reverse direction due to excessive continuous writing can be prevented.

The control signal generator 41 also transmits the aforementioned memory start-up signal to the gate controller 44. The gate control unit 44 receives the memory start-up signal and sends a data inversion signal to the input gate unit 39 and the output gate unit 40. The input gate unit 39 receives the above-mentioned data inversion signal, inverts the input data, and sends the inverted data to the information storage unit 43. The output gate unit 40 inverts the data read from the information storage unit 43 and sends the inverted data to the outside. By this operation, even when the data of the entire ferroelectric memory is inverted by the above-described polarization inversion control unit 42, the user of the ferroelectric memory device does not need to be aware of the inversion of the data.
The same use as usual becomes possible. After the waveform detection unit 45 detects that the imprint has disappeared, or
After writing the inversion data a certain number of times, the polarization inversion controller 42
Returns the data of the ferroelectric memory in the information storage unit 43 to the non-inverted state, and the gate control unit 44 sends a signal to the input gate unit 39 and the output gate unit 40 to stop the data inversion mode of both gate units. .

[0013]

However, the conventional ferroelectric memory device has the following problems. The waveform detector 45 in FIG. 13 has a Sawyer tower circuit for detecting a hysteresis curve indicating the characteristics of the ferroelectric. In order to measure the hysteresis curve in this Sawyer tower circuit, an AC voltage is applied to the Sawyer tower containing the ferroelectric to be measured, and the applied external voltage and the voltage applied to the ferroelectric are measured. This is realized by measuring and further calculating using the capacity value mounted on the Sawyer tower. In other words, an AC power supply and a potential measurement circuit are required, and the circuit scale becomes large.
This causes the size of the ferroelectric memory device to increase. Also, when a ferroelectric memory device is manufactured, Vt (threshold voltage) of a transistor used in the device may fluctuate due to the performance of the diffusion process, and as a result, the potential measurement circuit may not operate normally. Therefore, the occurrence of imprint cannot be reliably detected.

[0014] The present invention solves the above-mentioned problems, and it is possible to reliably detect that imprint has occurred in a ferroelectric memory cell by using a circuit that is simpler and smaller than a Sawyer tower circuit. It is an object of the present invention to provide a ferroelectric memory device that can be used.

[0015]

According to a first aspect of the present invention, there is provided a ferroelectric memory device in which information to be stored corresponds to a polarization state of a ferroelectric substance, and the ferroelectric memory device retains the information by maintaining the polarization state. A ferroelectric memory cell having a body, a data store for temporarily storing first information read from the ferroelectric memory cell, and a first information and a ferroelectric memory cell stored in the data store. A comparison circuit for comparing the read second information with the second information to detect a match between the first information and the second information; and a control unit for controlling the ferroelectric memory cell, the data store, and the comparison circuit. The control unit reads the first information from the ferroelectric memory cell in the refresh mode and causes the data storage unit to store the first information, and then writes the information opposite to the first information to the ferroelectric memory cell, After that, the ferroelectric The information is read from the recell and input to the comparison circuit unit as the second information, and when the comparison circuit unit detects coincidence between the first information and the second information, it is determined that imprint has occurred. It is like that.

According to the first aspect of the present invention, the data storage section and the comparison circuit section are provided, and the first information is read from the ferroelectric memory cell and held in the data storage section. By writing the information opposite to the first information and then comparing the second information read from the ferroelectric memory cell with the first information held in the data store by the comparison circuit, It is possible to accurately determine whether or not imprint has occurred in the ferroelectric memory cell, and to reliably detect the occurrence of imprint. As a result, the imprint mitigation operation can be performed as needed, and as a result, a long-life ferroelectric memory device can be realized. Further, the data store unit and the comparison circuit unit can be simpler and smaller in scale than the Sawyer tower circuit, and the size of the ferroelectric memory device can be reduced.

A ferroelectric memory device according to a second aspect is the ferroelectric memory device according to the first aspect,
When the control unit determines that the imprint has occurred, the control unit continuously transmits the information reverse to the first information held in the data store unit to the ferroelectric memory cell in order to ease the imprint. Writing is performed a predetermined number of times. Thereby, imprint can be eased.

According to a third aspect of the present invention, there is provided a ferroelectric memory device according to the first aspect.
The control unit, when determining that imprint has occurred, writes a predetermined number of times continuously to the ferroelectric memory cell while inverting the information to be written, in order to ease the imprint. Features. Thereby, imprint can be eased.

According to a fourth aspect of the present invention, there is provided the ferroelectric memory device according to the second or third aspect, wherein the control unit writes a predetermined number of times to the ferroelectric memory cell in order to ease imprint. After that, the first information stored in the data store unit is written in the ferroelectric memory cell. Thereby, the data of the ferroelectric memory cell can be brought into a state before entering the refresh mode.

According to a fifth aspect of the present invention, in the ferroelectric memory device, information to be stored is made to correspond to a polarization state of the ferroelectric,
A ferroelectric memory cell having a ferroelectric that holds the information by holding the polarization state, and a structure equivalent to the ferroelectric memory cell, and the polarization state is continuously inverted a predetermined number of times in the manufacturing stage. After that, a ferroelectric reference cell in which predetermined information has been written, a data store section for temporarily holding first information read from the ferroelectric reference cell,
Comparing the first information held in the data store unit with the second information read from the ferroelectric reference cell,
A control circuit for detecting a match between the first information and the second information; a control unit for controlling the ferroelectric memory cell, the ferroelectric reference cell, the data store unit, and the comparison circuit unit; In the refresh mode, after reading out the first information from the ferroelectric reference cell and holding it in the data storage section, the information opposite to the first information is written into the ferroelectric reference cell, and then the ferroelectric Information is read from the reference cell and input as second information to the comparison circuit unit. When the comparison circuit unit detects a match between the first information and the second information, it is determined that imprint has occurred. It is something to do.

According to the fifth aspect of the present invention, the ferroelectric reference cell, the data store section and the comparison circuit section are provided, and after reading the first information from the ferroelectric reference cell and holding the first information in the data store section, The opposite information to the first information is written in the ferroelectric reference cell, and then the second information read from the ferroelectric reference cell and the first information held in the data store are compared with the comparison circuit. Thus, it is possible to accurately determine whether or not imprint has occurred in the ferroelectric memory cell, and to reliably detect the occurrence of imprint. This allows
The imprint relaxation operation can be performed as required, and as a result, a long-life ferroelectric memory device can be realized. Further, the ferroelectric reference cell, the data store section, and the comparison circuit section can be a simple and small-scale circuit as compared with the Sawyer tower circuit, and the size of the ferroelectric memory device can be reduced.

The ferroelectric memory device according to claim 6 is the ferroelectric memory device according to claim 5,
The control unit has a memory cell data store unit for temporarily storing information read from the ferroelectric memory cell, and when it is determined that imprint has occurred, the memory cell data store unit stores the information read from the ferroelectric memory cell. To temporarily hold the read information and then relax the imprint, the ferroelectric reference cell and ferroelectric memory cell
Writing is continuously performed a predetermined number of times while inverting the information to be written, and then the information held in the memory cell data store is written to the ferroelectric memory cell, and further, arbitrary information is written to the ferroelectric reference cell. Features. Thereby, imprint can be eased.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a block diagram showing a configuration of a ferroelectric memory device according to a first embodiment of the present invention.

The information control section 1 includes a ferroelectric memory cell section 8, and performs writing and reading operations on the ferroelectric memory cell section 8 by an external signal. The ferroelectric memory cell unit 8 associates data (information) to be stored with the polarization state of the ferroelectric, and retains the polarization state to thereby retain a ferroelectric memory cell having the ferroelectric. Is provided with one or more. Hereinafter, the configuration of the ferroelectric memory cell unit 8 mainly including a plurality of ferroelectric memory cells will be described.

The power-on detection circuit section 5 detects that power is supplied to the ferroelectric memory device, and sends a power-on detection signal to the detection circuit control section 2.

The refresh mode start signal detecting unit 6
When a refresh mode start signal is given from outside, it is detected and sent to the detection circuit control unit 2.

When the detection circuit control unit 2 receives the power-on detection signal or the refresh mode start signal, the detection circuit control unit 2 controls the information control unit 1, the data storage unit 3, and the comparison circuit unit 4.

The data storage unit 3 is controlled by the detection circuit control unit 2 and holds data read from the ferroelectric memory cell unit 8 of the information control unit 1. For example, the configuration is as shown in FIG. 4, and the control signal 10 in FIG. 4 is a signal from the detection circuit control unit 2.

The comparison circuit section 4 is controlled by the detection circuit control section 2 and compares the data stored in the data storage section 3 with the data read from the ferroelectric memory cell section 8 of the information control section 1. Then, a comparison result signal indicating whether or not imprint has occurred is sent to the detection circuit control unit 2. For example,
As shown in FIG. 6, an exclusive OR (logical sum) circuit and an AND
(Logical product) circuit. FIG. 6 illustrates a case where data of 8 bits is compared.
When comparing 1-bit data or when the ferroelectric memory cell unit 8 is composed of only one ferroelectric memory cell, it is composed of only one exclusive OR circuit, and its output is the comparison result signal. Becomes

When the comparison result signal from the comparison circuit unit 4 indicates the occurrence of imprint, the detection circuit control unit 2 outputs an imprint relaxation mode start signal to the polarization inversion control unit 7 and receives this signal. The control unit 7 controls the information control unit 1 for writing.

It should be noted that the control section in claim 1 comprises the information control section 1 except for the ferroelectric memory cell section 8, the detection circuit control section 2, and the polarization inversion control section 7.

The operation of the ferroelectric memory device according to the present embodiment configured as described above will be described in detail below.

FIG. 2 is a flow chart of the execution of the refresh mode in the present embodiment, and shows a routine for detecting the occurrence of imprint on the ferroelectric memory and relaxing (eliminating) it. Detects the occurrence of this imprint,
A mode in which a series of operations for relaxing (eliminating) the operation and a mode for performing the operation are a refresh mode. Hereinafter, the refresh mode will be described with reference to the configuration diagram of the ferroelectric memory device of FIG. 1 and the flow of FIG.

When the power-on detection circuit 5 detects that power has been supplied to the ferroelectric memory device, the power-on detection circuit 5 sends a power-on detection signal to the detection circuit controller 2. When a refresh mode start signal is externally supplied to the refresh mode start signal detector 6, the refresh mode start signal detector 6 sends a refresh mode start signal to the detection circuit controller 2. The detection circuit controller 2 receives the power-on detection signal or the refresh mode start signal, and starts the imprint detection mode in step S1 of FIG. The refresh mode includes an imprint detection mode for detecting occurrence of imprint and an imprint relaxation mode for relaxing the detected imprint. First, in step S1, the imprint detection mode starts. Then, the detection circuit control unit 2 performs a control operation for detecting whether imprint has occurred in the ferroelectric memory cell unit 8 included in the information control unit 1.

FIG. 3 shows a flow for detecting the occurrence of imprint of the ferroelectric memory cell, and shows the processing of steps S2 and S3 in FIG.

In step S 10 of FIG. 3, the detection circuit control unit 2 reads data of, for example, 8 bits from the ferroelectric memory cell unit 8 and sends the read data to the data storage unit 3.

FIG. 4 shows an internal circuit of the data store unit 3. Data read from the ferroelectric memory cell unit 8 is input as a data signal 9 and is controlled by a store control signal 10 and stored in a central flip-flop. FIG. 3 corresponds to step S11.

In a ferroelectric memory cell in which imprint has occurred, as shown in FIG. 5, there is almost no difference between the read potential difference 11 before the imprint has occurred and the read potential difference 12 after the imprint has occurred. Therefore, even if imprint occurs, the reading operation is not hindered and data can be read normally.

Next, in step S12, the detection circuit control unit 2 sends a signal to the information control unit 1 to perform an operation of writing data opposite to the read data to each of the bits read in step S10. . Information control unit 1
Receives this, and writes the reverse data to the bit read in step S10 in the same routine as in normal use.

Here, as described above with reference to FIG. 12, when imprint occurs in the ferroelectric memory cell, data reverse to the data written before the imprint occurred can be written. It will be difficult. That is, in step S12 in which data is written at the write voltage during normal use, whether or not data is normally written is determined by the degree of imprint occurrence.

After writing the reverse data in step S12, in step S13, the information control unit 1 uses the signal written in step S12 to convert the data written in step S12 into the same routine as that in normal use, according to a signal from the detection circuit control unit 2. Read with. As shown in FIG. 5 described above, the read operation can be performed normally even when imprint has occurred, so that when data is normally written in the ferroelectric memory cell, the data is normally written. Can be read.

The data read in step S13 is sent to the comparison circuit unit 4, and the data and the data stored in the data storage unit 3 in step S11 are compared by the comparison circuit unit 4. FIG. 3 corresponds to step S14.

FIG. 6 shows an internal circuit of the comparison circuit section 4. The data SD1 to SD8 stored in the data storage unit 3 in step S11 and the data RD1 to RD8 read in step S13 are input and compared, and a comparison result signal 15 is output. SD1 and RD1, SD2 and RD2, ..., SD8 and RD8 are
These are data read in Steps 10 and 13 from the same ferroelectric memory cell, respectively. In the result represented by the comparison result signal 15, the data SD1 to SD8 stored in the data
If the data RD1 to RD8 read out in step 3 are all inverted data, it can be determined that imprint has not occurred in the ferroelectric memory cell enough to cause a malfunction during normal use. In that case, the comparison result signal 15
Is output as “H”. If the result is other than that, it can be determined that imprint has occurred. In that case, “L” is output as the comparison result signal 15. The reason is described below.

In step S12, if data has not been normally written in the 8 bits of the ferroelectric memory cell section 8 due to the occurrence of imprint, a read potential difference from which data can be read normally is obtained. Therefore, the data reading in step S13 is not performed normally. If the write operation is normally performed in step S12,
This means that data opposite to the data stored in step S11 has been written, and the data stored in the data storage unit 3 and the data read in step S13 are the reverse data. For this reason, if imprint has occurred, the data stored in the data storage unit 3 in step S11 and the data read in step S13 are:
The data is not completely reversed, and it can be determined that imprint has occurred in the ferroelectric memory cell. In addition, when reading is performed in step S13 when imprinting has occurred, even if data that is the reverse of the data stored in the data storage unit 3 is accidentally read out, in the above-described normal reading operation, Because of the rewriting operation, imprinting is eased. Thus, in step S15 in FIG. 3, the presence or absence of imprint is detected based on the comparison result signal 15.

As described above, the presence or absence of imprint occurrence is detected in step S3 of FIG. 2, and if the occurrence of imprint is detected, the imprint mitigation mode of step S4 is started. The purpose of this mode is to correct the shift of the hysteresis curve in 8 bits of the ferroelectric memory cell unit 8 due to the occurrence of imprint.
The operation will be described below.

The detection circuit control unit 2 receives the comparison result signal 15 from the comparison circuit unit 4, and the comparison result signal 15 becomes "L".
If so, an imprint relaxation mode start signal is sent to the polarization inversion control unit 7. Step S4 in FIG. 2 corresponds to this.

The polarization reversal control unit 7 receiving the imprint relaxation mode start signal from the detection circuit control unit 2
, A signal for writing data, which is the reverse of the data stored in the data storage unit 3, continuously for a predetermined number of times. In response to this signal, the information control unit 1 writes data opposite to the data stored in the data storage unit 3 into each ferroelectric memory cell a predetermined number of times consecutively (step S).
5). By performing this operation, the hysteresis curve of the ferroelectric memory cell shifted left and right due to the occurrence of imprint can be returned to the state before the occurrence of imprint. FIG.
Indicates a state in which the hysteresis curve returns to the state before the imprint occurred by continuous writing. Curve 1
Numeral 6 denotes a hysteresis curve after the imprint has occurred, and curve 17 denotes a hysteresis curve shifted by the continuous writing operation. The amount of movement of this curve depends on the number of consecutive writings, and the greater the number of times, the greater the amount of movement. Therefore, it is desirable that the number of continuous writing be a number corresponding to the amount of movement of the hysteresis curve that causes a malfunction during normal use.

After the writing has been performed a predetermined number of times in step S5, the data stored in the data storage section 3 is written into the 8 bits of the ferroelectric memory cell section 8 to be detected. Step S6 corresponds to this. As a result, 8
The bit ferroelectric memory cell returns to the state before entering the refresh mode.

Thereafter, in steps S7 and S8, imprint detection is performed again, and it is determined that imprint has occurred. That is, it is determined that the hysteresis curve has not sufficiently returned to the state before the imprint occurred. If
Returning to step S4, the continuous write operation is performed. By this imprint detection or relaxation operation again, imprint in the reverse direction due to excessive continuous writing can be prevented. Steps S7 and S8 are the same as step S
2, S3, which is shown in the flow of FIG.

If no imprint is detected in step S8, an imprint detection operation is similarly performed from step S2 for the next 8 bits in the ferroelectric memory cell unit 8, and the occurrence of imprint is detected. Then, the continuous writing operation is performed.

Further, even when the imprint is not detected in step S3, the data stored in the data storage section 3 is written into the 8 bits of the ferroelectric memory cell section 8 to be detected, and Return to the state before the detection operation. Step S9 corresponds to this. Then step S
Returning to step 2, the detection operation is started for the next 8 bits.

As described above, whether or not imprint has occurred for all bits of the ferroelectric memory cell unit 8 is detected, and if it has occurred, it is eliminated by continuous writing. Thus, the refresh mode ends when the above operation is performed on all the bits. As described above, by correcting the hysteresis curve for the bit where the imprint has occurred, a ferroelectric memory device having a long life can be realized.

According to the present embodiment, the data store 3
And a comparison circuit unit 4 for reading data from the ferroelectric memory cell and holding the data in the data storage unit 3, and then writing data opposite to the data held in the data storage unit 3 in the ferroelectric memory cell, and thereafter By comparing the data read from the ferroelectric memory cell with the data held in the data store unit 3 by the comparison circuit unit 4, it is accurately determined whether or not imprint has occurred in the ferroelectric memory cell. It is possible to reliably detect the occurrence of imprint. As a result, the imprint mitigation operation can be performed as needed, and as a result, a long-life ferroelectric memory device can be realized.

The data store section 3 composed of flip-flops and transistors as shown in FIG. 4 and the comparison circuit section 4 composed of exclusive OR circuits and AND circuits as shown in FIG. 6 are CMOS circuits. It can be configured as a simple and small-scale circuit as compared with the Sawyer tower circuit, and the size of the ferroelectric memory device can be reduced.

In the first embodiment, in step S5, data opposite to the data stored in the data storage unit 3 is written continuously for a predetermined number of times. As in step S16 in the embodiment, the data to be written is “H”, “L”, “H”, “L”,.
The polarization inversion writing may be performed by continuously writing a predetermined number of times while inverting.

In step S5, the data storage unit 3
When the data reverse to the data stored in the data storage unit 3 has been written continuously for a predetermined number of times, and the data reverse to the data stored in the data storage unit 3 is imprinted in the ferroelectric memory cell, However, the deviation of the hysteresis curve due to the occurrence of imprint can also be corrected by writing the number of times that the reverse data can be sufficiently written, and then leaving it for a certain period of time.

In the first embodiment, the number of ferroelectric memory cells to be used for detecting the occurrence of imprint is set to 8 bits at a time, but the number which can be read in one cycle, for example, 16 bits Or 32 bits. In that case, the number of times of imprint detection in one refresh mode is reduced, and the time in the refresh mode is reduced.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
An embodiment will be described. In the first embodiment, the target of the imprint detection operation (step S2 in FIG. 2) is the ferroelectric memory cell unit 8 included in the information control unit 1, but in the second embodiment, the imprint detection operation is performed. A reference cell is provided, and imprint detection is performed on the reference cell.

FIG. 8 is a block diagram showing a configuration of a ferroelectric memory device according to the second embodiment. The main difference from FIG. 1 is a cell (reference cell) having the same structure as the ferroelectric memory cell constituting the ferroelectric memory cell unit 8, and is constituted by a predetermined number, for example, 8-bit reference cells. The difference is that a reference cell unit 18 is added, and a memory cell data storage unit 46 for temporarily storing data read from a memory cell is added. Memory cell data storage unit 4
Reference numeral 6 denotes a CMOS circuit, and the amount of data that can be stored at one time is arbitrary.

Each reference cell of the reference cell section 18 is used during the manufacturing stage of the ferroelectric memory device.
A stress for continuously writing data while inverting the data a certain number of times is applied, and the shift of the hysteresis curve due to imprint generation is smaller than that of a normal ferroelectric memory cell in the ferroelectric memory cell unit 8. It is characterized by being large. After the above-described continuous data writing, predetermined (arbitrary) data is written in the reference cell.

The refresh mode in the second embodiment will be described below. FIG. 9 shows a flow of the refresh mode in the second embodiment.

First, as in the first embodiment, when the power supply to the ferroelectric memory device is detected, or when the refresh mode start signal is applied from the outside, the imprint detection in the refresh mode is performed. The mode is started (step S1).

When the refresh mode is started, imprint detection is started in step S2. Regarding the imprint detection operation, in the first embodiment, the detection target is 8 bits of the ferroelectric memory cell unit 8, whereas in the second embodiment, all bits (8 bits) of the reference cell unit 18 are detected. Bit), the description is omitted here. By setting the reference cell section 18 as an imprint detection target, there are advantages described below as compared with the first embodiment. As described above, since the imprint tends to occur in the reference cell in the normal ferroelectric memory cell in the ferroelectric memory cell unit 8, the hysteresis curve of the normal ferroelectric memory cell due to the imprint is shifted. At the stage when the amount is small,
Imprint occurrence can be detected. As a result, a margin can be obtained for a malfunction due to imprint generation during normal use. Further, by performing the polarization inversion writing described later for all bits, the number of times of imprint detection is greatly reduced, and the time for the refresh mode can be reduced.

If no imprint is detected in step S3 of FIG. 9, the refresh mode ends.
If imprint is detected in step S3, the imprint mitigation mode of step S4 is started. In step S17, data of the memory cell (for example, 8 bits) in the imprint mitigation mode in the memory cell unit 8 of FIG. 8 is read and stored in the memory cell data storage unit 46. After that, in step S16, the data to be written into the memory cell to be subjected to the imprint relaxation mode is inverted to “H”, “L”, “H”, “L”,. Write. By performing this writing, the hysteresis curve whose state has changed due to the occurrence of imprinting returns to the state before imprinting occurred, and the occurrence of imprinting in the reverse direction due to excessive writing can be prevented. After terminating the polarization inversion writing a predetermined number of times, data is read from the memory cell data storage unit 46, and rewriting is performed on the memory cell targeted for the imprint mitigation mode. Step S6 corresponds to this. The operation from the data store to the rewrite is performed for all the memory cells of the memory cell unit 8. After performing the polarization inversion writing on all the memory cells, the polarization inversion writing is performed on the reference cell unit 18. Step S18
Corresponds to this.

After performing the domain inversion writing as described above,
The imprint detection is performed again on the reference cell unit 18 to confirm that the deviation of the hysteresis curve due to the imprint has been corrected by the polarization inversion writing (steps S2 and S3). When the imprint is detected, the imprint relaxation mode in step S4 is started again.

By performing imprint detection and polarization inversion writing as described above, a shift in the hysteresis curve due to imprint generation can be corrected, and a long-life ferroelectric memory device can be realized.

According to the present embodiment, the reference cell section 18, the data storage section 3, and the comparison circuit section 4 are provided, data is read from the reference cell section 18 and held in the data storage section 3, Write the opposite data to the data held in the data store unit 3,
Thereafter, the comparison circuit 4 compares the data read from the reference cell 18 with the data held in the data store 3 to determine whether imprint has occurred in the ferroelectric memory cell 8. Accurate determination can be made, and occurrence of imprint can be reliably detected. In this case, since imprint occurrence is detected for the reference cell section 18 where imprinting is more likely to occur than in the ferroelectric memory cell section 8, the imprinting is detected at an early stage compared to the first embodiment. Print occurrence can be detected. As a result, the imprint mitigation operation can be performed as needed, and as a result, a long-life ferroelectric memory device can be realized.

The second embodiment has a configuration in which a reference cell unit 18 is added to the configuration of the first embodiment. The size of the ferroelectric memory cell is not larger than the size of the ferroelectric memory cell, and is very small in circuit size as compared with the Sawyer tower circuit. As compared with the circuit, the circuit can be simple and small in scale, and the size of the ferroelectric memory device can be reduced.

In the second embodiment, the number of bits (the number of cells) of the reference cell section 18 is set to 8 bits. However, the number may be 1 bit or more. As the number of bits of the reference cell unit 18 is increased, the detection accuracy of imprint occurrence can be improved.
Thus, the circuit scale of the data store unit 3 becomes large.

[0070]

As described above, according to the present invention, it is possible to reliably detect the occurrence of imprint in a ferroelectric memory cell by using a circuit that is much simpler and smaller than a Sawyer tower circuit. As a result, an imprint mitigation operation can be performed as required, and a long-life ferroelectric memory device can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a ferroelectric memory device according to a first embodiment of the present invention.

FIG. 2 is an execution flowchart of a refresh mode according to the first embodiment of the present invention.

FIG. 3 is an execution flowchart of imprint detection according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a data storage unit 3 of FIG.

FIG. 5 is a diagram showing a hysteresis curve representing a change in a read voltage before imprint occurs and after imprint occurs.

FIG. 6 is a circuit diagram showing one example of a comparison circuit unit 4 of FIG. 1;

FIG. 7 is a diagram showing hysteresis curves after imprint generation and after imprint mitigation.

FIG. 8 is a block diagram showing a configuration of a ferroelectric memory device according to a second embodiment of the present invention.

FIG. 9 is an execution flowchart of a refresh mode according to the second embodiment of the present invention.

FIG. 10 is a diagram showing a circuit configuration example for realizing reading and writing of a ferroelectric memory cell.

FIG. 11 is a diagram showing a hysteresis curve representing a read voltage and a polarization inversion voltage of a ferroelectric memory cell.

FIG. 12 is a diagram showing a hysteresis curve showing a change in polarization reversal voltage due to imprint generation.

FIG. 13 is a block diagram showing a configuration of a conventional ferroelectric memory device for preventing malfunction due to imprint generation.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 information control unit 2 detection circuit control unit 3 data store unit 4 comparison circuit unit 5 power-on detection circuit unit 6 refresh mode start signal detection unit 7 polarization inversion control unit 8 ferroelectric memory cell unit 18 reference cell unit 46 memory cell data Store Department

Claims (6)

[Claims] 1. A ferroelectric memory cell having a ferroelectric that retains information by associating information to be stored with a polarization state of the ferroelectric and maintaining the polarization state. A data storage unit for temporarily storing first information read from a cell; comparing the first information stored in the data store unit with second information read from the ferroelectric memory cell; A comparison circuit unit that detects a match between the first information and the second information; and a control unit that controls the ferroelectric memory cell, the data store unit, and the comparison circuit unit. In the mode, after reading the first information from the ferroelectric memory cell and holding the first information in the data store unit, information opposite to the first information is written into the ferroelectric memory cell, and then the Ferroelectric Information is read from a memory cell and input as the second information to the comparison circuit unit. When the comparison circuit unit detects a match between the first information and the second information, imprint occurs. Ferroelectric memory device that is determined to be 2. When the control unit determines that imprint has occurred, the control unit transmits the first information stored in the data store unit to the ferroelectric memory cell to reduce imprint. 2. The ferroelectric memory device according to claim 1, wherein information opposite to the above is written continuously a predetermined number of times. 3. The control unit, when judging that imprint has occurred, continuously writes the ferroelectric memory cell a predetermined number of times while inverting the information to be written, in order to ease the imprint. 2. The ferroelectric memory device according to claim 1, wherein 4. The control section writes the first information held in the data store section to the ferroelectric memory cell after writing the ferroelectric memory cell a predetermined number of times to ease imprint. 4. The ferroelectric memory device according to claim 2, wherein the data is written in a cell. 5. A ferroelectric memory cell having a ferroelectric which holds information to be stored by associating information to be stored with a polarization state of the ferroelectric and holding the polarization state. A ferroelectric reference cell which has a structure equivalent to that of the cell, and in which the polarization state is continuously inverted a predetermined number of times in the manufacturing stage, and in which predetermined information is written; and a first cell which is read from the ferroelectric reference cell. A first information stored in the data store unit and second information read from the ferroelectric reference cell, and the first information and the second information are compared. A comparison circuit unit that detects coincidence with the information of the above, and a control unit that controls the ferroelectric memory cell, the ferroelectric reference cell, the data store unit, and the comparison circuit unit, wherein the control unit includes: Re In the refresh mode, after reading out the first information from the ferroelectric reference cell and holding the first information in the data store section, information opposite to the first information is written into the ferroelectric reference cell, and thereafter, Information is read from the ferroelectric reference cell and input to the comparison circuit unit as the second information. When the comparison circuit unit detects a match between the first information and the second information, the input is performed. A ferroelectric memory device configured to determine that printing has occurred. 6. The control section has a memory cell data storage section for temporarily storing information read from the ferroelectric memory cell, and when it is determined that imprint has occurred, the control section has a memory cell data store section. Section temporarily holds the information read from the ferroelectric memory cell, and then successively inverts the information to be written to the ferroelectric reference cell and the ferroelectric memory cell to alleviate imprint. 6. A method according to claim 5, further comprising: writing a predetermined number of times, writing information held in said memory cell data store into said ferroelectric memory cell, and writing arbitrary information into said ferroelectric reference cell. A ferroelectric memory device according to claim 1.