JP3727451B2 - Semiconductor memory device and semiconductor memory device access method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a semiconductor memory device access method, and more particularly to suppression of occurrence of an imprint effect.
[0002]
[Background Art and Problems to be Solved by the Invention]
2. Description of the Related Art In recent years, ferroelectric memory devices that provide data non-volatility by using a ferroelectric material for a memory cell capacitor have been provided. The ferroelectric capacitor has a hysteresis characteristic, and even when the electric field becomes “0”, polarizations having different polarities depending on the history remain. By expressing the data as the polarization of the ferroelectric capacitor, a nonvolatile memory device is realized.
[0003]
FIG. 4 shows a circuit diagram of the ferroelectric capacitor. Ferroelectric capacitors 61 and 62 are provided on the bit lines BL1 and BL2, respectively. FIG. 3 shows a voltage related to the ferroelectric capacitor (the potentials of the bit lines BL1 and BL2 when the plate line PL shown in FIG. 4 is a reference potential) and a polarization state (in the figure, equivalent to “polarization state”). Hysteresis characteristics indicating the relationship to “charge”.
[0004]
In FIG. 3, it is assumed that the state in which the polarization Z1 occurs corresponds to the stored data “1”, and the state in which the polarization Z2 occurs corresponds to the stored data “0”. By examining which polarization state the ferroelectric capacitor is in, the stored data of the ferroelectric capacitor can be read out. It is assumed that the storage data “1” is stored in the ferroelectric capacitor 61 shown in FIG. 4 (polarization Z1 in FIG. 3), and the storage data “0” is stored in the ferroelectric capacitor 62 (FIG. 4). 3 polarization Z2).
[0005]
FIG. 5 is a timing chart for reading stored data. When reading data stored in the ferroelectric capacitor, an H signal is applied to the word line WL (timing T52), and the switches 63 and 64 in FIG. 4 are closed. Then, the plate line PL is set to H (timing T54 to T56).
[0006]
By setting the plate line PL to H, charges are discharged from the ferroelectric capacitors 61 and 62 toward the bit lines BL1 and BL2, and a current flows. The amount of the discharged electric charge varies depending on the polarization state of the ferroelectric capacitors 61 and 62.
[0007]
That is, a relatively large amount of charge is released from the ferroelectric capacitor 61, and a relatively small amount of charge is released from the ferroelectric capacitor 62. At timing T58 in FIG. 5, the sense amplifier is turned on, and is divided into H and L according to the discharged charges. In this case, as shown in FIG. 5, the bit line BL 1 becomes H and the bit line BL 2 becomes L, so that the storage data “1” is stored in the ferroelectric capacitor 61 and stored in the ferroelectric capacitor 62. It can be seen that data “0” was stored.
[0008]
With respect to the ferroelectric capacitor 61 in which a large amount of electric charge is released at the time of reading and the polarization state is reversed, the stored data is destroyed. For this reason, it is necessary to rewrite the stored data immediately after reading, that is, to reverse the polarization state again and return to the original state.
[0009]
When the sense amplifier is turned on at timing T58 in FIG. 5, since the plate line PL is at L, the polarization state of the ferroelectric capacitor 61 is reversed again to return to the original polarization state. (Rewrite). Thereafter, the plate line PL becomes H (timing T60 to T62), and the polarization state of the ferroelectric capacitor 62 in which the stored data is not destroyed (the polarization state is not reversed) is surely held. At time T64, the word line W is set to L and the switches 63 and 64 in FIG. 4 are opened.
[0010]
Reading and rewriting of the ferroelectric capacitors 61 and 62 described above will be described based on the hysteresis characteristics of FIG. First, with respect to the ferroelectric capacitor 61, the polarization state shifts from P1 to P2 in FIG. 3 at timings T54 to T56, and the polarization state reaches P4 at timing T58 at which rewriting is performed. At time T64, the process returns from P4 to P1.
[0011]
As described above, with respect to the ferroelectric capacitor 61 whose stored data is destroyed by reading, the polarization state goes around along the hysteresis characteristics shown in FIG. 3 at the time of reading and rewriting.
[0012]
On the other hand, with respect to the ferroelectric capacitor 62, the polarization state slightly shifts from P3 in FIG. 3 toward P2 along the broken line at timings T54 to T56, and the polarization state returns to P3 at timing T58. At timing T60, the process shifts from P3 to P2 along the broken line, and returns to P3 at timing T62.
[0013]
As described above, with respect to the ferroelectric capacitor 62 in which the stored data is not destroyed by reading, the polarization state does not go around the hysteresis characteristic shown in FIG. 3 at the time of reading, but simply shifts between P3 and P2. is there.
[0014]
By the way, a ferroelectric has a property (imprint effect) that when a certain polarization state is maintained for a long time, the polarization state is “queried” and distortion occurs in hysteresis characteristics. For this reason, if a certain amount of data is stored for a long time, an imprint effect occurs in the ferroelectric capacitor. When the imprint effect occurs, the amount of electric charge discharged at the time of reading changes.
[0015]
In particular, when the storage data opposite to the storage data when the imprint effect occurs is newly written, the ability to retain the polarization state of the new storage data decreases due to the influence of the original storage data, This new stored data cannot be read accurately. That is, with the passage of time, the function as a storage device may be reduced and may not be used.
[0016]
As described above, with respect to the ferroelectric capacitor 61 whose stored data is destroyed by reading, the polarization state makes a round along the hysteresis characteristics shown in FIG. This polarization state is not maintained for a long time, and the imprint effect hardly occurs.
[0017]
On the other hand, with respect to the ferroelectric capacitor 62 in which the stored data is not destroyed by reading, the polarization state does not go around the hysteresis characteristic shown in FIG. 3 at the time of reading, but simply shifts between P3 and P2. It is. For this reason, a constant polarization state is maintained for a long time, and there is a possibility that an imprint effect due to the “crimping” occurs.
[0018]
As a prior art for suppressing the occurrence of an imprint effect, there is a nonvolatile random access memory disclosed in Japanese Patent Laid-Open No. 8-264665. This prior art publication describes that reading with a low voltage can be performed to obtain a device with less influence of imprint and film fatigue resistance.
[0019]
However, in this nonvolatile random access memory, the generation of the imprint effect of the ferroelectric substance can be suppressed only to the dummy cell, and the generation of the imprint effect of the memory cell for storage can be suppressed. Can not. In other words, the target that can suppress the occurrence of the imprint effect is limited, and the occurrence of the imprint effect in the semiconductor memory device cannot be reliably suppressed.
[0020]
As another conventional technique for suppressing the occurrence of the imprint effect, there is a ferroelectric memory device disclosed in Japanese Patent Laid-Open No. 8-147983. In this ferroelectric memory device, the memory cell capacitor for storage is repeatedly operated until the capacitance characteristic no longer changes in the 1T1C type, and the capacitance value of the dummy cell capacitor is determined according to the capacitance characteristic at that time. This is intended to reduce the influence of the imprint effect.
[0021]
However, in this ferroelectric memory device, it is necessary to repeatedly operate the memory cell capacitor for storage until the capacitance characteristics no longer change, and to determine the capacitance value of the dummy cell capacitor. Generation of effects cannot be suppressed.
[0022]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device and a semiconductor memory device access method that can easily and reliably suppress the occurrence of an imprint effect.
[0023]
[Means for Solving the Problems]
(1) A semiconductor device access method according to the present invention includes:
A ferroelectric capacitor that stores first data or second data corresponding to each state by holding a first polarization state or a second polarization state opposite to the first polarization state;
A plate line for writing first data or second data, connected to one end of the ferroelectric capacitor;
A bit line connected to the other end of the ferroelectric capacitor for reading out the first data or the second data;
A control unit for controlling storage processing or readout processing to the ferroelectric capacitor;
An inverting circuit that amplifies and distributes the bit line voltage, and amplifies and distributes the bit line voltage by the inverting circuit based on the sense amplifier signal from the control unit, and a bit based on the switching signal from the control unit A sense amplifier having an AND circuit for switching the voltage of the line;
A method for accessing a semiconductor device comprising:
The control unit outputs a sense amplifier signal to the sense amplifier,
The sense amplifier operates an inverting circuit based on the signal from the AND circuit that receives the sense amplifier signal, and amplifies the voltage of the bit line according to the electric charge discharged from the ferroelectric capacitor toward the bit line. Sort and hold
The control unit reads first data or second data from the bit line,
For the ferroelectric capacitor storing the first data in which the polarization state is reversed at the time of reading, the polarization state is reversed again to return to the original state,
When the control unit provides a switching signal to the sense amplifier, the AND circuit switches the voltage of the bit line so as to reverse the polarization state of the ferroelectric capacitor storing the first data,
The controller further applies a voltage to the plate line so as to reverse the polarization state of the ferroelectric capacitor storing the second data,
When the control unit gives a switching signal to the sense amplifier, the AND circuit switches the bit line voltage so as to invert the polarization state of the ferroelectric capacitor storing the second data again,
The control unit applies a voltage to the plate line to reverse the polarization state of the ferroelectric capacitor storing the first data again.
It is characterized by that.
[0024]
(2) A semiconductor device access method according to the present invention includes:
There are two ferroelectric capacitors,
One ferroelectric capacitor stores the first data by holding the first polarization state, and the other one ferroelectric capacitor stores the second data by holding the second polarization state.
It is characterized by that.
[0026]
According to a fourth aspect of the present invention, there is provided a semiconductor memory device.
Corresponding to the first data corresponding to the first polarization state or the second polarization state by polarizing the polarizable region to the first polarization state or by polarizing to the second polarization state opposite to the first polarization state Second data to be stored,
Semiconductor memory device that reverses the second polarization state to the first polarization state and reads the second data as the second data read processing, reads the second data, and then returns the first polarization state to the second polarization state In
When storing or reading at least the first data, separately from the storage process or the read process, the first state is once reversed to the second state as an incidental process, and then returned to the first state.
It is characterized by that.
[0027]
According to a fifth aspect of the present invention, there is provided a semiconductor memory device.
In the semiconductor memory device according to claim 3 or 4,
The separable region is a ferroelectric,
It is characterized by that.
[0028]
An access method of a semiconductor memory device according to claim 6 is:
In an access method of a semiconductor memory device that stores first data or second data by holding a first state corresponding to first data or a second state corresponding to second data,
When storing or reading the first data, the first state is once reversed to the second state, then returned to the first state,
And,
When storing or reading the second data, the second state is once reversed to the first state and then returned to the second state.
It is characterized by that.
[0029]
An access method for a semiconductor memory device according to claim 7 is:
In an access method of a semiconductor memory device that stores first data or second data by holding a first state corresponding to first data or a second state corresponding to second data,
When storing or reading at least the first data, separately from the storage process or the read process, the first state is once reversed to the second state as an incidental process, and then returned to the first state.
It is characterized by that.
[0030]
【The invention's effect】
(1) A semiconductor device access method according to the present invention includes:
A ferroelectric capacitor that stores first data or second data corresponding to each state by holding a first polarization state or a second polarization state opposite to the first polarization state;
A plate line for writing first data or second data, connected to one end of the ferroelectric capacitor;
A bit line connected to the other end of the ferroelectric capacitor for reading out the first data or the second data;
A control unit for controlling storage processing or readout processing to the ferroelectric capacitor;
An inverting circuit that amplifies and distributes the bit line voltage, and amplifies and distributes the bit line voltage by the inverting circuit based on the sense amplifier signal from the control unit, and a bit based on the switching signal from the control unit A sense amplifier having an AND circuit for switching the voltage of the line;
A method for accessing a semiconductor device comprising:
The control unit outputs a sense amplifier signal to the sense amplifier,
The sense amplifier operates an inverting circuit based on the signal from the AND circuit that receives the sense amplifier signal, and amplifies the voltage of the bit line according to the electric charge discharged from the ferroelectric capacitor toward the bit line. Sort and hold
The control unit reads first data or second data from the bit line,
For the ferroelectric capacitor storing the first data in which the polarization state is reversed at the time of reading, the polarization state is reversed again to return to the original state,
When the control unit provides a switching signal to the sense amplifier, the AND circuit switches the voltage of the bit line so as to reverse the polarization state of the ferroelectric capacitor storing the first data,
The controller further applies a voltage to the plate line so as to reverse the polarization state of the ferroelectric capacitor storing the second data,
When the control unit gives a switching signal to the sense amplifier, the AND circuit switches the bit line voltage so as to invert the polarization state of the ferroelectric capacitor storing the second data again,
The control unit applies a voltage to the plate line to reverse the polarization state of the ferroelectric capacitor storing the first data again.
It is characterized by that.
[0032]
In the semiconductor memory device according to claim 2, when at least the first data is stored or read, the first state is once reversed to the second state as an incidental process separately from the storage process or the read process. Return to the first state.
[0033]
For this reason, the danger that a 1st state is hold | maintained for a long time can be reduced, and generation | occurrence | production of the imprint effect by the cursing of a 1st state can be suppressed reliably. Moreover, since it is only necessary to reverse the first state to the second state and then return to the first state, it is possible to easily suppress the occurrence of the imprint effect. Further, since the incidental process is performed together with the storage process or the read process and only the incidental process is not performed independently of the storage process or the read process, the process control is easy and efficient.
[0034]
In the semiconductor memory device according to claim 3, the first state is a first polarization state in which the polarizable region is polarized, and the second state is that the polarizable region is polarized in a direction opposite to the first polarization state. The second polarization state.
[0035]
Therefore, the risk of maintaining the first polarization state or the second polarization state for a long time can be reduced, and the occurrence of the imprint effect due to the first polarization state or the second polarization state is easily and reliably suppressed. can do.
[0036]
In the semiconductor memory device according to claim 4, when at least the first data is stored or read, the first state is once reversed to the second state as an incidental process separately from the storage process or the read process. Return to the first state.
[0037]
For this reason, the danger that a 1st state is hold | maintained for a long time can be reduced, and generation | occurrence | production of the imprint effect by the cursing of a 1st state can be suppressed reliably. Moreover, since it is only necessary to reverse the first state to the second state and then return to the first state, it is possible to easily suppress the occurrence of the imprint effect. Further, since the incidental process is performed together with the storage process or the read process and only the incidental process is not performed independently of the storage process or the read process, the process control is easy and efficient.
[0038]
In the semiconductor memory device according to the fifth aspect, the separable region is a ferroelectric.
[0039]
Therefore, it is possible to reduce the risk that the first polarization state or the second polarization state of the separable region in the ferroelectric material is maintained for a long time, and the imprint effect due to the kinking of the first polarization state or the second polarization state Can be easily and reliably suppressed.
[0040]
In the semiconductor memory device access method according to claim 6, when storing or reading the first data, the first state is once reversed to the second state, then returned to the first state, and the second data When storing or reading data, the second state is once reversed to the first state and then returned to the second state.
[0041]
That is, when reading the first data or the second data, the state is once reversed and then returned to the original state. For this reason, the risk that the first state and the second state are maintained for a long time can be reduced, and the occurrence of the imprint effect due to the clinging of the first state or the second state can be reliably suppressed. Further, since it is only necessary to reverse the state once upon reading and then return to the original state, it is possible to easily suppress the occurrence of the imprint effect.
[0042]
In the semiconductor memory device access method according to claim 7, when storing or reading at least the first data, the first state is temporarily reversed to the second state as an incidental process separately from the storage process or the read process. After that, the first state is restored.
[0043]
For this reason, the danger that a 1st state is hold | maintained for a long time can be reduced, and generation | occurrence | production of the imprint effect by the cursing of a 1st state can be suppressed reliably. Moreover, since it is only necessary to reverse the first state to the second state and then return to the first state, it is possible to easily suppress the occurrence of the imprint effect. Furthermore, since the incidental process is performed together with the storage process or the read process and only the incidental process is not performed separately from the storage process or the read process, the process control is easy and efficient.
[0044]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of a semiconductor memory device and a semiconductor memory device access method according to the present invention will be described with reference to the drawings. In this embodiment, a two-transistor two-capacitor type ferroelectric memory is taken as an example.
[0045]
FIG. 1 is a circuit diagram of the sense amplifier 2, ferroelectric capacitors 61 and 62, and the like. The ferroelectric portions of the ferroelectric capacitors 61 and 62 are polarizable regions in the present embodiment. FIG. 2 is a timing chart at the time of reading stored data stored in the ferroelectric capacitors 61 and 62. Further, FIG. 3 is a diagram showing a hysteresis characteristic representing the relationship between the voltage and the polarization state relating to the ferroelectric capacitor.
[0046]
In FIG. 3, it is assumed that the state in which the polarization Z1 occurs corresponds to the stored data “1”, and the state in which the polarization Z2 occurs corresponds to the stored data “0”. In the present embodiment, the state in which the polarization Z1 is generated is the first polarization state or the first state, and the stored data “1” is the first data. In the present embodiment, the state in which the polarization Z2 is generated is the second polarization state or the second state, and the stored data “0” is the second data.
[0047]
By examining which polarization state the ferroelectric capacitor is in, the stored data of the ferroelectric capacitor can be read out. Note that storage data “1” is stored in the ferroelectric capacitor 61 shown in FIG. 1 (polarization Z1 in FIG. 3), and storage data “0” is stored in the ferroelectric capacitor 62 (FIG. 3). 3 polarization Z2).
[0048]
  When reading data from the ferroelectric capacitors 61 and 62, a control unit (not shown) gives an H signal to the word line WL (FIG. 2, timing T2), and switches 63 and 64 in FIG.open. Then, the control unit sets the plate line PL to H (timing T4 to T6).
[0049]
By setting the plate line PL to H, charges are discharged from the ferroelectric capacitors 61 and 62 toward the bit lines BL1 and BL2, and a current flows. The amount of the discharged electric charge varies depending on the polarization state of the ferroelectric capacitors 61 and 62. That is, a relatively large amount of charge is released from the ferroelectric capacitor 61, and a relatively small amount of charge is released from the ferroelectric capacitor 62.
[0050]
At timing T8 in FIG. 5, the control unit outputs a sense amplifier signal. Based on this sense amplifier signal, a signal is output from the AND circuit 21 in FIG. 1, and the switches 11 and 12 in the sense amplifier 2 are closed. Thus, the inverting circuits 23 and 24 amplify the voltages of the bit lines BL1 and BL2 according to the electric charges discharged toward the bit lines BL1 and BL2, and distribute and hold the voltages to H and L.
[0051]
In this case, as shown in FIG. 2, the bit line BL 1 becomes H and the bit line BL 2 becomes L, so that the storage data “1” is stored in the ferroelectric capacitor 61 and stored in the ferroelectric capacitor 62. It can be seen that data “0” was stored.
[0052]
For the ferroelectric capacitor 61 whose polarization state has been reversed upon reading, the stored data will be destroyed. Therefore, immediately after the reading, the stored data is rewritten, that is, the polarization state is reversed again to restore the original state. It is necessary to return to When the sense amplifier is turned on at timing T8 in FIG. 2, since the plate line PL is L, the polarization state of the ferroelectric capacitor 61 is reversed again and returns to the original polarization state. (Rewrite).
[0053]
In the present embodiment, processing at timings T12, T13, and T14 is performed in order to suppress the occurrence of the imprint effect of the ferroelectric capacitor 62. The timings T12, T13, and T14 in this embodiment are incidental processes. In this embodiment, timings T4, T6, and T8 for reading and rewriting stored data are read processing.
[0054]
First, the plate line PL is set to H at timing T12, and the control unit supplies a switching signal to the sense amplifier 2. By this switching signal, the switches 11 and 12 shown in FIG. 1 are opened and the switches 13 and 14 are closed. As a result, the bit line BL1 becomes L and the bit line BL2 becomes H as shown in FIG. In this case, since the plate line PL is H and the bit line BL1 is L, the polarization state of the ferroelectric capacitor 61 is inverted again.
[0055]
Thereafter, at timing T14, the control unit sets the plate line PL to L. Since the plate line PL is L and the bit line BL2 is H, the polarization state of the ferroelectric capacitor 62 is reversed here. Then, the switching signal is set to L at timing T16. As a result, the bit line BL1 returns to H and the bit line BL2 returns to L.
[0056]
  Further, since the plate line PL is set to H at timing T16, the polarization state of the ferroelectric capacitor 62 is inverted again here. Subsequently, at the timing T18, the plate line PL is set to L to reverse the polarization state of the ferroelectric capacitor 61 again. At time T20, the word line W is set to L and the switches 63 and 64 in FIG.close.
[0057]
Reading and rewriting of the ferroelectric capacitors 61 and 62 described above will be described based on the hysteresis characteristics of FIG. First, with respect to the ferroelectric capacitor 61, the polarization state shifts from P1 to P2 in FIG. 3 at timings T4 to T6 (FIG. 2), and the polarization state reaches P4 at timing T8 at which rewriting is performed.
[0058]
Then, the polarization state of the ferroelectric capacitor 61 reaches P2 again from P4 through P1 at timing T12, and reaches P3 at timing T14. Thereafter, the process shifts to P4 at timing T18, and returns to P1 at timing T20.
[0059]
Next, the polarization state of the ferroelectric capacitor 62 will be described based on the hysteresis characteristic of FIG. From timing T4 to T6 (FIG. 2), the polarization state slightly shifts from P3 in FIG. 3 toward P2 along the broken line, and at timing T8 (FIG. 2), the polarization state returns to P3.
[0060]
Then, the polarization state of the ferroelectric capacitor 62 reaches P4 from P3 at timing T14, and reaches P2 via P1 at timing T16. Then, it returns to P3 at timing T18.
[0061]
As described above, in this embodiment, the polarization state of the ferroelectric capacitor 61 has at least one round of hysteresis characteristics (in this embodiment, two rounds), and the polarization state of the ferroelectric capacitor 62 also has at least hysteresis characteristics. One round (one round in this embodiment) is made.
[0062]
For this reason, the risk that the polarization state of the ferroelectric capacitor 62 is maintained for a long time can be reduced, and the occurrence of the imprint effect due to the polarization state of the ferroelectric capacitor 62 can be reliably suppressed. it can. Further, since the polarization state of the ferroelectric capacitor 62 only needs to be reversed once and then returned to the original polarization state, the occurrence of the imprint effect can be easily suppressed.
[0063]
Further, the polarization state of the ferroelectric capacitor 62 is reversed at the time of reading and rewriting of stored data, which has been conventionally performed, and only the reversal processing is performed independently of the reading and rewriting. Therefore, the control of the process is easy and efficient.
[0064]
In the present embodiment, a two-transistor two-capacitor type ferroelectric memory is exemplified, but the present invention can also be applied to other types of semiconductor memories, for example, a one-transistor one-capacitor type ferroelectric memory. In the present embodiment, the ferroelectric memory is exemplified, but the present invention can also be applied to, for example, a ferroelectric transistor. Furthermore, the present invention can be applied to other semiconductor memories that do not use a ferroelectric substance.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of ferroelectric capacitors 61 and 62, a sense amplifier 2, and the like.
FIG. 2 is a timing chart at the time of reading stored data stored in ferroelectric capacitors 61 and 62;
FIG. 3 is a diagram showing hysteresis characteristics representing a relationship between a voltage and a polarization state related to a ferroelectric capacitor.
FIG. 4 is a circuit diagram of a ferroelectric capacitor.
FIG. 5 is a conventional timing chart at the time of reading stored data stored in ferroelectric capacitors 61 and 62;
[Explanation of symbols]
2 Sense amplifier
11, 12, 13, 14
·····switch
21, 22 ... AND circuit
23, 24... Inversion circuit
61, 62 ... Ferroelectric capacitors

Claims (4)

  A ferroelectric capacitor that stores first data or second data corresponding to each state by holding a first polarization state or a second polarization state opposite to the first polarization state;
  A plate line for writing first data or second data, connected to one end of the ferroelectric capacitor;
  A bit line connected to the other end of the ferroelectric capacitor for reading out the first data or the second data;
  A control unit for controlling storage processing or readout processing to the ferroelectric capacitor;
  An inverting circuit that amplifies and distributes the bit line voltage, and amplifies and distributes the bit line voltage by the inverting circuit based on the sense amplifier signal from the control unit, and the bit based on the switching signal from the control unit A sense amplifier having an AND circuit for switching the voltage of the line;
  A method for accessing a semiconductor device comprising:
  The control unit outputs a sense amplifier signal to the sense amplifier,
  The sense amplifier operates an inverting circuit based on the signal from the AND circuit that receives the sense amplifier signal, and amplifies the voltage of the bit line according to the electric charge discharged from the ferroelectric capacitor toward the bit line. Sort and hold
  The control unit reads first data or second data from the bit line,
  For the ferroelectric capacitor storing the first data in which the polarization state is reversed upon reading, the polarization state is reversed again to return to the original state,
  When the control unit provides a switching signal to the sense amplifier, the AND circuit switches the voltage of the bit line so as to reverse the polarization state of the ferroelectric capacitor storing the first data,
  The controller further applies a voltage to the plate line so as to reverse the polarization state of the ferroelectric capacitor storing the second data,
  When the control unit gives a switching signal to the sense amplifier, the AND circuit switches the bit line voltage so as to invert the polarization state of the ferroelectric capacitor storing the second data again,
  The control unit applies a voltage to the plate line to reverse the polarization state of the ferroelectric capacitor storing the first data again.
  A method for accessing a semiconductor device.   The method for accessing a semiconductor device according to claim 1,
  There are two ferroelectric capacitors,
  One ferroelectric capacitor stores the first data by holding the first polarization state, and the other one ferroelectric capacitor stores the second data by holding the second polarization state.
  A method for accessing a semiconductor device.   A ferroelectric capacitor that stores first data or second data corresponding to each state by holding a first polarization state or a second polarization state opposite to the first polarization state;
  A plate line for writing first data or second data, connected to one end of the ferroelectric capacitor;
  A bit line connected to the other end of the ferroelectric capacitor for reading out the first data or the second data;
  A control unit for controlling storage processing or readout processing to the ferroelectric capacitor;
  An inverting circuit that amplifies and distributes the bit line voltage and amplifies and holds the bit line voltage by the inverting circuit based on the sense amplifier signal from the control unit. An AND circuit for switching the voltage of the bit line based on the switching signal from
  A semiconductor device comprising:
  The control unit outputs a sense amplifier signal to the sense amplifier,
  The sense amplifier operates an inverting circuit based on the signal from the AND circuit that receives the sense amplifier signal, and amplifies the voltage of the bit line according to the electric charge discharged from the ferroelectric capacitor toward the bit line. Sort and hold
  The control unit reads first data or second data from the bit line,
  For the ferroelectric capacitor storing the first data in which the polarization state is reversed at the time of reading, the polarization state is reversed again to return to the original state,
  When the control unit provides a switching signal to the sense amplifier, the AND circuit switches the voltage of the bit line so as to reverse the polarization state of the ferroelectric capacitor storing the first data,
  The controller further applies a voltage to the plate line so as to reverse the polarization state of the ferroelectric capacitor storing the second data,
  When the control unit provides a switching signal to the sense amplifier, the AND circuit switches the voltage of the bit line so as to reverse the polarization state of the ferroelectric capacitor storing the second data again.
  The controller is configured to apply a voltage to the plate line so as to reverse the polarization state of the ferroelectric capacitor storing the first data again.
  A semiconductor device.   The semiconductor device according to claim 3.
  There are two ferroelectric capacitors,
  One ferroelectric capacitor stores the first data by holding the first polarization state, and the other one ferroelectric capacitor stores the second data by holding the second polarization state.
  A semiconductor device.

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