JPH0541502A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To eliminate a need for a dummy cell and to perform a high-speed readout operation by a method wherein a capacitor which uses a ferroelectric film as a capacitor insulating film is installed. CONSTITUTION:One memory cell is constituted of one capacitor and two MOS transistors 4, 5; a ferroelectric film is used as a capacitor insulating film 8. In addition, a bit line 1, an inverted bit line and a word line 3 are provided. Different potentials are applied on capacitor electrodes 6, 7 through the MOS transistor 4, 5; '0' is distinguished from '1' by the direction of a polarization generated by the capacitor insulating film 8. Then, a residual electric charge generated when '1' and '0' are written is utilized for a readout operation. When the potential difference between the bit line 1 and the inverted bit line 2 is sensed, it is possible to directly perform the readout operation without the intermediary of a dummy cell. Thereby, the readout operation can be performed at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art Conventionally, a memory cell using a ferroelectric film as a capacitor insulating film is composed of one MOS transistor and one capacitor. FIG. 4 shows polarization characteristics at the time of writing and reading in the memory cell composed of one transistor and one capacitor. 4 is MOS
Transistors, 6 and 7 are capacitor electrodes, and 8 is a capacitor insulating film.

The polarization state of the capacitor insulating film 8 during writing will be described. First, the capacitor electrode 7 side is Vc
The potential is set to c / 2 (V). Next, the capacitor electrode 6
The side is Vcc (V) (when writing "1") or 0
(V) (when writing "0"). At this time,
As shown in (a) and (b), the residual polarization charge is accumulated in the capacitor in the state where the polarization directions are opposite between when "1" is written and when "0" is written. Become.

Next, the polarization state of the capacitor insulating film 8 at the time of reading will be described. First, the capacitor electrode 6 side is set to Vcc (V). When reading "1",
As shown in (a) and (c), since the polarization direction of the capacitor is not inverted, I = (Ps-Pr) / Δt (Ps is a saturated polarization charge, Pr is a remanent polarization charge, and Δt is a reversal speed. ) The electric current of the magnitude flows. On the other hand, when "0" is read, the direction of polarization of the capacitor is reversed as shown in FIGS.
= (2Pr + (Ps−Pr)) / Δt = (Pr + Ps)
/ Δt, and the flowing current is larger than that when reading “1”. That is, depending on the magnitude of the flowing current,
It is possible to determine whether to read "1" or "0".

[0005]

As described above, when one memory cell is composed of one capacitor and one transistor, a dummy cell is necessary in the read operation to determine the magnitude of the current amount. Therefore, the reading speed is suppressed.

Therefore, the present invention eliminates the need for dummy cells,
An object is to provide a semiconductor memory device capable of high-speed reading.

[0007]

In the semiconductor memory device of the present invention, one memory cell is composed of one capacitor and two MOS transistors, and the capacitor using a ferroelectric film as a capacitor insulating film is provided. It is characterized by

[0008]

According to the present invention, by sensing the potential difference between the bit line and the inverted bit line, it is possible to directly perform the read operation without using the dummy cell.

[0009]

The present invention will be described in detail below based on an example.

FIG. 1 shows a memory cell circuit configuration of an embodiment of the present invention, FIGS. 2A and 2B show polarization state diagrams at the time of a write operation of the embodiment of the present invention, and FIG. c),
FIG. 2D shows a state of the residual charge at the time of the read operation using the residual charge according to the embodiment of the present invention, and FIGS.
Indicates the polarization direction during a read operation using the same polarization inversion. 1 is a bit line, 2 is an inverted bit line, 3 is a word line,
Reference numerals 4 and 5 are MOS transistors, 6 and 7 are capacitor electrodes, and 8 is a capacitor insulating film using a ferroelectric film (for example, a PZT film or the like).

Next, the write operation of "1" and "0" will be described. First, when writing "1", the bit line 1 is set to Vcc (V) and the inverted bit line 2 is set to 0 (V). Due to the residual charge generated at this time, the polarization direction is from the capacitor electrode 7 to the capacitor electrode 6 as shown in FIG. When writing "0", the bit line 1 is set to 0 (V) and the inverted bit line 2 is set to Vcc (V). Due to the residual charge generated at this time, the polarization direction changes from the capacitor electrode 6 to the capacitor electrode 7 as shown in FIG.
The direction is toward.

Next, the read operation using the residual charge will be described. First, bit line 1 and inverted bit line 2
To the same potential (Vcc / 2 (V)). Next, when the word line 3 is turned on, as shown in FIGS. 2C and 2D, ± Vr = ± Qr / C (±) on the bit line 1 and the inverted bit line 2 depending on the residual charge. Qr represents a residual charge, and C represents a capacitance of the bit line 1 etc.). After that, by directly performing the sensing operation, depending on the direction of polarization,
It is possible to read "1" and "0". The initial potentials of the bit line 1 and the inverted bit line 2 at the time of reading are Vcc
The value is not limited to / 2 (V) and may be set to any value as long as it can be sensed.

Next, as another embodiment, a read operation using polarization inversion will be described.

Bit line 1 is set to Vcc / 2 (V) or 0
(V) and set the inverted bit line 2 to Vcc (V) or Vcc
After setting it to / 2 (V), the word line 3 is turned on. Figure 3
(A) and (b) show hysteresis characteristics in the operation of reading "1" and "0" by utilizing polarization inversion. As shown in FIG. 3A, when "1" is read, polarization inversion occurs and the charge amount changes. On the other hand, when "0" is read, polarization inversion does not occur and the charge amount hardly changes, as shown in FIG. Therefore, when the polarization reversal is used as described above, it is possible to judge "1" or "0" by the change in the current or the potential caused by the change in the charge amount.

The potentials set on the bit line 1 and the inverted bit line 2 at the time of reading are not limited to those in the present embodiment.
It is possible if polarization inversion occurs when one of "1" and "0" is read and polarization inversion does not occur when the other is read.

[0016]

As described above in detail, by using the present invention, the read operation can be speeded up by directly performing the sensing operation without using the dummy cell.
Further, by using the ferroelectric film for the capacitor insulating film, a non-volatile semiconductor memory device that does not require refreshing can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a memory cell according to an embodiment of the present invention.

FIG. 2 is a state diagram of a capacitor during writing and reading according to an embodiment of the present invention.

FIG. 3 is a hysteresis characteristic diagram at the time of reading when the polarization inversion in FIG. 2 is used.

FIG. 4 is a state diagram of a capacitor of a memory cell using a conventional ferroelectric film.

[Explanation of symbols]

 1 bit line 2 inverted bit line 3 word line 4,5 MOS transistor 6,7 capacitor electrode 8 capacitor insulating film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Keizo Sakiyama 22-22 Nagaike-cho, Abeno-ku, Osaka

Claims (1)

[Claims] 1. A capacitor and a MOS transistor 2
A semiconductor memory device comprising a memory cell and a memory cell, wherein the capacitor is provided with a ferroelectric film as a capacitor insulating film.