JP3360418B2 - Ferroelectric semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric semiconductor memory device using a ferroelectric film as a charge storage means for a memory cell.

[0001]

2. Description of the Related Art A semiconductor memory device is used as a general-purpose memory in many information devices such as a large computer, a mainframe of a minicomputer class, and a personal computer. In particular, a dynamic random access memory (DRAM) is used.
ss Memory) is characterized by high integration, high yield, and low power consumption, and its demand is great because of its low price. A DRAM is a volatile memory in which data is stored in a capacitor formed of an insulating film such as SiO ₂ by storing electric charges and data is easily lost in a short time due to leakage or the like. As a result, a so-called refresh operation is required in which data is read out to the bit line BL at regular intervals and is reinforced and stored again. When the power is turned off, the stored contents are erased. Recently, instead of insulating films such as SiO ₂ , ferroelectric films such as PbTiO ₃ , PZT (Pb (Zr _0.4 Ti _0.6 ) O ₃ ) or PLZT ((Pb, La) (Zr, Ti) O ₃ ) A memory cell (hereinafter, also referred to as FRAM) which can be used as a non-volatile memory in addition to a function as a DRAM using a ferroelectric capacitor composed of the following has been proposed. FIG. 7 is a configuration diagram of an FRAM cell used in a conventional FRAM. As shown in FIG. 7, an FRAM cell used in a conventional FRAM includes an nMOS transistor Tr and a ferroelectric capacitor FC (hereinafter simply referred to as F
C). nMOS transistor Tr
Has a drain (D) connected to the bit line BL, a gate (G) connected to the word line WL, and a source (S) connected to one electrode of the ferroelectric capacitor FC. The other electrode of the capacitor FC is connected to the plate line PL.

FIG. 8 shows the voltage (V) applied to the ferroelectric capacitor FC and the stored charge (Q) stored in the FC when the threshold voltage Vth of the nMOS transistor Tr shown in FIG. 7 is ignored. Is a hysteresis loop showing the relationship In the FRAM cell shown in FIG. 7, when writing "1", "Vcc" is applied to the ferroelectric capacitor FC. "Vcc" at both ends of ferroelectric capacitor FC
Is applied, the polarization state of the ferroelectric capacitor FC becomes the polarization state "P1" shown in FIG. Then, when the voltage applied to the ferroelectric capacitor FC becomes “0”, the polarization state of the ferroelectric capacitor FC becomes “P2” shown in FIG. On the other hand, when writing "0", a voltage of "-Vcc" is applied to the ferroelectric capacitor FC. As a result, the polarization state of the ferroelectric capacitor FC becomes "P3" shown in FIG. Then, when the voltage applied to the ferroelectric capacitor FC becomes “0”, the polarization state of the ferroelectric capacitor FC becomes “P4” shown in FIG.

When reading stored information from the FRAM cell shown in FIG. 7, a voltage "-V" is applied to the ferroelectric capacitor FC.
cc ". The voltage "-" is applied to the ferroelectric capacitor FC.
When “Vcc” is applied, the polarization state of the ferroelectric capacitor FC changes along the hysteresis loop “loop” shown in FIG. 8, and finally becomes “P3”. At this time, FRA
When “1” is stored in the M cell, the polarization state of FC changes from “P2” to “P3”, and the switch storage charge SC is released to the bit line BL. On the other hand, when “0” is stored in the FRAM cell, the polarization state of FC changes from “P4” to “P3”, and the unswitch accumulated charge USC is discharged to the bit line BL.

In the FRAM cell shown in FIG. 7, in a read operation, for example, a signal charge corresponding to the difference between the switch charge SC and the unswitch charge USC is detected by a sense amplifier, so that "1" is stored in the FRAM cell. Alternatively, it is determined which of “0” is stored. Therefore, in the FRAM cell shown in FIG. 7, the larger the difference between the switch accumulated charge SC and the unswitch accumulated charge USC, the higher the sensitivity and speed of the reading operation, and the easier the reading operation.

[0005]

However, the conventional FRA
In M, the voltage “Vcc” applied to the bit line BL is not actually applied to the ferroelectric capacitor FC shown in FIG. 7 when writing “1”, and the voltage “Vcc− Vth "was applied. Here, "Vt
"h" is a threshold voltage of the nMOS transistor Tr.
Therefore, in the conventional FRAM, the switch storage charge SC actually becomes as shown in FIG. 9, and is smaller than the case where the threshold voltage of the nMOS transistor Tr described with reference to FIG. 8 is not considered.

The reason will be described below with reference to FIGS. 7 and 9. FIG. 9 is a hysteresis diagram showing the relationship between the voltage (V) applied to the ferroelectric capacitor FC shown in FIG. 7 and the stored charge (Q) stored in the FC when the threshold voltage of the nMOS transistor Tr is considered. It is a loop. Loop (0) shown in FIG. 9 is a hysteresis loop of the ferroelectric capacitor FC in the write operation of “0”. Loop (1) shown in FIG. 9 is a hysteresis loop of the ferroelectric capacitor FC in the write operation and the read operation of “1”.

In the FRAM cell shown in FIG. 7, a voltage is supplied from the source of the nMOS transistor Tr to one electrode of the ferroelectric capacitor FC. FRAM shown in FIG.
In the cell, when writing “1”, a voltage “Vcc” is applied to the bit line BL and the word line WL, and the plate line P
A voltage “0” is applied to L. nMOS transistor Tr
Becomes conductive when a voltage equal to or higher than the threshold voltage “Vth” is generated between the gate and the source. Therefore, the maximum value of the source voltage of the nMOS transistor Tr is “Vcc−Vth”.

Therefore, when "1" is written, the voltage "Vcc-Vth" is applied to the ferroelectric capacitor FC of the FRAM cell, and the polarization state of FC is shown in FIG. 9 in the write operation and the read operation. It changes along the hysteresis loop loop (1). At this time, since “Vcc” is larger than “Vcc−Vth”, the hysteresis loop loop (1) shown in FIG. 9 is located inside the theoretical hysteresis loop loop shown in FIG. The charge SC is smaller than the switch accumulation charge SC shown in FIG.

On the other hand, in the FRAM cell shown in FIG.
When writing “0”, the voltage of the bit line BL is “0”, and the voltage “Vc” is applied to the plate line PL and the word line WL.
c "is applied. Therefore, the voltage “−Vcc” is applied to the ferroelectric capacitor FC, and the ferroelectric capacitor F
The polarization state of C changes along the hysteresis loop loop (0) shown in FIG. 9 in the write operation and the read operation. The hysteresis loop loop shown in FIG.
(0) is the theoretical hysteresis loop loo shown in FIG.
equal to p. Therefore, the unswitch accumulated charge USC shown in FIG. 9 becomes equal to the unswitch accumulated charge USC shown in FIG.

Therefore, in the FRAM, actually, the difference between the switch charge SC and the unswitch charge USC is smaller than that described with reference to FIG. As a result, it is difficult to detect the signal charge using the sense amplifier during the actual reading operation, and it may not be possible to increase the sensitivity and speed of the reading operation.

The present invention has been made in view of the above-mentioned problems of the prior art, and provides a ferroelectric semiconductor memory device capable of improving the sensitivity and speeding up reading of a memory cell using a ferroelectric film. The purpose is to:

[0012]

In order to solve the above-mentioned problems of the prior art and achieve the above-mentioned object, a ferroelectric memory device according to the present invention is configured such that voltages having different polarities are selectively applied. The polarity is different between the ferroelectric film provided for each of the plurality of memory cells arranged in a matrix and the ferroelectric film, which stores information according to a polarization state due to the applied voltage. A pMOS having a source connected to one electrode of the ferroelectric film by selectively applying a voltage;
A transistor, a bit line connected to the drain of the pMOS transistor, a word line connected to the gate of the pMOS transistor, and a plate connected to the other electrode of the ferroelectric film. When writing data “1” to the dielectric film, in a state where a reference voltage lower than a threshold voltage of the pMOS transistor is applied to the word line and a reference voltage higher than the threshold voltage is applied to the bit line, The voltage applied to the plate line is switched from a reference voltage higher than the threshold voltage to a reference voltage lower than the threshold voltage.

In the ferroelectric memory device according to the present invention, preferably, when reading data stored in the ferroelectric film, a reference voltage lower than the threshold voltage is applied to the word line, A reference voltage higher than the threshold voltage is applied to the line. Further, the ferroelectric storage device of the present invention,
Preferably, when writing data “0” to the ferroelectric film, applying a reference voltage lower than the threshold voltage to the word line, applying a reference voltage lower than the threshold voltage to the bit line, In a state where a reference voltage higher than the threshold voltage is applied to the plate line, a voltage applied to the bit line is switched from a reference voltage higher than the threshold voltage to a reference voltage lower than the threshold voltage.

[0014]

In the ferroelectric semiconductor memory device of the present invention, for example, in a write operation, the reference voltage "0" is applied to the gate of the pMOS transistor from the word line, and the drain / source is conductive. First, the operation when data "1" is written in the ferroelectric semiconductor memory device of the present invention will be described. The reference voltage "Vcc" is applied to the drain from the bit line, and the voltage of the source is the reference voltage "Vcc". In this state, the voltage applied to the plate line is changed to the reference voltage “Vcc”.
, The voltage "Vcc" (first voltage) corresponding to the difference between the voltage "Vcc" from the source and the voltage "0" from the plate line is applied to the ferroelectric film. Applied. That is, in the ferroelectric semiconductor memory device of the present invention, by using the pMOS transistor, the voltage of the reference voltage “Vcc” from the bit line can be directly generated at the source, and the voltage “Vc” is applied to the ferroelectric film.
c "can be applied.

When a voltage "Vcc" is applied, the ferroelectric film polarizes in response to the voltage "Vcc", and then changes along a first hysteresis loop. When the voltage applied to the ferroelectric film decreases (eg, becomes “0”), the ferroelectric film enters a polarization state according to the first hysteresis loop.

Next, an operation when data "0" is written in the ferroelectric semiconductor memory device of the present invention will be described. The reference voltage "Vcc" is applied to the drain from the bit line.
Is applied, and the source voltage is equal to the reference voltage “Vcc”.
It has become. The voltage applied to the plate line is the reference voltage “Vcc”. In this state, when the voltage applied to the bit line falls from the reference voltage “Vcc” to the reference voltage “0”, the source voltage also changes to the reference voltage “Vc”.
“c” falls toward “0”. When the source voltage reaches the threshold voltage “Vth” of the pMOS transistor in the course of the fall, the source / sole becomes non-conductive, and the source voltage becomes the threshold voltage “Vt”.
h ”.

As a result, the voltage “Vth” from the source and the voltage “Vcc” from the plate line are applied to the ferroelectric film.
And a voltage “Vth−Vcc” (second voltage) corresponding to the difference between the two. At this time, the voltage “Vth−Vcc”
Has a polarity different from the voltage “Vcc” (first voltage), and its absolute value is smaller than the voltage “Vcc”. Thus, in the ferroelectric semiconductor memory device of the present invention, when writing “0”, the voltage “0” is applied to the ferroelectric film from the bit line.
“−Vcc” corresponding to the difference between the voltage “Vcc” from the plate line and the voltage “Vth” is not applied as it is,
-Vcc "is applied. The ferroelectric film has a voltage “Vth
When "-Vcc" is applied, it polarizes accordingly and then changes along the second hysteresis loop. When the voltage applied to the ferroelectric film decreases (for example, becomes “0”), the ferroelectric film enters a polarization state according to the second hysteresis loop.

In the ferroelectric semiconductor memory device of the present invention, in the reading operation, the voltage applied to the plate line is changed from the reference voltage "0" while the reference voltage "0" is applied to the gate and the bit line of the pMOS transistor. The voltage is raised to the reference voltage “Vcc”. As a result, a voltage "-Vcc" is applied to the ferroelectric film, and the accumulated charge corresponding to the polarization state is released from the ferroelectric film to the bit line, and the released charge is amplified using, for example, a sense amplifier. Then, the polarization state of the ferroelectric film is determined, and the stored information is read based on the determination result.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An FRAM according to an embodiment of the ferroelectric semiconductor memory device of the present invention will be described below. First Embodiment FIG. 1 is a configuration diagram of an FRAM cell used in the FRAM of the present embodiment. In the FRAM of the present embodiment, the FRAM cells shown in FIG. 1 are arranged in a matrix. As shown in FIG. 1, an FRAM used in the FRAM of the present embodiment
The cells include pMOS transistors Tr1 and Tr2 and ferroelectric capacitors FC1 and FC2 (hereinafter simply referred to as FC1 and FC2).
2) to form a memory cell. in this way,
Since a memory cell is configured using the two ferroelectric capacitors FC1 and FC2, the information stored in FC1 and FC2 is opposite to each other. pMOS transistor Tr1
Has a drain (D) connected to the bit line BL1, a gate (G) connected to the word line WL, and a source (S) connected to one electrode of the ferroelectric capacitor FC1. The other electrode of capacitor FC1 is connected to plate line PL. Also, the pMOS transistor Tr2
Has a drain (D) connected to the bit line BL0, a gate (G) connected to the word line WL, and a source (S) connected to one electrode of the ferroelectric capacitor FC2. The other electrode of the capacitor FC2 is connected to the plate line PL.

The voltages applied to word lines WL and plate lines PL are controlled by a row decoder. Further, the voltages applied to the bit lines BL1 and BL0 are controlled by the write circuit. $ WE which is binary data is written in the write circuit.
A signal and an I / O signal are input.

An example of a write operation of the FRAM cell shown in FIG. 1 will be described. FIG. 2 shows the voltage (V) applied to the ferroelectric capacitors FC1 and FC2 shown in FIG.
It is a hysteresis loop showing the relationship with the stored charge (Q) stored in FC2. FIG. 3 shows a word line WL and a plate line P in the write operation of the FRAM cell shown in FIG.
5 is a timing chart of signals applied to L and bit lines BL1 and BL0, where the horizontal axis indicates time and the vertical axis indicates voltage.

First, the data "is stored in the FRAM cell shown in FIG.
The case where 1 "is written will be described. As shown in FIG. 3, the voltage applied to the word line WL varies in the periods T1 to T3.
Is "0". The voltage applied to the bit line BL1 is “Vcc” in the periods T0 to T3.
The voltage applied to the bit line BL0 is “Vcc” in the periods T0 and T1, and “0” in the periods T2 and T3.
It is.

First, in the period T0 shown in FIG. 3, the voltage applied to the word line WL, the bit lines BL1 and BL0 and the plate line PL is "Vcc".
The drain and source of the transistors Tr1 and Tr2 are non-conductive.

Next, in a period T1 shown in FIG. 3, the word line WL falls from "Vcc" to "0". As a result, a voltage equal to or higher than the threshold voltage "Vth" is generated between the gate and the source of the pMOS transistors Tr1 and Tr2, and the drain and the source are turned on. At this time, since the voltage “Vcc” is applied to the bit lines BL1 and BL0, the source voltage of the pMOS transistors Tr1 and Tr2 becomes “Vcc”. Here, since the voltage of the plate line PL is “Vcc”, a voltage “0” is applied to both FC1 and FC2. At this time, FC1 and FC2 are in a polarization state according to the data stored before. For example, when data “0” is stored in the FRAM cell before, the polarization state of FC1 is “P11” shown in FIG. 2 and the polarization state of FC2 is “P1”.
0 ".

Next, in a period T2 shown in FIG. 3, the voltage of the bit line BL0 falls from "Vcc" to "0". While the voltage of the bit line BL0 falls from “Vcc” to “0”, the voltage of the source of the pMOS transistor Tr2 also falls from “Vcc” to “0”. And
When the source voltage of the pMOS transistor Tr falls below the threshold voltage “Vth”, the pMOS transistor Tr
Since the connection between the drain and source of No. 2 becomes non-conductive,
The source voltage of the pMOS transistor Tr2 is "Vt
h ". At this time, the voltage of the plate line PL is “Vc
c ”, FC2 has“-(Vcc−Vth) ”
Is applied. Thereby, FC2 shown in FIG.
Is changed to "P12" shown in FIG. 2, and "0" is stored in FC2. As described above, in the period T2,
Since “− (Vcc−Vth)” is applied to FC2,
Thereafter, the polarization state of FC2 changes according to the hysteresis loop loop (0) shown in FIG.

On the other hand, in the period T2 shown in FIG. 3, the state of the word line WL, the plate lines PL and BL1 is not different from that in the period T1, and the state in the period T1 is kept as it is in FC1 shown in FIG. That is, p shown in FIG.
The voltage of the source of the MOS transistor Tr1 is “Vcc”
, The voltage applied to FC1 remains “0”, and the polarization state of FC1 is maintained at “P11” shown in FIG.

Next, in a period T3 shown in FIG. 3, the voltage of the plate line PL falls from "Vcc" to "0". At this time, the pMOS transistor Tr1 in the period T2
Is in a conductive state between the drain and the source, and since the voltage of the source is “Vcc”, “Vcc” is applied to FC1. As a result, the polarization state of FC1 shown in FIG. 1 becomes “P13” shown in FIG. 2, and “1” is stored in FC1.

As described above, in the period T3, "Vcc" is applied to FC1, and thereafter, the polarization state of FC1 changes according to the hysteresis loop loop (1) shown in FIG. The voltage “Vcc” is equal to the voltage “(Vcc−Vt
h) ”, the hysteresis loop loo
p (1) is located so as to surround the hysteresis loop loop (0). On the other hand, in the period T3, since the plate line PL falls from “Vcc” to “0”, the voltage applied to FC2 becomes “0”, and as shown in FIG.
The polarization state of C2 changes from “P12” to “P11” along the hysteresis loop loop (0).

As described above, the FRAM cell has "
When "1" is written, the polarization states of FC1 and FC2 change according to loop (1) and loop (0), respectively. That is, when the voltage applied to FC1 and FC2 becomes "0" However, the polarization states of FC1 and FC2 are respectively "P10" and "P11" shown in FIG.
become. As a result, "1" is stored in FC1,
“0” is stored in FC2. On the other hand, when writing "0" to the FRAM cell, the above-described operation is performed in reverse for FC1 and FC2 shown in FIG. 1, and "0" is stored in FC1, and "1" is stored in FC2. You.

Next, an operation example in the case of reading the data "1" written by the operation example shown in FIG. 3 will be described. FIG. 4 shows a case where the data written by the operation example shown in FIG.
5 is a timing chart of signals applied to L, the plate line PL, and the bit lines BL1 and BL0, where the horizontal axis indicates time and the vertical axis indicates voltage.

In a period T0 'shown in FIG.
Falls from “Vcc” to “0”, and the drains of the pMOS transistors Tr1 and Tr2
The source becomes conductive. At this time, the plate line PL
Is "0" and the bit lines BL1 and B1
The voltages applied to L0 are both “0”. Therefore, F
The voltages applied to C1 and FC2 are both “0”. Therefore, the polarization states of FC1 and FC2 are shown in FIG.
"P10" and "P11".

Next, in a period T1 'shown in FIG.
Similarly to the case of 0 ′, the drain and source of the pMOS transistors Tr1 and Tr2 shown in FIG. 1 are in a conductive state, and the voltage applied to the plate line PL changes from “0” to “V”.
cc ". As a result, the polarization state of FC1 becomes “P” in the hysteresis loop loop (1) shown in FIG.
14 ", and the polarization state of FC2 is" P12 "in the hysteresis loop loop (0). At this time, FC
1 and FC2 are stored in the bit line BL, respectively.
1, BL0, and the bit lines BL1, BL
At 0, a potential difference (voltage) of the difference between the discharged charges is generated, thereby activating the sense amplifier and reading information.

Assuming that “Vcc” is the same voltage, FIG.
Is larger than the conventional switch charge SC shown in FIG. Further, the unswitch accumulated charge USC shown in FIG. 2 is smaller than the conventional unswitch accumulated charge USC shown in FIG.

Next, in a period T2 'shown in FIG. 4, the voltage applied to the plate line PL falls from "Vcc" to "0". At this time, the voltage of the bit line BL1 is “Vc
c ”, and the voltage of the bit line BL0 is“ 0 ”. Accordingly, the voltage “Vcc” is applied to FC1, and the polarization state of FC1 is changed to the hysteresis loop “loop” shown in FIG.
The state changes from “P14” to “P13” along (1).
Further, a voltage “0” is applied to FC2, and the polarization state changes from “P12” to “P11” along the hysteresis loop loop (0) shown in FIG. By the above operation, “1” is rewritten to FC1 and “1” is written to FC2.
0 "is rewritten, that is, data is rewritten in the period T2 '.

Next, in a period T3 'shown in FIG. 14, the voltage applied to the word line WL rises from "0" to "Vcc". As a result, the drains of FC1 and FC2 /
The sources become non-conductive, and the polarization states of FC1 and FC2 finally become "P10" and "P1" shown in FIG.
1 ".

The operation of writing data "1" to the FRAM cell shown in FIG. 1 and reading the data has been described above.
The same can be done by reversing all the voltages applied to 1 and FC2.

As described above, according to the FRAM of the present embodiment, compared with the conventional FRAM described with reference to FIG. 9, the switch storage charge SC and the unswitched unswitched storage charge USC can be reduced. it can. As a result, according to the FRAM of the present embodiment, the signal charge corresponding to the difference between the switch charge SC and the unswitch charge USC is larger than that of the conventional FRAM described with reference to FIG. It will be easier. Therefore, according to the FRAM of the present embodiment, it is possible to increase the sensitivity and speed of the reading operation. Further, according to the FRAM of the present embodiment, since the signal charge can be increased, the reference voltage such as “Vcc” can be reduced.

Second Embodiment The FRAM of this embodiment has the same configuration as that of the FRAM according to the first embodiment shown in FIG. 1, but the signal applied to the bit line BL0 in the write operation is related to the first embodiment. Different from FRAM. FIG. 5 is a timing chart of signals applied to the word line WL, the plate line PL, and the bit lines BL1 and BL0 in the write operation in the FRAM of the present embodiment. The horizontal axis indicates time, and the vertical axis indicates voltage. .

As shown in FIG. 5, in the FRAM of this embodiment, the voltage applied to the bit line BL0 is always "0", and during the period T2 ', the pMOS transistor T
The voltage of the source of r2 becomes “0” to “Vth”, and FC2
2, a voltage of “−Vcc” to “− (Vcc−Vth)” is applied. As a result, "0" is written to FC2. Therefore, in this embodiment, in FIG.
2 is a hysteresis loop loo
It is located between p (0) and the hysteresis loop loop (1).

In the FRAM of this embodiment, the operation of FC1 is the same as that of the first embodiment.

In the FRAM of the present embodiment, the unswitch accumulated charge USC is equal to that in the FRAM of the first embodiment when the source voltage of the pMOS transistor Tr2 is the threshold voltage "Vth". When the voltage of the source of the transistor Tr2 is “0”, unlike the first embodiment, the unswitched accumulated charge USC
Cannot be reduced, and only the switch storage charge SC is increased.

In the FRAM of this embodiment, the difference between the switch storage charge SC and the unswitch storage charge USC can be increased by making the switch storage charge SC larger than in the prior art, and reading becomes easier. Therefore, even with the FRAM of this embodiment, it is possible to increase the sensitivity and speed of the reading operation. Further, according to the FRAM of the present embodiment, since the signal charge can be increased, the reference voltage such as “Vcc” can be reduced.

The ferroelectric semiconductor memory device of the present invention is not limited to the above embodiment. For example, in the above-described embodiment, an FRAM cell including two pMOS transistors, a ferroelectric capacitor, and a bit line has been illustrated as shown in FIG. 1, but as shown in FIG. , A ferroelectric capacitor and a bit line may be used.

Further, the ferroelectric semiconductor memory device of the present invention can be applied not only to the FRAM according to the above-described embodiment but also to other memory devices and the like which detect a reversal current by using a ferroelectric film as a capacitor. .

[0045]

As described above, according to the ferroelectric semiconductor memory device of the present invention, the signal charge corresponding to the difference between the switch accumulated charge and the unswitch accumulated charge used in the read operation is increased. Can be. Therefore, when data is read using charges accumulated in the ferroelectric film, the sensitivity and speed of the reading operation can be increased, and the reading operation can be facilitated. Further, according to the ferroelectric semiconductor memory device of the present invention, the voltage can be reduced.

[Brief description of the drawings]

FIG. 1 is an FRAM according to a first embodiment of the present invention;
FIG. 2 is a configuration diagram of an FRAM cell used in the first embodiment.

FIG. 2 is a graph showing accumulated charges (Q) -voltages (V) of ferroelectric capacitors FC1 and FC2 of the FRAM cell shown in FIG. 1;
It is a graph which shows a characteristic curve.

FIG. 3 is a timing chart of signals applied to a word line WL, a plate line PL, and bit lines BL1 and BL0 in a write operation of the FRAM cell shown in FIG.

FIG. 4 is a timing chart of signals applied to a word line WL, a plate line PL, and bit lines BL1 and BL0 in a read operation of the FRAM cell shown in FIG.

FIG. 5 is an FRAM according to a second embodiment of the present invention;
Word line WL and plate line PL
4 is a timing chart of signals applied to bit lines BL1 and BL0.

FIG. 6 is a diagram for explaining another example of the FRAM cell used in the FRAM according to the embodiment of the present invention.

FIG. 7 is a configuration diagram of a general FRAM cell.

8 is a diagram showing the accumulated charge (Q) -voltage (V) of a ferroelectric capacitor in a case where a threshold voltage Vth between a gate and a source of an nMOS transistor is not considered in a read operation and a write operation of the FRAM cell shown in FIG. 7; FIG. 5 is a diagram showing a hysteresis loop representing a relationship with the following.

9 shows a relationship between a charge (Q) and a voltage (V) stored in a ferroelectric capacitor in consideration of a threshold voltage Vth between a gate and a source of an nMOS transistor in a read operation and a write operation of the FRAM cell shown in FIG. FIG. 5 is a diagram showing a hysteresis loop representing a relationship with the following.

[Explanation of symbols]

 FC, FC1, FC2: Ferroelectric capacitor BL1, BL0: Bit line WL: Word line PL: Plate line Tr: nMOS transistor Tr1, Tr2: pMOS transistor

Claims (3)

(57) [Claims] A voltage having a different polarity is selectively applied, information is stored in accordance with a polarization state by the applied voltage, and information is stored corresponding to each of a plurality of memory cells arranged in a matrix. A ferroelectric film, a pMOS transistor having a source connected to one electrode of the ferroelectric film by selectively applying the voltages having different polarities to the ferroelectric film, and a drain to the pMOS transistor. A bit line connected thereto; a word line connected to the gate of the pMOS transistor; and a plate connected to the other electrode of the ferroelectric film, wherein data “1” is stored in the ferroelectric film. When writing, in a state where a reference voltage lower than the threshold voltage of the pMOS transistor is applied to the word line and a reference voltage higher than the threshold voltage is applied to the bit line, The strong switch the voltage applied to the plate line to the reference voltage lower than the threshold voltage from reference voltage higher than the threshold voltage dielectric semiconductor memory device. 2. When reading data stored in the ferroelectric film, a reference voltage lower than the threshold voltage is applied to the word line, and a reference voltage higher than the threshold voltage is applied to a plate line. The ferroelectric semiconductor memory device according to claim 1. 3. When writing data "0" to the ferroelectric film, a reference voltage lower than the threshold voltage is applied to the word line, and a reference voltage lower than the threshold voltage is applied to the bit line. 2. A voltage applied to the bit line is switched from a reference voltage higher than the threshold voltage to a reference voltage lower than the threshold voltage while a reference voltage higher than the threshold voltage is applied to the plate line. 3. The ferroelectric semiconductor memory device according to 1.