JPH04228191A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To non-volatilize the high-density semiconductor integrated circuit. CONSTITUTION:A capacitor 6 consisting of a ferrodielectric body and a transistor 8 as a switch for charging and discharging this capacitor 6 are added to a DRAM sell section 11. The information stored in the capacitor 2 of the DRAM cell section 11 consisting of the volatile memory is stored at arbitrary time in the capacitor 6 consisting of the ferrodielectric body without volatilization.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit element that nonvolatizes information used in IC cards, DIP switches, and the like.

0002

2. Description of the Related Art Conventionally, as a method for making the information stored in a volatile memory non-volatile, it has been proposed in Japanese Patent Laid-Open No. 185376/1983 to make the information stored in a DRAM non-volatile. As shown in FIG. 3(a), the first transistor 33
The circuit configuration is such that a second capacitor 36 made of ferroelectric material and a line 37 are added to a DRAM cell consisting of a first capacitor 32, a word line 34, a bit line 31, and a line 35. In such a configuration, when a DRAM is used, the capacitor 36 made of ferroelectric material and the accompanying line 37 become a parasitic capacitance with respect to the grounded line, so the first capacitor 32 with a large capacitance is required. was. Therefore, a very large memory cell is essentially required, making it impractical for high integration.

[0003] In addition, NVRAM (Nonvolatile memory) shown in FIG.
e RAM) etc. have been put into practical use. In the case of NVRAM, there are those in which a floating gate type memory transistor 43 is added to the SRAM 40, and those in which a capacitor using a ferroelectric material is added instead of the floating gate type memory transistor. Note that 41 is a bit line and 42 is a word line.

0004

[Problems to be Solved by the Invention] In the case of a conventional example in which a capacitor using a ferroelectric substance is added to a DRAM, the DRAM
There was a problem in that the parasitic capacitance when used as M was extremely large. Furthermore, in the case of NVRAM, the area of the SRAM memory cell is large, which is very disadvantageous for high integration.

[0005]

[Means for Solving the Problems] In the present invention, by adding a capacitor using a ferroelectric material and a transistor as a switch for charging and discharging the capacitor, an increase in parasitic capacitance is suppressed during DRAM operation. It is suitable for high integration because it does not cause problems and the capacitance of the memory holding capacitor in the DRAM cell can be small.

[0006]

[Operation] The semiconductor integrated circuit formed as in the present invention has
The hysteresis characteristic of the polarization of a ferroelectric capacitor with respect to voltage is used as a memory. normal DR
A capacitor made of a paraelectric material used for memory storage in AM has no hysteresis with respect to the applied voltage, as shown by the broken line in Figure 4, whereas a ferroelectric material has no hysteresis with respect to the applied voltage, as shown by the solid line. Even if there is no polarization, it has polarization in the opposite direction to state 1 or state 3 in the figure. This state is called spontaneous polarization, and the ferroelectric material is in a polarized state, but when viewed as a capacitor, a charge is induced in the upper and lower electrodes to compensate for the polarization (not shown in the figure). For clarity, the direction of polarization is indicated by an arrow). For example, currently 3
If a positive voltage is applied when the polarization state is 4, the polarization state becomes state 4. At this time, when the applied voltage is returned to 0V or the applied voltage is removed, the polarization is reversed to the 1 state. The electric field required to reverse polarization is called a coercive electric field. This polarization reversal changes the polarity of the stored charge, so that the charge induced to compensate for the polarization of the ferroelectric material is discharged. When backing up DRAM,
The information in the DRAM can be made non-volatile by writing into the M cell section and the non-volatile cell section at the same time, or by moving the information stored in the DRAN cell to the non-volatile cell section. In general, the retention characteristic of floating gate nonvolatile memory is 10
However, in the case of non-volatile memory using ferroelectric materials, the potential energy required to rewrite information by polarization reversal from a certain polarization is Since the barrier height is greater than the barrier height of the silicon oxide film, it exhibits retention characteristics superior to that of floating gate nonvolatile memory.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor integrated circuit comprising a DRAM cell section and a nonvolatile cell section according to the present invention will be described in detail with reference to the drawings. Here, the state of 1 in Figure 4 is “1”
, 3 corresponds to "0". In addition, in the timing charts of the operations shown in FIGS. 5 to 12, the level of the applied signal is described as "High" and "Low," but in general, "High" is greater than the coercive electric field of the ferroelectric film used. The voltage "Low" represents a state in which no voltage is applied. Ferroelectric materials include PZT and PbT.
There are iO3, PLZT, etc., but PZT, PbTiO3 are preferred in terms of ferroelectricity and compatibility with semiconductor processes.
etc. are preferable. Hereinafter, Vc1 represents the voltage generated between the upper electrode and the lower electrode of the first capacitor 2, and Vc2 represents the voltage generated between the upper electrode and the lower electrode of the second capacitor 6.

FIG. 1 is a circuit diagram of a semiconductor integrated circuit per bit according to the present invention using a DRAM consisting of one transistor and one capacitor. bit line 1
The source of transistor 3 is connected to
The gate electrode of the transistor 3 is connected to the word line 4, the drain of the transistor 3 is connected to the upper electrode of a capacitor 2 made of a paraelectric material, and the lower electrode of the capacitor 2 is connected to the line 5. Further, the drain of the transistor 3 and the source of the transistor 8 are connected, and the drain of the transistor 8 is connected to the upper electrode of a capacitor 6 made of a ferroelectric material. Further, the circuit configuration is such that the gate electrode of the transistor 8 is connected to a line 9 and the lower electrode of the capacitor 6 is connected to a line 7.

Hereinafter, for convenience, the combination of bit line 1, word line 4, first transistor 3, first capacitor 2, and line 5 will be referred to as DRAM cell section 11, line 7, line 9, second transistor 8, and second transistor. The combination of capacitors 6 will be referred to as a nonvolatile cell section 12. Here, the line 5 is for stabilizing the potential of the electrode connected to the capacitor 2 during write and read operations for the DRAM cell section 11. The line 7 is for stabilizing the potential of the electrode connected to the capacitor 6 during write and read operations for the nonvolatile cell section 12. Line 9 is for selecting the nonvolatile cell section 12. The bit line 1 is used for writing information into the DRAM cell section 11 and the nonvolatile cell section 12 and for reading information from the DRAM cell section 11 and the nonvolatile cell section 12. The word line 4 is for selecting the DRAM cell section 11.

When used as a volatile DRAM, the second transistor 8 is turned off, the DRAM cell section 11 and the nonvolatile cell section 12 are separated, and only DRAM operations are performed. Here, the operation of DRAM is DR
A case will be described in which the state where positive charge is stored in the upper electrode of the first capacitor 2 in the AM cell is "1" information, and the state where no positive charge is stored is "0" information. It goes without saying that the presence or absence of negative charge may correspond to "0" or "1".

[0011] Also, the presence of positive charge is "1", and the absence thereof is "0".
”, the second capacitor 6 in the nonvolatile cell section must be in the “0” state, that is, the state 3 in FIG. 4, in advance. , “0”
In order to correspond to this, the second capacitor 6 of the nonvolatile cell section needs to be in the "1" state, that is, the state 1 in FIG. 4, in advance.

When backing up the storage information of the DRAM cell unit 11 to the nonvolatile cell unit 12, there are two cases: (1) writing to both the DRAM cell and the nonvolatile cell simultaneously at the time of backup; and (2) writing the contents of the DRAM cell to the nonvolatile cell unit 12. There are two actions when moving to non-volatile cells. FIG. 5 shows a timing chart for writing the "1" state when writing to both the DRAM cell and the nonvolatile cell at the same time during backup. In all subsequent timing charts, the horizontal axis shows time and the vertical axis shows voltage. Signal B is input to bit line 1 at time t1, signal W is input to word line 4 at time t2, and signal L1 is input to line 9 at time t3. Here, line 5 and line 7 are in a grounded state. A voltage Vc1 is applied to the upper and lower electrodes of the capacitor 2 made of a paraelectric material by the signals B, W, and L1.
is caused by the capacitor 2 being charged during the time T2. The voltage Vc2 applied to the upper and lower electrodes of the capacitor 6 made of ferroelectric material is generated by being charged during the time T1 between time t3 and t4. As a result, the polarization of the capacitor 6, which was in the "0" state, was reversed to the "1" state. Signal B, Signal W
, signal L1 may start and end at any time, but a time T1 is required for each signal to overlap. Since the capacitor 6 is a capacitor made of ferroelectric material, it retains the information at time t4 even if the power is turned off after time t4. In the figure, the voltage after writing Vc2 is shown to decrease with a certain time constant, but this is because the polarization of the ferroelectric capacitor is compensated for by the charge in the wiring. When writing the "0" state to the DRAM, even if the transistor 8 is selected by the signal L1, polarization reversal will not occur because "0" has been written in the second capacitor 6 made of ferroelectric material in advance. , there is no change in the information of the first and second capacitors. For these write operations the word line 4 is always selected and the first transistor is in the on state.

Next, FIG. 6 shows a timing chart for writing a state of "1" in the case of transferring information of a DRAM cell to a nonvolatile cell. Signal L1 is input to line 9 at time t1, and word line 4 is not selected at this time.
Line 7 is in a grounded state. This action causes the first
The charge stored between the upper electrode and the lower electrode of the capacitor 2 is divided during a time T1 between time t1 and time t2 according to the capacitance ratio of the first capacitor and the second capacitor. When the electric field generated by the charges divided in the second capacitor is larger than the coercive electric field, the "1" information in the DRAM cell becomes non-volatile. At this time, the line 5 is in a grounded state, but it may be in a state where a positive voltage is applied. When writing the "0" state to the DRAM, even if the transistor 8 is selected by the signal L1, the polarization will not be reversed because the "0" information has been written in the second capacitor 6 made of ferroelectric material in advance. There is no change in the information on the first and second capacitors.

[0014] When reading information from non-volatile cells,
(1) There are cases in which information is read directly from the nonvolatile cell to the sense amplifier side, and (2) information in the nonvolatile cell is transferred to the DRAM cell. FIG. 7 shows a timing chart when reading information to the sense amplifier from a state in which "1" information is written in a nonvolatile cell. “1” in the nonvolatile cell section 12
To read from the state in which information has been written, use line 9.
A signal L1 is input to line 7 at time t1, and a signal L2 is input to line 7 at time t2. By the signals L1 and L2, the time t
2 to time t3, the second capacitor 6 is discharged due to polarization reversal. As a result, information "1" appears on bit line 1. The start and end times of the signals L1 and L2 do not matter whichever comes first, but a time T1 is required for each signal to overlap. When reading from a state in which "0" information is written in the non-volatile cell section, polarization inversion does not occur due to signal L2 in the timing chart of FIG. 7, so there is no charge in the first and second capacitors. It can be seen on the bit line that there is almost no movement and the information written in the nonvolatile cell section is "0". During this read operation, the word line 4 is always selected and the first transistor 3 is in an on state.

Next, FIG. 8 shows a timing chart for transferring information from the nonvolatile cell to the DRAM cell when information of "1" (state of 1 on the hysteresis curve in FIG. 4) is written in the nonvolatile cell. show. Signal L1 is input to line 9 at time t1, and signal L2 is input to line 7 at time t2. The polarization of the second capacitor 6 made of a ferroelectric material is inverted by the signal L2, and the state becomes "0" (state 3 of the hysteresis curve in FIG. 4). The capacitor 2 of 1 is charged and the information of the non-volatile cell is transferred to the DRAM cell. At this time, line 5 is grounded. Although it does not matter which time the signals L1 and L2 start and end first, a time T1 is required for each signal to overlap. When transferring information from the nonvolatile cell to the DRAM cell when "0" information is written in the nonvolatile cell section, the first capacitor is 2 is charged by the series connection of capacitor 6 and capacitor 2, but the amount of charged charge is smaller than when transferring "1" information. At this time, word line 4 is not selected and transistor 3 is off.

Next, the operation of the semiconductor integrated circuit shown in FIG. 2 will be explained. Transistor 3 on bit line 1
The source of the transistor 3 is connected to the word line 4, the drain of the first transistor 3 is connected to the upper electrode of the first capacitor 2 made of a paraelectric material, and the lower electrode of the capacitor 2 is connected to the word line 4. Connected to line 5. Further, the bit line 1 and the source of the second transistor 8 are connected, the gate electrode of the second transistor 8 is connected to the line 9, and the drain of the transistor 8 is connected to the upper electrode of the second capacitor 6 made of ferroelectric material. It is connected to the. The lower electrode of the capacitor 6 is connected to a line 7 in a circuit configuration. For convenience, the combination of bit line 1, word line 4, line 5, first transistor 3, and first capacitor 2 will be described below in the DRAM cell section 1.
1, line 7, line 9, second transistor 8, second
The combination of capacitors 6 will be referred to as a nonvolatile cell section 12. Here, the line 5 is for stabilizing the potential of the electrode connected to the capacitor 2 during write and read operations for the DRAM cell section 11. The line 7 is for stabilizing the potential of the electrode connected to the capacitor 6 during write and read operations for the nonvolatile cell section 12. Line 9 is for selecting the nonvolatile cell section 12. The bit line 1 is used for writing information into the DRAM cell section 11 and the nonvolatile cell section 12 and for reading information from the DRAM cell section 11 and the nonvolatile cell section 12. The word line 4 is for selecting the DRAM cell section 11.

When used as a volatile DRAM, the second transistor 8 is turned off, the DRAM cell section 11 and the nonvolatile cell section 12 are separated, and only the DRAM operation is performed. When backing up the storage information of the DRAM cell unit 11 to the nonvolatile cell unit 12, (1
There are two operations: (2) writing to both the DRAM cell and the nonvolatile cell at the same time during backup, and (2) moving the contents of the DRAM cell to the nonvolatile cell.

FIG. 9 shows a timing chart for writing "1" information into both the DRAM cell and the nonvolatile cell during backup. Signal B is input to bit line 1 at time t1, signal W is input to word line 4 at time t2, and signal L1 is input to line 9 at time t3. At this time, line 5 and line 7 are in a grounded state. Due to the signals B, W, and L1, the voltage Vc1 applied to the upper and lower electrodes of the capacitor 2 made of a paraelectric material increases at a time T2.
This is caused by the capacitor 2 being charged during this period. The voltage Vc2 applied to the upper and lower electrodes of the capacitor 6 made of ferroelectric material is generated by being charged during the time T1 between time t3 and t4. Since the capacitor 6 is a capacitor made of ferroelectric material, the polarization of the ferroelectric material is reversed at time T1, so that the polarization of the ferroelectric material is reversed at time t4.
Thereafter, even if the power is turned off, the information at time t4 is retained. Here, the start and end times of the signal B, the signal W, and the signal L1 do not matter which time comes first, but a time T1 is required for each signal to overlap. When writing the "0" state to the DRAM, even if the second transistor 8 is selected by the signal L1, "0" is written in the second capacitor 6 made of ferroelectric material in advance. There is no change in the information on the first and second capacitors.

Next, FIG. 10 shows a timing chart for writing "1" information in the case of transferring information in a DRAM cell to a nonvolatile cell. Signal L1 is applied to line 9 at time t1
, and line 7 is grounded. Due to this operation, the charge stored between the upper electrode and the lower electrode of the first capacitor 2 is divided into two parts during the time T1 between time t1 and time t2 according to the capacitance ratio of the first capacitor and the second capacitor. be done. DR when the electric field generated by the charge divided in the second capacitor 6 is larger than the coercive electric field
The "1" information in the AM cell is made non-volatile. At this time, the line 5 is in a grounded state, but it may also be in a state where a positive voltage is applied. When writing the “0” state to the DRAM, even if the transistor 7 is selected by the signal L1, since the “0” information has been written in the second capacitor 6 made of ferroelectric material in advance, the charge There is no movement, and there is no change in the information on the first and second capacitors. In these write operations, the word line 4 is always selected and the transistor 3 is in the on state. Furthermore, since the writing is performed via the bit line 1, the bit line 1 is in an electrically floating state during writing.

[0020] When reading information from non-volatile cells,
(1) There are cases in which information is read directly from the nonvolatile cell to the sense amplifier side, and (2) information in the nonvolatile cell is transferred to the DRAM cell. FIG. 11 shows a timing chart for reading out information to the sense amplifier when information "1" is written in a nonvolatile cell. A read operation from the non-volatile cell section 12 is performed by inputting the signal L1 to the line 9 at time t1 and inputting the signal L2 to the line 7 at time t2 in a state in which "1" information is written to the non-volatile cell section 12. do. Due to the signals L1 and L2, the capacitor 6 is discharged by polarization inversion like Vc2 during the time T1 from time t2 to time t3, so that information at the time of writing to the nonvolatile cell section appears on the bit line. At this time, word line 4 is not selected and the DRAM cell portion remains isolated. Here, the start and end times of the signal W and the signal L2 do not matter whichever comes first, but a time T1 is required for each signal to overlap. When reading from a state in which "0" information has been written in the nonvolatile cell section, polarization inversion does not occur due to the signal L2, so there is almost no charge transfer to the second capacitor and no charge is transferred to the nonvolatile cell section. It can be seen on bit line 1 that the stored information is "0".

Next, FIG. 12 shows a timing chart for transferring information from the nonvolatile cell section to the DRAM cell section when information "1" is written in the nonvolatile cell. Signal L1 is input to line 7 at time t1, and signal L is input to line 9.
2 is input at time t2. Time T1 due to L2 signal
During this time, the second capacitor 6 made of a ferroelectric material is polarized as Vc2 and discharged to the "0" state, but at this time, the first capacitor 2 is charged as Vc1, and the non-volatile cell information is written into the DRAM cell. At this time, line 5 is grounded. Here signal L1 and signal L
2 may start and end at any time, but a time T1 is required for each signal to overlap. When transferring information from the nonvolatile cell to the DRAM cell when "0" information is written in the nonvolatile cell section, the first Capacitor 2 is capacitor 6
is charged by the series combination of capacitor 2 and capacitor 2, but “1
”The amount of charged charge is smaller than when transferring information. In this read operation, word line 4 is always selected and transistor 3 is always on. Also, since it is performed via bit line 1, read sometimes bit line 1
is in an electrically floating state.

[0022]

As described above, according to the present invention, a volatile DRAM can be made into a non-volatile memory by adding one transistor and one ferroelectric capacitor. Since the non-volatile memory according to the present invention can be highly integrated relatively easily, it can also be used as a data memory for system settings, or as a memory for storing system parameter settings and the like before the system goes down.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram of a semiconductor integrated circuit according to the present invention. FIG. 2 is a diagram of another semiconductor integrated circuit according to the present invention. FIGS. 3A and 3B are diagrams of conventional semiconductor integrated circuits. FIG. 4 is a hysteresis characteristic diagram of a ferroelectric film. FIG. 5 is a timing chart of writing to a DRAM cell and a nonvolatile cell. FIG. 6 is a timing chart of writing from a DRAM cell to a nonvolatile cell. FIG. 7 is a timing chart of reading from a nonvolatile cell. FIG. 8 is a timing chart of writing from a nonvolatile cell to a DRAM cell. FIG. 9 is a timing chart of writing to a DRAM cell and a nonvolatile cell. FIG. 10 is a timing chart of writing from a DRAM cell to a nonvolatile cell. FIG. 11 is a timing chart of reading from a nonvolatile cell. FIG. 12 is a timing chart of writing from a nonvolatile cell to a DRAM cell. [Description of symbols] 1, 31, 41 Bit line 2 First capacitor 3 First transistor 4, 34, 42 Word line 5 First line 6 Second capacitor 7 Third line 8 Second transistor 9 Second line 11 DRAM cell section 12 Nonvolatile cell section

Claims (2)

[Claims] [Claim 1] A first electrode other than the gate electrode is provided on the bit line.
a first transistor to which a main electrode is connected, a first capacitor having one electrode connected to a second main electrode of the first transistor, and a first capacitor connected to the other electrode of the first capacitor. a first line connected to the gate electrode of the first transistor, a word line connected to the gate electrode of the first transistor, and a first main electrode other than the gate electrode of the second transistor connected to the second main electrode of the first transistor. A second capacitor made of a ferroelectric material, one electrode of which is connected to a second main electrode of the second transistor, and a gate electrode of the second transistor are connected. and a third line to which the other electrode of the second capacitor is connected. [Claim 2] A first electrode other than the gate electrode is provided on the bit line.
a first transistor to which a main electrode is connected, a first capacitor having one electrode connected to a second main electrode of the first transistor, and a first capacitor connected to the other electrode of the first capacitor. a word line connected to the gate electrode of the first transistor; a second transistor whose first main electrode other than the gate electrode is connected to the bit line; a second capacitor made of ferroelectric material connected to the second main electrode of the transistor; a second line connected to the gate electrode of the second transistor; and the other electrode of the second capacitor. A semiconductor integrated circuit consisting of a third line to which is connected.